DETAILED ACTION
This action is in response to the amendment filed 05/26/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 5-6, & 17 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claims 5 & 6 depends on the claim 4 which has been cancelled.
Claim 17 depends on claim 16 which has been cancelled.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Response to Arguments
Applicant's arguments filed 05/26/2026 have been fully considered but they are not persuasive.
Regarding claim 1, Applicant argues that Hwang does not disclose changing the target level according to a monitored level of the AC input voltage and the change in level is actually due to a rise in voltage across capacitor C15 (Remarks, pg. 1). The examiner respectfully disagrees.
Paragraph 0030 specifies “If the AC input voltage is higher than 380 volts DC, but lower than 440 volts DC, then the switching power supply can be expected to successfully commence operation” which does showcase that the AC input voltage is being monitored and the second target level is adjusted based on monitored AC voltage.
Furthermore, paragraph 0058 of Hwang discloses that “When an AC input voltage is detected, the switch S3 is opened. When the switches S2 and S3 are open, a voltage across the capacitor C15 slowly rises. While the voltage across C15 rises, the switch S1 is held closed by a comparator DISBF, which sets the target level of the PFC output VDC to its higher, initial level”. Thus, the target level is changed due to the voltage across C15, as the applicant argues, however this rise in voltage is reliant on the monitored AC level. Thus, the target level is changed according to a monitored level of the AC input voltage.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9, & 11-19 are rejected under 35 U.S.C. 103 as being unpatentable over US Doc ID. US2016322907A1 (Hereinafter Hwang) in view of CN Doc ID. CN215072181U (Hereinafter Hu) .
Regarding claim 1, Hwang discloses a switching power supply [e.g. Fig. 1, element 100] comprising: a first power supply stage [e.g. Fig. 1, element 102] configured to receive an AC input voltage [e.g. Fig. 1, element VAC] and to generate a DC output voltage [e.g. Fig. 1, element VO], wherein the DC output voltage of the first power supply stage [e.g. Fig. 1, element VDC] is set to a first target level during a light load condition and, otherwise, the DC output voltage is set to a second target level [e.g. paragraph 0006, “The initial target level can be higher than the second target level. The intermediate voltage can be set to a third target level under light loading conditions. The third target level can be lower than the second target level”], wherein the first power supply stage adjusts the second target level according to a monitored level of the AC input voltage [e.g. paragraph 0030, “For example, the steady-state target level for the PFC stage output can be 380 volts DC. Upon start-up of the switching power supply, the target level can be set to an elevated level, higher than 380 volts. For example, the initial elevated level can be 440 volts. If the AC input voltage is higher than 380 volts DC, but lower than 440 volts DC, then the switching power supply can be expected to successfully commence operation”; paragraph 0058, “When an AC input voltage is detected, the switch S3 is opened. When the switches S2 and S3 are open, a voltage across the capacitor C15 slowly rises. While the voltage across C15 rises, the switch S1 is held closed by a comparator DISBF, which sets the target level of the PFC output VDC to its higher, initial level”].
Hwang fails to disclose the second target level being lower than the first target level.
Hu teaches the second target level being lower than the first target level [e.g. paragraph 0047, “When the equivalent PFC load is light, the PFC output voltage increases; when the equivalent PFC load is heavy, the PFC output voltage decreases. The functions of the circuits are similar. Therefore, this conduction angle modulation method expands the conduction angle of the input rectifier diode, the AC input current iac and the AC input voltage vin have the same variation law, and the input current and the AC voltage can achieve the same frequency and the same phase, thus achieving AC/AC The power factor correction function of the DC converter achieves higher power factor and lower harmonic distortion of input current.”]
It would be obvious to someone having ordinary skill in the art, before the effective filing date, to modify Hwang wherein the switching power supply further includes the second target level being lower than the first target level as taught by Hu to improve the power factor and reduce harmonic distortion of the input current.
Regarding claim 2, Hwang discloses the switching power supply according to claim 1 [e.g. Fig. 1, element 100], wherein the first power supply stage [e.g. Fig. 1, element 102] performs power factor correction [e.g. paragraph 0003, “An exemplary off-line power supply includes a power factor correction (PFC) stage and a DC-to-DC converter stage. The PFC stage receives the AC input signal, performs rectification and maintains current drawn from the AC source substantially in phase with the AC voltage so that the power supply appears as a resistive load to the AC source.”] and further comprising a second power supply stage [e.g. Fig. 1, element 104] configured to receive the DC output voltage from the first power supply stage [e.g. Fig. 1, element VDC] and the second power supply stage being configured to generate a DC output voltage [e.g. Fig. 1, element VO] for the second power supply stage.
Regarding claim 3, Hwang discloses the switching power supply according to claim 1, wherein the second target level for the DC output voltage of the first power supply stage is variable [e.g. paragraph 0041, “The PFC switching controller 108 generates a signal PFCOUT which controls the opening and closing of the switches QA and QB so as to regulate the intermediate output voltage VDC while maintaining the input current in phase with the input voltage VAC . To accomplish this, the controller 108 uses the signal VFB, as well as the input current and voltage sensing signals IAC and Isense”].
Regarding claim 5, the switching power supply according to claim 4, wherein the second target level is not lower than a peak level of the AC input voltage [e.g. paragraph 0029, “This can occur if the AC input is higher than a target level set for the DC output of the PFC stage. The resulting lack of auxiliary power can cause the entire switching power converter to shut-down. For example, where the target level for the PFC output stage is 380 volts, and the AC input voltage is higher than 380 volts, this can result in a failure of the switching power supply to commence operation.”].
Regarding claim 6, the switching power supply according to claim 4, wherein the AC input voltage is monitored by the first power supply stage to determine the second target level [e.g. paragraph 0039, “A voltage sensing current signal IAC which is representative of the rectified input voltage Vrect flows through the resistor RAC and is received by the controller 108”; Fig. 3, IAC feeding into Gain Mod].
Regarding claim 7, the switching power supply according to claim 1, wherein the DC output voltage of the first power supply stage is regulated using a negative feedback loop [e.g. Fig 2, element 106] and wherein an error signal [e.g. Fig. 3, element VEAO] representative of a difference between a current target level for the DC output voltage of the first power supply stage and a monitored level of the DC output voltage [e.g. paragraph 0041, “The PFC switching controller 108 generates a signal PFCOUT which controls the opening and closing of the switches QA and QB so as to regulate the intermediate output voltage VDC while maintaining the input current in phase with the input voltage VAC . To accomplish this, the controller 108 uses the signal VFB, as well as the input current and voltage sensing signals IAC and Isense”].
Regarding claim 8, the switching power supply according to claim 7, wherein the error signal is monitored to detect the light loading condition [e.g. paragraph 0032, “A light load condition can be sensed by monitoring a signal, VEAO, which is an error signal that is representative of a difference between the actual level of the output voltage, VDC , and a desired level for the output voltage”].
Regarding claim 9, the switching power supply according to claim 1, wherein the first target level is approximately 380 volts DC [e.g. paragraph 0046. “The nominal level of the output, VDC , of the first stage 102 may be, for example, approximately 380 volts DC”].
Regarding claim 11, Hwang discloses a controller for switching power supply [e.g. Fig. 2, element 108], the controller comprising: a power factor correction circuit arrangement [e.g. Fig. 3, element 124] configured to control a switching element [e.g. Fig. 2, element QB] to generate a regulated DC output voltage [e.g. Fig. 2, element VDC] using a received AC input voltage [e.g. Fig. 2, element VAC], wherein a level of the regulated DC output voltage is variable according to a reference voltage [e.g. paragraph 0041, “The PFC switching controller 108 generates a signal PFCOUT which controls the opening and closing of the switches QA and QB so as to regulate the intermediate output voltage VDC while maintaining the input current in phase with the input voltage VAC . To accomplish this, the controller 108 uses the signal VFB, as well as the input current and voltage sensing signals IAC and Isense”]; and a detector circuit arrangement [e.g. Fig. 3, elements 114, GMV, Gain Mod, GM1, PFC comp] coupled to the power factor correction circuit arrangement and configured to detect a load condition [e.g. paragraph 0032, “A light load condition can be sensed by monitoring a signal, VEAO, which is an error signal that is representative of a difference between the actual level of the output voltage, VDC , and a desired level for the output voltage”] and to control the reference voltage according to the detected load condition [e.g. paragraph 0031, “When the steady-state target level is 380 volts DC, this can also be the target level for “full load” conditions. However, under light load conditions, the target level can be reduced to approximately 342 volts DC”], wherein the output voltage of the first power supply stage is set to a first target level in response to the load condition being light and, otherwise, the output voltage is set to a second target level [e.g. paragraph 0006, “The initial target level can be higher than the second target level. The intermediate voltage can be set to a third target level under light loading conditions. The third target level can be lower than the second target level”], wherein the controller is configured to adjust the second target level according to a monitored level of the AC input voltage [e.g. paragraph 0030, “For example, the steady-state target level for the PFC stage output can be 380 volts DC. Upon start-up of the switching power supply, the target level can be set to an elevated level, higher than 380 volts. For example, the initial elevated level can be 440 volts. If the AC input voltage is higher than 380 volts DC, but lower than 440 volts DC, then the switching power supply can be expected to successfully commence operation”; paragraph 0058, “When an AC input voltage is detected, the switch S3 is opened. When the switches S2 and S3 are open, a voltage across the capacitor C15 slowly rises. While the voltage across C15 rises, the switch S1 is held closed by a comparator DISBF, which sets the target level of the PFC output VDC to its higher, initial level”].
Hwang fails to disclose the second target level being lower than the first target level.
Hu teaches the second target level being lower than the first target level [e.g. paragraph 0047, “When the equivalent PFC load is light, the PFC output voltage increases; when the equivalent PFC load is heavy, the PFC output voltage decreases. The functions of the circuits are similar. Therefore, this conduction angle modulation method expands the conduction angle of the input rectifier diode, the AC input current iac and the AC input voltage vin have the same variation law, and the input current and the AC voltage can achieve the same frequency and the same phase, thus achieving AC/AC The power factor correction function of the DC converter achieves higher power factor and lower harmonic distortion of input current.”]
It would be obvious to someone having ordinary skill in the art, before the effective filing date, to modify Hwang wherein the switching power supply further includes the second target level being lower than the first target level as taught by Hu to improve the power factor and reduce harmonic distortion of the input current.
Regarding claim 12, the controller according to claim 11, wherein the power factor correction circuit arrangement is configured to generate an error signal [e.g. Fig. 3, element VEAO] wherein the error signal is representative of a difference between a current target level for the regulated DC output voltage and a monitored level of the DC output voltage [e.g. paragraph 0032, “A light load condition can be sensed by monitoring a signal, VEAO, which is an error signal that is representative of a difference between the actual level of the output voltage, VDC , and a desired level for the output voltage”].
Regarding claim 13, the controller according to claim 12, wherein the detector circuit arrangement monitors the error signal for detecting the load condition [e.g. paragraph 0032, “A light load condition can be sensed by monitoring a signal, VEAO, which is an error signal that is representative of a difference between the actual level of the output voltage, VDC , and a desired level for the output voltage”].
Regarding claim 14, the controller according to claim 11, further comprising a first power supply stage [e.g. Fig. 1, element 102] configured to generate the regulated DC output voltage [e.g. Fig. 1, element VDC] and further comprising a second power supply stage [e.g. Fig. 1, element 104] configured to receive the DC output voltage from the first power supply stage and the second power supply stage being configured to generate a DC output voltage [e.g. Fig. 1, element VO] for the second power supply stage.
Regarding claim 15, the controller according to claim 11, wherein the second target level for the DC output voltage is variable [e.g. paragraph 0041, “The PFC switching controller 108 generates a signal PFCOUT which controls the opening and closing of the switches QA and QB so as to regulate the intermediate output voltage VDC while maintaining the input current in phase with the input voltage VAC . To accomplish this, the controller 108 uses the signal VFB, as well as the input current and voltage sensing signals IAC and Isense”].
Regarding claim 17, the controller according to claim 16, wherein the second target level is not lower than a peak level of the AC input voltage [e.g. paragraph 0029, “This can occur if the AC input is higher than a target level set for the DC output of the PFC stage. The resulting lack of auxiliary power can cause the entire switching power converter to shut-down. For example, where the target level for the PFC output stage is 380 volts, and the AC input voltage is higher than 380 volts, this can result in a failure of the switching power supply to commence operation.”].
Regarding claim 18, the controller according to claim 17, wherein the AC input voltage is monitored by the controller to determine the second target level [e.g. paragraph 0039, “A voltage sensing current signal IAC which is representative of the rectified input voltage Vrect flows through the resistor RAC and is received by the controller 108” ; Fig. 3, IAC feeding into Gain Mod].
Regarding claim 19, the controller according to claim 11, wherein the first target level is approximately 380 volts DC [e.g. paragraph 0046. “The nominal level of the output, VDC , of the first stage 102 may be, for example, approximately 380 volts DC”].
Claims 10 & 20 are rejected under 35 U.S.C. 103 as being unpatentable over US Doc ID. US2016322907A1 (Hereinafter Hwang) in view of CN Doc ID. CN215072181U (Hereinafter Hu) and US Doc ID. US20080278092A1 (Hereinafter Lys).
Regarding claim 10, Hwang fails to disclose the switching power supply according to claim 1, wherein the second target level is within a range of approximately 162 volts DC to 311 volts DC.
Lys teaches wherein the second target level is within a range of approximately 162 volts DC to 311 volts DC [e.g. paragraph 0091, “The particular circuit component values illustrated in FIG. 14 provide an output voltage 32 on the order of approximately 300 VDC. In some implementations of lighting apparatus 500B employing the power supply 200B and a load including in LED-based light source, the power supply is configured such that the output voltage is nominally between 1.4 and 2 times the peak A.C. input voltage. The lower limit (1.4*) is primarily an issue of reliability; since it is worthwhile to avoid input voltage transient protection circuitry due to its cost, a fair amount of voltage margin may be preferred before current is forced to flow through the load. At the higher end (2*), it may be preferable in some instances to limit the maximum output voltage, since both switching and conduction losses increase as the square of the output voltage.”].
It would be obvious to someone having ordinary skill in the art, before the effective filing date, to modify Hwang wherein the controller further includes the second target level is 300 volts DC as taught by Lys to reduce switching and conduction losses.
Regarding claim 20, Hwang fails to disclose the controller according to claim 11, wherein the second target level is within a range of approximately 162 volts DC to 311 volts DC.
Lys teaches the controller according to claim 11, wherein the second target level is within a range of approximately 162 volts DC to 311 volts DC [e.g. paragraph 0091, “The particular circuit component values illustrated in FIG. 14 provide an output voltage 32 on the order of approximately 300 VDC. In some implementations of lighting apparatus 500B employing the power supply 200B and a load including in LED-based light source, the power supply is configured such that the output voltage is nominally between 1.4 and 2 times the peak A.C. input voltage. The lower limit (1.4*) is primarily an issue of reliability; since it is worthwhile to avoid input voltage transient protection circuitry due to its cost, a fair amount of voltage margin may be preferred before current is forced to flow through the load. At the higher end (2*), it may be preferable in some instances to limit the maximum output voltage, since both switching and conduction losses increase as the square of the output voltage.”].
It would be obvious to someone having ordinary skill in the art, before the effective filing date, to modify Hwang wherein the controller further includes the second target level is 300 volts DC as taught by Lys to reduce switching and conduction losses.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US12062989B2 - Hwang- POWER CONVERTER AND CONTROLLER FOR A POWER CONVERTER AND MANNERS OF OPERATION THEREOF
US20080025052A1 – Yasumura – Switching Power Supply Circuit
CN112865549A – Xu - Constant-current control method for asymmetric half-bridge flyback converter with primary side modulation function
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARED RAYMOND HAUSMAN whose telephone number is (571)272-6139. The examiner can normally be reached M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at 5712721838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MONICA LEWIS/Supervisory Patent Examiner, Art Unit 2838
/JARED RAYMOND HAUSMAN/Examiner, Art Unit 2838
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