DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Applicant’s amendments, filed on 06/22/2026 regarding rejection of claims 1-20 has been considered and entered.
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the arguments do not apply to new combinations of references including new prior arts being used in the current rejection. The new grounds of rejection are necessitated by amendment.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 -4, 6, 1012-15, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Biederman et al. (US 20230077631 A1)hereinafter Biederman and further in view of Lesi et al. (US 20240223603 A1) hereinafter Lesi
As to claim 1. Biederman A network device including ([0015] Fig. 1, a network device)
a host interface to couple to a host device via a peripheral communication ([0015] Fig. 1, Host systems and devices 150 can be communicatively connected to network interface device 100 using a host or device interface (e.g., Peripheral Component Interconnect express (PCIe),)
data bus to receive time synchronization messages ([0034] [0041] Fig. 1, Fig. 2, network interface device 250 can receive timing signal or sync message via bus ) and schedule data generated by software executed by a processing unit of the host device; ([0066] Fig. 10, schedule data by executing software in the memory by cpu)
scheduler circuitry to manage ([0066] Fig. 10, infrastructure processing unit (IPU
scheduling circuit manages)
Biederman does not teach a hardware clock to maintain a clock time;
periodic transmission of the time synchronization messages according to the clock time, and the schedule data provided by the software; a network interface to transmit the time synchronization messages to at least one clock synchronization follower, according to the schedule data and the clock time
Lesi teaches a hardware clock to maintain a clock time; ;([0063] Fig. 4, Nodes hardware platform 408 may include, among other hardware components, a network interface such as a transceiver 410, clock circuitry 412, processing circuitry 414 and memory 416/maintain hardware clock.)
periodic transmission of the time synchronization messages according to the clock time ([0035] A TSN periodically sends messages with time information from a clock leader node to one or more clock follower nodes)
and the schedule data provided by the software; ([0055] [0074] Fig. 2A, Fig. 4, TSN node implementing the software platform 402 and/or the hardware platform 408,Leader node and follower node synchronizes clock, then leader node scheduling traffic, )and
a network interface to transmit the time synchronization messages to at least one clock synchronization follower ([0081]Fig. 1A, The time-synchronized networks TSN node 104a sends messages 112 with time information 418 to synchronize or syntonize the clock 108b)
according to the schedule data and the clock time. ([0055][0058] Fig. 2A,Fig. 2B, , to facilitate transmission of packets e.g., packet 212, etc. , master and slave nodes are time synchronized and scheduled to transmit TC packets (e.g., packet 212, etc.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine teaching of Lesi with the teaching of Biederman because Lesi teaches that systems based on time-synchronized networks (TSNs) enables time synchronization and deterministic data delivery in converged networks where time sensitive traffic coexists with other types of traffic. (Lesi [0032])
As to claim 12. Biederman teaches comprising: receiving , via a peripheral
communication data bus from a host device, time synchronization messages communication ([0015] [0034] [0041] Fig. 1, Fig. 2,Host systems and devices 150 can be communicatively connected to network interface device 100 using a host or device interface (e.g., Peripheral Component Interconnect express (PCIe), receive timing signal or sync message via data bus)
and schedule data provided by the software([0066] Fig. 10, infrastructure processing unit (IPU) perform scheduling data with CPU using software)
and schedule data generated by software executed by a processing unit of the host device; ([0066] Fig. 10, schedule data by executing software in the memory by cpu)
Biederman does not teach; maintaining a clock time; managing periodic transmission of the time synchronization messages according to the clock time, and schedule data provided by the software; transmitting the time synchronization messages to at least one clock synchronization follower
maintaining a clock time; ;([0063] Fig. 4, Nodes hardware platform 408 may include, among other hardware components, a network interface such as a transceiver 410, clock circuitry 412, processing circuitry 414 and memory 416/maintain hardware clock.)
managing periodic transmission of the time synchronization messages according to the clock time([0035] A TSN periodically sends messages with time information from a clock leader node to one or more clock follower nodes)
and transmitting the time synchronization messages to at least one clock synchronization follower. ([0081]Fig. 1A, The time-synchronized networks TSN node 104a sends messages 112 with time information 418 to synchronize or syntonize the clock 108b) according to the schedule data and the clock time ([0055][0058] Fig. 2A,Fig. 2B, , to facilitate transmission of packets e.g., packet 212, etc. , master and slave nodes are time synchronized and scheduled to transmit TC packets (e.g., packet 212, etc.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine teaching of Lesi with the teaching of Biederman because Lesi teaches that systems based on time-synchronized networks (TSNs) enables time synchronization and deterministic data delivery in converged networks where time sensitive traffic coexists with other types of traffic. (Lesi [0032])
As to claim 2. The combination of Biederman and Lesi specifically Biederman teaches wherein the scheduler circuitry is to manage ([0066] Fig. 10, infrastructure processing unit (IPU) scheduling circuit manages) a first one of the time synchronization messages provided by the software and a given periodic time or frequency provided by the software.([0013] [0018] Fig. 1, host systems and devices 150 can provide clock signals 0 to n as inputs TimedIO_0 to TimedIO_n, where n is an integer and n>1, to network interface device 100; and perform time signal synchronization of servers and monitor variances of time signals used by servers from a reference clock signal)
Biederman does not teach the periodic transmission of the time synchronization messages according to a transmission time
Lesi teaches the periodic transmission of the time synchronization messages according to a transmission time of [0035] TSN periodically sends messages with time information from a clock leader node to one or more clock follower nodes)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine teaching of Lesi with the teaching of Biederman because Lesi teaches that systems based on time-synchronized networks (TSNs) enables time synchronization and deterministic data delivery in converged networks where time sensitive traffic coexists with other types of traffic. (Lesi [0032])
Claim 13 is/are interpreted and rejected for the same reasons as set forth in claim 2.
As to claim 3. The combination of Biederman and Lesi specifically Biederman teaches , wherein the time synchronization messages are sync messages according to Precision Time Protocol (PTP).([0014] , such as in a warehouse computer or one or more data centers, the reference clock signal can be synchronized with a main clock signal using Institute of Electrical and Electronics Engineers (IEEE) 1588 Precision Time Protocol (PTP)
Claim 14 is/are interpreted and rejected for the same reasons as set forth in claim 3.
As to claim 4. The combination of Biederman and Lesi specifically Biederman teaches wherein the scheduler circuitry is to manage ([0065][0066] Fig. 10, infrastructure processing unit (IPU) scheduling circuit manages, process packets that are to be transmitted from network interface)
transmission of each of the time synchronization messages([0079] Fig. 6, time information 418 may include information to synchronize a first clock 108a for the TSN node 104a and a second clock 108b for the TSN node 104b to a network time for the TSN 102 maintained by the first clock 108a)
according to a scheduled transmission time assigned by the software for each of the time synchronization messages.([0013] [0018] [0019]Fig. 1, host systems and devices 150 can provide clock signals 0 to n as inputs TimedIO_0 to TimedIO_n, where n is an integer and n>1, to network interface device 100; an provide clock signals 0 to n based on a time stamp counter; and perform time signal synchronization of servers and monitor variances of time signals used by servers from a reference clock signal)
Claim 15 is/are interpreted and rejected for the same reasons as set forth in claim 4.
As to claim 6. The combination of Biederman and Lesi specifically Biederman teaches wherein the scheduler circuitry is to manage ([0065][0066] Fig. 10, infrastructure processing unit (IPU) scheduling circuit manages, process packets that are to be transmitted from network interface)
according to a given periodic time or frequency provided by the software. .([0013] [0018] [0019]Fig. 1, host systems and devices 150 can provide clock signals 0 to n as inputs TimedIO_0 to TimedIO_n, where n is an integer and n>1, to network interface device 100; an provide clock signals 0 to n based on a time stamp counter; and perform time signal synchronization of servers and monitor variances of time signals used by servers from a reference clock signal)
Biederman does not teach the periodic transmission of the time synchronization messages
Lesi teaches the periodic transmission of the time synchronization messages ([0035] A TSN periodically sends messages with time information from a clock leader node to one or more clock follower nodes)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine teaching of Lesi with the teaching of Biederman because Lesi teaches that systems based on time-synchronized networks (TSNs) enables time synchronization and deterministic data delivery in converged networks where time sensitive traffic coexists with other types of traffic. (Lesi [0032])
Claim 17 is/are interpreted and rejected for the same reasons as set forth in claim 6.
As to claim 10. The combination of Biederman and Lesi specifically Biederman teaches
wherein the network device includes an application-specific integrated circuit (ASIC), which includes the scheduler circuitry. ([0066] motherboard or circuit board that includes a CPU, including application specific integrated circuits (ASICs), provide scheduling functions)
Claim(s) 5, 7, 16, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Beiderman Lesi and further in view of Mula et al. (US 20210409137 A1) hereinafter Mula
As to claim 5. The combination of Biederman and Lesi specifically Biederman teaches wherein the scheduler circuitry is to manage([0065][0066] Fig. 10, infrastructure processing unit (IPU) scheduling circuit manages, process packets that are to be transmitted from network interface)
Biederman does not teach further comprising the host device including the processing unit to execute the software to generate the time synchronization messages; the periodic transmission of the time synchronization messages; and associated work descriptors having corresponding transmission times at which the time synchronization packets are to be transmitted to the at least one clock synchronization follower,
according to the corresponding transmission times of the associated work descriptors and the clock time of the hardware clock.
Lesi teaches further comprising the host device including the processing unit to execute the software to generate the time synchronization messages ([0068]Fig. 6, memory to store instructions that when executed by the processor circuitry,; the clock manager 106 may send a message 112 with time information 418 representing a current network time; analyzes the time information 418, and determines whether to adjust a parameter (e.g., phase or frequency) of the clock circuitry 412 to synchronize the clock circuitry 412 to the current network time.
the periodic transmission of the time synchronization messages ([0035] A TSN periodically sends messages with time information from a clock leader node to one or more clock follower nodes)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine teaching of Lesi with the teaching of Biederman because Lesi teaches that systems based on time-synchronized networks (TSNs) enables time synchronization and deterministic data delivery in converged networks where time sensitive traffic coexists with other types of traffic. (Lesi [0032])
The combination of Biederman and Lesi does not teach and associated work descriptors having corresponding transmission times at which the time synchronization packets are to be transmitted to the at least one clock synchronization follower,
according to the corresponding transmission times of the associated work descriptors and the clock time of the hardware clock.
Mula teaches and associated work descriptors having corresponding transmission times at which the time synchronization packets are to be transmitted to the at least one clock synchronization follower,([0104] [0106] Fig. 5, Fig. 6, time stamps are provided to (outgoing) packets by the adjusted PTP time unit 520, such as to packets 465 and 475 in PTP time format/sync packets, each of the plurality of packets is associated with a packet descriptor; at least one of the packet descriptors is a transmission time packet descriptor including a desired physical transmission time for the packet associated with the transmission time packet descriptor)
according to the corresponding transmission times of the associated work descriptors and the clock time of the hardware clock. ([0054][0075] Fig. 1,control plane 140 is configured to choose particular packets which are to be sent at an exact time and to mark said packets, generally in a descriptor; circuitry keeping the real-time hardware clock 185 synchronized to UTC using PTP )
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine teaching of Mula with the teaching of Biederman and Lesi because Mula teaches that utilizing time in PTP format would enable better scheduling in accordance with a specific time.(Mula [0104])
Claim 16 is/are interpreted and rejected for the same reasons as set forth in claim 5.
As to claim 7 The combination of Biederman and Lesi specifically Biederman teaches further comprising the host device including the processing unit to execute the software to ([0066] Fig. 10, schedule data by executing software in the memory by cpu)
Biederman does not teach provide the given periodic time or frequency to the scheduling circuitry, generate the time synchronization messages and associated work descriptors; add the work descriptors to a work queue designated for transmitting the time synchronization messages
Lesi teaches provide the given periodic time or frequency to the scheduling circuitry.
provide the given periodic time or frequency to the scheduling circuitry. ([0035] 0055] [0074] Fig. 2A, Fig. 4 A TSN periodically sends messages with time information from a clock leader node to one or more clock follower nodes; then leader node scheduling traffic)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine teaching of Lesi with the teaching of Biederman because Lesi teaches that systems based on time-synchronized networks (TSNs) enables time synchronization and deterministic data delivery in converged networks where time sensitive traffic coexists with other types of traffic. (Lesi [0032])
The combination of Biederman and Lesi does not teach generate the time synchronization messages and associated work descriptors; add the work descriptors to a work queue designated for transmitting the time synchronization messages
Mula teaches generate the time synchronization messages and associated work descriptors; add the work descriptors to a work queue designated for transmitting the time synchronization messages; ,([0104] [0106] Fig. 5, Fig. 6, time stamps are provided to (outgoing) packets by the adjusted PTP time unit 520/generate packets, , such as to packets 465 and 475 in PTP time format/sync packets, each of the plurality of packets is associated with a packet descriptor; at least one of the packet descriptors is a transmission time packet descriptor including a desired physical transmission time for the packet associated with the transmission time packet descriptor)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine teaching of Mula with the teaching of Biederman and Lesi because Mula teaches that utilizing time in PTP format would enable better scheduling in accordance with a specific time.(Mula [0104])
Claim 18 is/are interpreted and rejected for the same reasons as set forth in claim 7
Claim(s) 8 11 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Biederman , Lesi and further in view of Ruelke et al. (US 20220240108 A1) hereinafter Ruelke
As to claim 8. The combination of Biederman and Lesi specifically Lesi teaches wherein: the time synchronization messages are to be transmitted to multiple time synchronization followers; ([0033][0035] A TSN periodically sends messages with time information to synchronize the hardware clock, from a clock leader node to one or more clock follower nodes)
and
the scheduler circuitry is to manage transmission of the time synchronization messages ([0068]Fig. 6, memory to store instructions that when executed by the processor circuitry,; the clock manager 106 may send a message 112 with time information 418 representing a current network time; analyzes the time information 418, and determines whether to adjust a parameter (e.g., phase or frequency) of the clock circuitry 412 to synchronize the clock circuitry 412 to the current network time)
The combination of Biederman and Lesi does not teach according to an interleaved time schedule such that the time synchronization messages to be transmitted to different ones of the time synchronization followers are transmitted at different times.
Ruelke teaches according to an interleaved time schedule such that the time synchronization messages to be transmitted to different ones of the time synchronization followers are transmitted at different times. ([0053]Fig. 4, the sync symbol, frame timing, and resource block assignments may be different for each 5G/LTE communication device 105 such that each 5G/LTE communication device 105 is interleaved in time and frequency with other 5G/LTE communication devices 105 )
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine teaching of Ruelke with the teaching of Biederman and Lesi because Ruelke teaches that interleaving sync symbol frame timing would realize tandem access to the 5G/LTE base station without interference between individual 5G/LTE communication devices. (Ruelke [0053]).
Claim 19 is/are interpreted and rejected for the same reasons as set forth in claim 8.
As to claim 11 The combination of Biederman and Ruelke specifically Ruelke teaches , wherein the scheduler circuitry includes a hardware accelerator and/or a microcontroller to run firmware. ([0055][0099]Fig. 3, Fig. 4, base station assigns sync symbol, frame timing, and resource block, base station includes specialized processors (or “processing devices”) and unique stored program instructions (including both software and firmware) that control the one or more processors)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine teaching of Ruelke with the teaching of Biederman and Lesi because Ruelke teaches that interleaving sync symbol frame timing would realize tandem access to the 5G/LTE base station without interference between individual 5G/LTE communication devices. (Ruelke [0053]).
Claim(s) 9, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Biederman and further in view of Shibuta et al. (US 20170127364 A1) hereinafter Shibuta
As to claim 9 The combination of Biederman and Lesi does not teach wherein the scheduler circuitry is comprised in a hardware accelerator.
Shibuta teaches wherein the scheduler circuitry of master node, is comprised in a hardware accelerator. ([0045] Fig. 2, Synchronization control hardware 112 includes a hardware accelerator that conforms to IEEE 1588 Ver. 2. Synchronization control hardware 112 has a hardware function for generating a clock, and synchronizing time information)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to combine teaching of Shibuta with the teaching of Biederman and Lesi because Shibuta teaches that by using individual time slots , it would be possible to improve synchronization accuracy between cell stations and slave stations. (Shibuta [0109])
Claim 20 is/are interpreted and rejected for the same reasons as set forth in claim 9
Conclusion
5. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Rentschler; Michael [US 20190386763 A1] Performing PHY-Level Hardware Timestamping and Time Synchronization in Cost-Sensitive Environments
Edens; Glenn T. et al. [US 6611537 B1] Synchronous network for digital media streams
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ATIQUE AHMED whose telephone number is (571)272-6244. The examiner can normally be reached 9:30 - 7:30 PM M-F Eastern.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Un Cho can be reached at 5712727919. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ATIQUE AHMED/Primary Examiner, Art Unit 2413
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