Prosecution Insights
Last updated: July 17, 2026
Application No. 18/631,132

CLASS-D AMPLIFIER DEVICE FOR HAPTIC APPLICATIONS

Non-Final OA §102§103§112
Filed
Apr 10, 2024
Priority
Oct 12, 2023 — provisional 63/543,859
Examiner
NGUYEN, LONG T
Art Unit
Tech Center
Assignee
Microchip Technology Incorporated
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
833 granted / 934 resolved
+29.2% vs TC avg
Moderate +8% lift
Without
With
+8.2%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 10m
Avg Prosecution
32 currently pending
Career history
968
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
27.5%
-12.5% vs TC avg
§102
36.4%
-3.6% vs TC avg
§112
27.4%
-12.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 934 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections Claims 1-16 are objected to because of the following informalities: Claim 1, line 5, “signal a non-overlapped” should be changed to “signal comprising a non-overlapped”. Claims 2-6 are objected to because they depend on claim 1. Claim 7, line 7, “signal a non-overlapped” should be changed to “signal comprising a non-overlapped”. Claims 8-11 are objected to because they depend on claim 7. Claim 12, line 6, “signal an” should be changed to “signal comprising an”. Claims 13-16 are objected to because they depend on claim 12. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. For claim 1, the recitation “a common node” on line 23 is unclear antecedent basis because it is not clear if it refers to “a common node” recited earlier on line 20 of the claim. It is suggested that “a common node” on line 23 should be changed to “the common node”. Clarification and/or appropriate correction is required. Claim 2-6 are indefinite because they depend on claim 1. For claims 7 and 12, these claims are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are: there is no connection of “a haptic actuator” (line 3 of claim 7, and line 2-3 of claim 12) with any other elements in the claims, so it is not clear where “a haptic actuator” being connected. Clarification and/or appropriate correction is required. Claims 8-11 and 13-16 are indefinite because they depend on claims 7 and 12, respectively. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-3, 5-10, 12-14 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ishizaki (US 2007/0079710). For claim 1, Figures 2 and 6 of Ishizaki (where Figure 2 is detail of amplifier 13 in Figure 6, see [0035]) teaches a class-D amplifier device comprising: a PWM controller circuit (11-12, C1, R1-R2 in Figure 6, and C21, D2, R21-R22, Q21-Q24, C11, D11, R11-R12, and Q11-Q14 in Figure 2), the PWM controller circuit (11-12, C1, R1-R2 in Figure 6, and C21, D2, R21-R22, Q21-Q24, C11, D11, R11-R12, and Q11-Q14 in Figure 2) to receive an input signal (DRIVING SIGNAL) and to generate a first PWM signal (signal at junction node of Q13-Q14, see [0034]) and a second PWM signal (signal at junction node of Q23-Q24) based on the input signal, the first PWM signal (signal at junction node of Q13-Q14) comprising a fixed-frequency PWM signal and the second PWM signal (signal at junction node of Q23-Q24) comprising a non-overlapped version of the first PWM signal; a first plate of a first coupling capacitor (C12) coupled to receive the first PWM signal; a first plate of a second coupling capacitor (C22) coupled to the receive the second PWM signal; a driver circuit (Q15, Q25) comprising a high-side device (Q15) coupled to a second plate of the first coupling capacitor (C12) and a low-side device (Q25) coupled to a second plate of the second coupling capacitor (C22), the driver circuit (Q15, Q25) to drive an output node (51 in Figure 2 which is output of 13 in Figure 6), and a filter circuit (14, 18, 2) coupled to the output node (51), the filter circuit comprising: a filter capacitor (C6); an inductor (L1); and a haptic actuator (221-22n); wherein the filter capacitor (C6) comprises a first plate (top) coupled to the output node (output of 13) and a second plate (bottom) coupled to a common node (ground GND), the inductor (L1) comprises a first node (left) coupled to the output node (output of 13), and a second node (right) coupled to a first node (top) of the haptic actuator (221-22n), and the second node (bottom) of the haptic actuator (221-22n) coupled to the common node (GND). For claim 2, Figure 2 of Ishizaki teaches the high-side device (Q15) comprising a MOSFET (Q15). For claim 3, Figure 2 of Ishizaki teaches the low-side device (Q25) comprising a MOSFET (Q25). For claim 5, Figure 6 of Ishizaki teaches the input signal (DRIVING SIGNAL) comprising a bursted sinusoidal signal (DRIVING SIGNAL, see Figure 11), the bursted sinusoidal signal (DRIVING SIGNAL, see Figure 11) based on a desired haptic response. For claim 6, Figure 6 of Ishizaki teaches the haptic actuator (221-22n) comprising a piezoelectric actuator (221-22n). For claim 7, Figures 2 and 6 of Ishizaki (where Figure 2 is detail of amplifier 13 in Figure 6, see [0035]) teaches a system comprising: a microcontroller (the controller that generates DRIVING SIGNAL in Figure 6) to generate an input signal (output of 12), the input signal to generate a haptic response at a haptic actuator (221-22n); a PWM controller circuit (11-12 in Figure 6, and C21, D2, R21-R22, Q21-Q24, C11, D11, R11-R12, and Q11-Q14 in Figure 2), the PWM controller circuit to receive the input signal (DRIVING SIGNAL) and to generate a first PWM signal (signal at junction node of Q13-Q14, see [0034]) and a second PWM signal (signal at junction node of Q23-Q24) based on the input signal (DRIVING SIGNAL), the first PWM signal (signal at junction node of Q13-Q14, see [0034]) comprising a fixed-frequency PWM signal and the second PWM signal (signal at junction node of Q23-Q24) comprising a non-overlapped version of the first PWM signal; a coupling circuit (C12 and C22 in Figure 2) to couple the first PWM signal (signal at junction node of Q13-Q14) and second PWM signal (signal at junction node of Q23-Q24) to a driver circuit (Q15, Q25), the driver circuit comprising a high-side device (Q15) and a low-side device (Q25), and the driver circuit to drive an output node (51 in Figure 2 which is output of 13 in Figure 6), and a filter circuit (14, 18, 2) communicatively coupled to the output node (output of 13), the filter circuit (14, 18, 2) to filter the output node (output of 13). For claim 8, Figure 2 of Ishizaki teaches the coupling circuit (C12, C22) comprising a first coupling capacitor (C12) coupled between the first PWM signal (signal at junction node of Q13-Q14) and the high-side device (Q15) and comprising a second coupling capacitor (C22) coupled between the second PWM signal (signal at junction node of Q23-Q24) and the low-side device (Q25). For claim 9, Figure 6 of Ishizaki teaches the input signal (DRIVING SIGNAL) comprising a bursted sinusoidal signal (DRIVING SIGNAL, see Figure 11), the bursted sinusoidal signal (DRIVING SIGNAL, see Figure 11) based on a desired haptic response. For claim 10, Figure 6 of Ishizaki teaches the haptic actuator (221-22n) comprising a piezoelectric actuator (221-22n). For claim 12, Figures 2 and 6 of Ishizaki (where Figure 2 is detail of amplifier 13 in Figure 6, see [0035]) teaches a method comprising: receiving an input signal (DRIVING SIGNAL, Figure 6), the signal to produce a haptic response at a haptic actuator (221-22n); converting the input signal (DRIVING SIGNAL) to a first PWM signal (signal at junction node of Q13-Q14, see [0034]) and a second PWM signal (signal at junction node of Q23-Q24), the first PWM signal (signal at junction node of Q13-Q14) comprising a fixed-frequency PWM signal and the second PWM signal (signal at junction node of Q23-Q24) an inverted and non-overlapped version of the first PWM signal (signal at junction node of Q13-Q14); coupling the first PWM signal (signal at junction node of Q13-Q14) to a first coupling capacitor (C12) and coupling the second PWM signal (signal at junction node of Q23-Q24) to a second coupling capacitor (C22); driving a driver circuit (Q15, Q25) with the outputs of the first coupling capacitor (C12) and the second coupling capacitor (C22); filtering the output of the driver circuit (51 in Figure 2 which is output of 13 in Figure 6) with a filter circuit (14, 18, 2). For claim 13, Figure 6 of Ishizaki teaches the input signal (DRIVING SIGNAL) comprising a bursted sinusoidal signal (DRIVING SIGNAL, see Figure 11), the bursted sinusoidal signal (DRIVING SIGNAL, see Figure 11) based on a desired haptic response. For claim 14, Figure 2 of Ishizaki teaches the driver circuit (Q15, Q25) comprising a high-side device (Q15) and a low-side device (Q25). For claim 16, Figure 6 of Ishizaki teaches the haptic actuator (221-22n) comprising a piezoelectric actuator (221-22n). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 4, 11, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Ishizaki (US 2007/0079710) in view of May et al. (US 2020/0235712). For claim 4, Figure 2 of Ishizaki teaches the high-side device (Q15) receives a supply voltage from a high-voltage supply (91) wherein the high-voltage supply (91) greater than or equal to 10 Volts (+40V). Figure 2 of Ishizaki does not teach the high-voltage supply (91) is from a boost converter, wherein the boost converter to convert a battery voltage to the high-voltage supply. However, Figure 2 of May et al. teaches a high-volage supply (VBST) is generated from a boost converter (210) that converts a battery voltage (200) to generate the high-volage supply (VBST). Therefore, it would have been obvious to one having ordinary skilled in the art at the time before the invention was effectively filed to modify the circuitry in Figure 2 of Ishizaki to use a boost converter (210) that converts a battery voltage (200) to generate a high-volage supply (VBST), as taught by May et al., for the high-side device (Q15) to receive a supply-voltage for the purpose of improving the performance of the circuitry (see [0045], May et al.). Thus, this combination/modification teaches all the limitation of claim 4. For claims 11 and 15, the combination/modification as discussed in claim 4 above also teaches the driver circuit (Q15, Q25) to receive a supply voltage from a boost converter (210, May et al.), and the high-side device (Q15) to receive a power supply voltage (VBST) from a boost converter (210, May et al.). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kanoh et al. (USP 7,268,621) discloses a digital amplifier (Class-D amplifier). Any inquiry concerning this communication or earlier communications from the examiner should be directly to Examiner Long Nguyen whose telephone number is (571) 272-1753. The Examiner can normally be reached on Monday to Friday from 8:30am to 5:00pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch, can be reached at (571) 270-7101. The fax number for this group is (571) 273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. /Long Nguyen/ Primary Examiner Art Unit 2836
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Prosecution Timeline

Apr 10, 2024
Application Filed
Jun 16, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
97%
With Interview (+8.2%)
1y 10m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 934 resolved cases by this examiner. Grant probability derived from career allowance rate.

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