Prosecution Insights
Last updated: July 17, 2026
Application No. 18/631,284

LOCAL CLOCK DRIVEN DETUNE ON A CONTINUOUS CLOCK GRID

Final Rejection §103
Filed
Apr 10, 2024
Examiner
NGUYEN, PHIL K
Art Unit
2176
Tech Center
2100 — Computer Architecture & Software
Assignee
International Business Machines Corporation
OA Round
2 (Final)
82%
Grant Probability
Favorable
3-4
OA Rounds
4m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
450 granted / 546 resolved
+27.4% vs TC avg
Moderate +14% lift
Without
With
+14.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
13 currently pending
Career history
564
Total Applications
across all art units

Statute-Specific Performance

§101
3.1%
-36.9% vs TC avg
§103
69.7%
+29.7% vs TC avg
§102
20.1%
-19.9% vs TC avg
§112
2.1%
-37.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 546 resolved cases

Office Action

§103
DETAILED ACTION Claims 1 – 20 are pending. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action: (a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made. Claims 1-3, 9-10, 16-17 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Jung et al (US Publication 20160162001 A1) and in view of Yoshida et al (US Publication 20120161833) and in further view of MARGALIT (US Publication 20210382520). The teachings of Jung as disclosed in the previous office action are hereby incorporated by reference to the extent applicable to the amended claims. Applicant has amended independent claims 1, 9 and 16 to incorporate the limitations that (1) wherein reducing the strength of the clock buffer comprises: receiving, by the clock buffer from an associated memory register, a strength value that controls the reduced strength of the clock signal to the circuitry; and (2) maintaining the clock signal of the clock buffer and the other clock buffers in a synchronous state. Regarding limitation (1), Jung does not disclose the amended limitation (1) above. Yoshida discloses (1) wherein reducing the strength of the clock buffer [PLL] comprises: receiving, by the clock buffer from an associated memory register [register 132], a strength value that controls the reduced strength of the clock signal to the circuitry [0055: The CPU 126 sets a self-oscillation flag in the self-oscillation flag setting register 132. For example, the self-oscillation flag is set to logical "0" if the PLL circuit 121 is in the PLL normal-oscillation mode, and the self-oscillation flag is set to logical "1" if the PLL circuit 121 is in the PLL self-oscillation mode] [0063: In the PLL self-oscillation mode, the frequency of the clock signal output from the PLL circuit 121 is fixed to a frequency lower than that in the PLL normal-oscillation mode, which is supplied to each part in the microcomputer 1 via the frequency divider 122. In the PLL self-oscillation mode, since the frequency of the clock signal output from the PLL circuit 121 is fixed to a frequency lower than that in the PLL normal-oscillation mode, power consumption is reduced in comparison with the PLL normal-oscillation mode]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Jung and Yoshida together because they both directed to supply the clock signals to the circuits. Yoshida’s disclosing of lowering the PPL clock to the circuit based on the value stored in the register would allow Jung to accurately control the clock signal to the corresponding circuit based on the register stored value Margalit discloses (2) maintaining the clock signal of the clock buffer and the other clock buffers in a synchronous state [0013: three reference clocks 130, 132, and 134; and three clock domains 140; 142; and 144 (which are synchronized to reference clocks 130, 132, and 134, respectively). As shown in FIG. 1, the three clock domains (140, 142, 144) are shared among the seven blocks of ASIC 100 (110, 112, 114, 116, 118, 120, 122) such that multiple blocks (e.g., blocks 110, 112, 114) are synchronized to the same clock domain (e.g., clock domain 140). Blocks synchronized to the same clock domain enjoy benefits such as the elimination of clock drift (obviating the need to synchronize blocks to independent clocks). In such systems, data can be transmitted synchronously between two blocks within the same clock domains (e.g., between block 110 and block 112 in the example)]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Jung and Yoshida together for the same reasons as disclosed above. It would have further been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Margalit into the disclosures of Jung and Yoshida because they all directed to control the clocks to the corresponding circuits. Margalit’s disclosing of synchronizing the clock domains would allow Jung in view of Yoshida to increase the method’s efficiency by allowing each clock domains operate in a synchronous manner. Regarding claims 2,3,10 and 17, these claims are taught by Jung as set forth in the previous office action. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 4-8, 11-15, 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jung et al (US Publication 20160162001 A1) in view of Yoshida et al (US Publication 20120161833) in further view of MARGALIT (US Publication 20210382520) and in further view of Alleyne et al (US Publication 20250190046 A1). Regarding claims 4-8, 11-15, 18-20, the base claims 1, 9 and 16 are taught by Jung in view of Yoshida and further in view of Margalit as disclosed above and the additional limitations in claims 4-8, 11-15, 18-20 are taught by Alleyne as disclosed in the previous office action. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Jung, Yoshida and Margalit as disclosed above. It would have further been obvious before the effective filing date of the claimed invention to combine the teachings of Alleyne for the same reasons as disclosed in the previous office action. Response to Arguments Applicant’s arguments filed on 03/24/2026 have been fully considered but are moot in view of new ground(s) of rejection because the arguments do not apply to any of the references being used in the current rejection. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). Examiner's note: Examiner has cited particular paragraphs and columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner (see MPEP § 2123). Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHIL K NGUYEN whose telephone number is (571)270-3356. The examiner can normally be reached 9:30 a.m - 5 p.m. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at (571)270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PHIL K NGUYEN/Primary Examiner, Art Unit 2176
Read full office action

Prosecution Timeline

Apr 10, 2024
Application Filed
Jan 02, 2026
Non-Final Rejection mailed — §103
Mar 18, 2026
Applicant Interview (Telephonic)
Mar 18, 2026
Examiner Interview Summary
Mar 24, 2026
Response Filed
Jun 09, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
82%
Grant Probability
97%
With Interview (+14.3%)
2y 8m (~4m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 546 resolved cases by this examiner. Grant probability derived from career allowance rate.

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