DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) rejected have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 6-12 and 14-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Haba 20240249995.
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Regarding claim 1, figs. 14 and 4C of Haba discloses a semiconductor device comprising:
a top semiconductor die 1401 (par [0084] – semiconductor) located above and in direct physically contact with a bottom semiconductor die 1402 ((par [0084] – semiconductor) at a hybrid bonding interface (par [0083] - the first chip and the second chip are hybrid bonded to one another via direct bonds formed between metal features 1303 and the surrounding dielectric surfaces);
wherein the top semiconductor die comprises a top semiconductor-containing thermoelectric cooling element of a first conductivity type located on a first side of the hybrid bonding interface, and
the bottom semiconductor die comprises a bottom semiconductor-containing thermoelectric cooling element of a second conductivity type that is opposite from the first conductivity type located on a second side of the hybrid bonding interface which is opposite the first side of the hybrid bonding interface (par [0084] - ,
wherein the top semiconductor-containing thermoelectric cooling element and the bottom semiconductor-containing thermoelectric cooling element are electrically connected to provide a thermoelectric cooling structure (see fig. 4 above).
Regarding claim 9, figs. 14 and 4C of Haba discloses a semiconductor device comprising:
a top semiconductor die 1401 (par [0084] – semiconductor) located above and in direct physically contact with a bottom semiconductor die 1402 ((par [0084] – semiconductor) at a hybrid bonding interface (par [0083] - the first chip and the second chip are hybrid bonded to one another via fdirect bonds formed between metal features 1303 and the surrounding dielectric surfaces), and
wherein the top semiconductor die comprises a top pillar-containing first semiconductor thermoelectric cooling element of a first conductivity type located on a first side of the hybrid bonding interface, and the bottom semiconductor die comprises a bottom pillar- containing second semiconductor thermoelectric cooling element of a second conductivity type that is opposite from the first conductivity type located on a second side of the hybrid bonding interface which is opposite the first side of the hybrid bonding interface, and the top pillar- containing first semiconductor thermoelectric cooling element and the bottom pillar-containing second semiconductor thermoelectric cooling element are electrically connected to provide a thermoelectric cooling structure (see fig. 4C).
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Regarding claims 2 and 10, figs. 4C and 14 of Haba discloses further comprising top metal wiring located in the top semiconductor die and bottom metal wiring located in the bottom semiconductor die, wherein the top metal wiring and the bottom metal wiring are used to electrically connect the top semiconductor-containing thermoelectric cooling element and the bottom semiconductor-containing thermoelectric cooling element.
Regarding claims 3 and 11, par [0052] of Haba discloses wherein the first conductivity type is n-type, and the second conductivity type is p-type.
Regarding claims 4 and 12, par [0052] of Haba discloses wherein the first conductivity type is p-type, and the second conductivity type is n-type.
Regarding claims 6 and 14, fig. 14 of Haba discloses wherein the hybrid bonding interface comprises metal-to-metal bonding and dielectric-to-dielectric bonding.
Regarding claim 7, par [0083] and fig. 14 of Haba disclose wherein the top semiconductor- containing thermoelectric cooling element is present in a top bonding dielectric layer of the top semiconductor die, and the semiconductor-containing thermoelectric cooling element is present in a bottom bonding dielectric layer of the bottom semiconductor die, and the top bonding dielectric layer and the bottom bonding layer have a dielectric-to-dielectric bond at the hybrid bonding interface.
Regarding claim 15, par [0083] and fig. 14 of Haba disclose wherein the top pillar-containing first semiconductor thermoelectric cooling element is present in a top bonding dielectric layer of the top semiconductor die, and the bottom pillar-containing second semiconductor thermoelectric cooling element is present in a bottom bonding dielectric layer of the bottom semiconductor die, and the top bonding dielectric layer and the bottom bonding layer have a dielectric-to-dielectric bond at the hybrid bonding interface.
Regarding claims 8 and 16, Haba necessary discloses wherein the top semiconductor die comprises a top front-end-of-the-line (FEOL) level and a top back-end-of-the-line (BEOL) structure including a top bonding dielectric layer as an uppermost layer (note in fabrication steps – those formed first are considered FEOL and those formed last are considered BEOL), and the bottom semiconductor die comprises a bottom FEOL level and a bottom BEOL structure including a bottom bonding dielectric layer as an uppermost layer (note in fabrication steps – those formed first are considered FEOL and those formed last are considered BEOL), wherein the top bonding dielectric layer and the bottom bonding layer form a dielectric-to-dielectric bond at the hybrid bonding interface (see figs. 4C and 14).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Haba in view of Sato et al. 20220052001.
Regarding claims 17-18, Haba disclose claim 9. Haba does not discloses wherein the top pillar-containing first semiconductor thermoelectric cooling element comprises a plurality of individual top semiconductor-containing fingers that are spaced apart by a first dielectric material; and wherein the bottom pillar-containing second semiconductor thermoelectric cooling element comprises a plurality of individual bottom semiconductor-containing fingers that are spaced apart by a second dielectric material.
However, Sato discloses an integrated circuit device may include a multi-material toothed bond pad including (a) an array of vertically-extending teeth formed from a first material, e.g., aluminum, and (b) a fill material, e.g., silver, at least partially filling voids between the array of teeth. The teeth may be formed by depositing and etching aluminum or other suitable material, and the fill material may be deposited over the array of teeth and extending down into the voids between the teeth, and etched to expose top surfaces of the teeth. The array of teeth may collectively define an abrasive structure. The multi-material toothed bond pad may be bonded to another bond pad, e.g., using an ultrasonic or thermosonic bonding process, during which the abrasive teeth may abrade, break, or remove unwanted native oxide layers formed on the respective bond pad surfaces, to thereby create a direct and/or eutectic bonding between the bond pads.
As such it would have been obvious to form a device comprising wherein the top pillar-containing first semiconductor thermoelectric cooling element comprises a plurality of individual top semiconductor-containing fingers that are spaced apart by a first dielectric material; and wherein the bottom pillar-containing second semiconductor thermoelectric cooling element comprises a plurality of individual bottom semiconductor-containing fingers that are spaced apart by a second dielectric material such as taught by Sato in order to create a direct and/or eutectic bonding between the bond pads.
Claims 5 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Haba in view of Chen et al. 20210249380.
Regarding claims 5 and 13, Haba discloses claims 1 and 9, but do not disclose further comprising a pair of through via structures located in the top semiconductor die, wherein a first through via structure of the pair of through via structures is electrically connected to the top semiconductor-containing thermoelectric cooling element and a second through via structure of the pair of through via structures is electrically connected to the bottom semiconductor-containing thermoelectric cooling element.
However, fig. 1 of Chen discloses a top semiconductor die located above and directly contacting a bottom semiconductor die and further comprising a pair of through via structures located in the top semiconductor die, wherein a first through via structure of the pair of through via structures is electrically connected to the top semiconductor-containing thermoelectric cooling element (directly connected to provide heat transfer) and a second through via structure of the pair of through via structures is electrically connected to the bottom semiconductor-containing thermoelectric cooling element (directly connected to provide heat transfer).
As such it would have been obvious to form a device of Haba further comprising a pair of through via structures located in the top semiconductor die, wherein a first through via structure of the pair of through via structures is electrically connected to the top semiconductor-containing thermoelectric cooling element and a second through via structure of the pair of through via structures is electrically connected to the bottom semiconductor-containing thermoelectric cooling element such as taught by Chen in order to transfer heat directly.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VONGSAVANH SENGDARA whose telephone number is (571)270-5770. The examiner can normally be reached 9AM-6PM EST.
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/VONGSAVANH SENGDARA/Primary Examiner, Art Unit 2893
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