Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of the information disclosure statements filed on April 10, 2024. U.S. patents and Foreign Patents have been considered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 - 6 are rejected under 35 U.S.C. 103 as being unpatentable over US6751785B1 (Oh) in view of US20190340326 A1 (Huda).
In regards to claim 1 (Oh) shows:
An integrated circuit design system using a computing system, the integrated circuit design system comprising; Oh [Column 7 Lines 60 - Column 8 Lines 5] teaches a system for locating dummy fills in an integrated circuit, implemented with a metal conductor identification processor, an exclusion zone processor, and a dummy fill locator.
a memory configured to store an instruction; and Oh [Column 8 Lines 55 - 65] teaches a system memory that stores the program instructions executed by the system.
a processor configured to execute the instruction to cause the integrated circuit design system to design an integrated circuit, Oh [Column 8 Lines 65 - Column 9 Lines 5] teaches a microprocessor that, using instructions retrieved from memory, controls the reception and manipulation of input data to design the dummy-fill layout of the integrated circuit.
wherein the integrated circuit includes a substrate, Oh [Column 4 Lines 50 - 55] teaches an integrated circuit chip having multiple metal layers in which a lower layer is a substrate.
select a first metal layer included in the BEOL and disposed at a first level from the substrate; Oh [Column 7 Lines 1 - 10] teaches identifying a metal conductor of a designated critical net located in a corresponding signal net layer at a level of the layered structure.
generate a first blockage layer disposed at the first level and surrounding the first metal layer; Oh [Column 5 Lines 35 - 55] and [Column 6 Lines 5 - 20] teach delineating a net blocking exclusion zone extending omnidirectionally around the designated metal conductor in the layer that contains that conductor.
generate at least one first upper blockage layer disposed at a level higher than the first level from the substrate; and Oh [Column 5 Lines 50 - 60] teaches that each metal layer above the designated signal net layer has a net blocking exclusion zone similar to that of the designated layer.
generate at least one first lower blockage layer disposed at a level lower than the first level from the substrate. Oh [Column 5 Lines 50 - 60] and [Column 7 Lines 5 - 20] teach that each metal layer below the designated signal net layer also has a net blocking exclusion zone within the net blocking distance.
Oh differs from the claimed invention in that it does not explicitly disclose a front end of line (FEOL) in at least a portion of the substrate and on the substrate, and a back end of line (BEOL) formed on the FEOL.
Huda teaches a front end of line (FEOL) in at least a portion of the substrate and on the substrate, and a back end of line (BEOL) formed on the FEOL; Huda [0018] teaches a front end of line (FEOL) layer formed before the first metallization and including device components in and on the substrate, and a back end of line (BEOL) layer formed after the first metallization and containing wires and vias.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Oh and Huda to expressly designate the front end of line and back end of line layers of the integrated circuit whose fill is being controlled, with a reasonable expectation of success as both references address computer-aided layout of integrated circuit metallization and fill.
In regards to claim 2 (Oh) shows the integrated circuit design system of claim 1:
wherein when the processor generates the first upper blockage layer, the processor is configured to: generate a second blockage layer disposed at a second level higher than the first level from the substrate; and Oh [Column 5 Lines 65 - Column 6 Lines 10] teaches that the blocking is applied in additional layers above the designated signal net layer, the number of layers above being selectable.
generate a third blockage layer disposed at a third level higher than the second level from the substrate. Oh [Column 5 Lines 65 - Column 6 Lines 10] teaches that the blocking is applied in additional layers above the designated signal net layer, the number of layers above being selectable.
In regards to claim 3 (Oh) shows the integrated circuit design system of claim 2:
generate a first dummy pattern at the second level; and Oh [Column 4 Lines 55 - 65] and [Column 7 Lines 15 - 25] teach locating dummy metal fills in the designated signal net layer as well as in upper and lower metal layers, only outside the blocked zones.
generate a second dummy pattern at the third level, Oh [Column 4 Lines 55 - 65] and [Column 7 Lines 15 - 25] teach locating dummy metal fills in the designated signal net layer as well as in upper and lower metal layers, only outside the blocked zones.
wherein the first and second dummy patterns do not overlap the first metal layer in a plan view. Oh [Column 7 Lines 15 - 25] teaches that the dummy fill locations are placed only within the permissible areas outside of the blocked zones, so the dummy fills do not overlap the designated conductor.
In regards to claim 4 (Oh) shows the integrated circuit design system of claim 2:
wherein when the processor generates the first lower blockage layer, the processor is configured to generate a fourth blockage layer disposed at a fourth level, which is lower than the first level from the substrate. Oh [Column 5 Lines 65 - Column 6 Lines 10] teaches that the blocking is applied in additional layers below the designated signal net layer, generally the same number of layers below as above.
In regards to claim 5 (Oh) shows the integrated circuit design system of claim 4:
wherein when the processor generates the first lower blockage layer, the processor is further configured to generate a fifth blockage layer disposed at a fifth level, which is lower than the fourth level from the substrate. Oh [Column 5 Lines 65 - Column 6 Lines 10] teaches that the blocking is applied in additional layers below the designated signal net layer, generally the same number of layers below as above.
In regards to claim 6 (Oh) shows the integrated circuit design system of claim 5:
generate a third dummy pattern at the fourth level; and Oh [Column 4 Lines 55 - 65] and [Column 7 Lines 15 - 25] teach locating dummy metal fills in the designated signal net layer as well as in upper and lower metal layers, only outside the blocked zones.
generate a fourth dummy pattern at a fifth level, Oh [Column 4 Lines 55 - 65] and [Column 7 Lines 15 - 25] teach locating dummy metal fills in the designated signal net layer as well as in upper and lower metal layers, only outside the blocked zones.
wherein the third and fourth dummy patterns do not overlap the first metal layer in a plan view. Oh [Column 7 Lines 15 - 25] teaches that the dummy fill locations are placed only within the permissible areas outside of the blocked zones, so the dummy fills do not overlap the designated conductor.
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over US6751785B1 (Oh) in view of US20190340326 A1 (Huda) and further in view of US20210125922A1 (Lee).
In regards to claim 7 (Oh modified by Huda) does not show: wherein the integrated circuit includes a passive element, and wherein the passive element includes a second metal layer included in the BEOL, disposed at the first level from the substrate and not overlapped with the first metal layer, and a third metal layer included in the BEOL and disposed at a second level higher than the first level from the substrate, and wherein the second metal layer and the third metal layer are connected to each other through a via;
Lee teaches wherein the integrated circuit includes a passive element, and wherein the passive element includes a second metal layer included in the BEOL, disposed at the first level from the substrate and not overlapped with the first metal layer, and a third metal layer included in the BEOL and disposed at a second level higher than the first level from the substrate; Lee [0011] and [0013] teach a back end of line passive element, such as an inductor, formed in the interlevel dielectric layers, and Lee [0015] teaches a metal layer Mn-1 at a first level and an overlying metal layer Mn at a higher level.
Lee teaches wherein the second metal layer and the third metal layer are connected to each other through a via; Lee [0015] teaches that a via plug layer Vn-1 electrically connects the metal layer Mn-1 to the overlying metal layer Mn.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine Oh and Huda with Lee to apply the exclusion-zone and dummy-fill control to a back end of line passive element formed of two metal layers connected by a via, with a reasonable expectation of success as the references address managing dummy fill around sensitive back end of line structures.
In regards to claim 8 (Oh) shows the integrated circuit design system of claim 7:
generate a second blockage layer disposed at the first level and surrounding the second metal layer; and Oh [Column 6 Lines 5 - 20] teaches delineating an exclusion zone surrounding a selected metal conductor in the layer that contains it, applied to each identified conductor.
generate a third blockage layer disposed at the second level, and surrounding the third metal layer. Oh [Column 6 Lines 5 - 20] teaches delineating an exclusion zone surrounding a selected metal conductor in the layer that contains it, applied to each identified conductor.
Claims 9 - 20 are rejected under 35 U.S.C. 103 as being unpatentable over US6751785B1 (Oh) in view of US20190340326 A1 (Huda), US20210125922A1 (Lee), and US20060163692A1 (Detecheverry).
In regards to claim 9 (Oh) shows the integrated circuit design system of claim 8:
generate at least one second lower blockage layer disposed at a level lower than the first level from the substrate. Oh [Column 5 Lines 50 - 60] and [Column 7 Lines 5 - 20] teach that each metal layer below the designated signal net layer also has a net blocking exclusion zone within the net blocking distance.
Oh differs from the claimed invention in that it does not explicitly disclose generate at least one second upper blockage layer disposed at a level higher than the second level from the substrate.
Detecheverry teaches generate at least one second upper blockage layer disposed at a level higher than the second level from the substrate; Detecheverry [0066] teaches that all or part of the filling structure pattern layers may be located above the inductive element, so that the inductive element is located between a lower shield and at least one filling structure pattern layer above it.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine Oh, Huda, and Lee with Detecheverry to dispose the fill-control layers at levels above the passive element in addition to below it, with a reasonable expectation of success as the references address controlling fill around back end of line passive elements.
In regards to claim 10 (Oh) shows the integrated circuit design system of claim 9:
wherein the second lower blockage layer overlaps at least a portion of the second metal layer and the third metal layer in a plan view. Oh [Column 5 Lines 50 - 60] and FIG. 3 teach that the net blocking exclusion zone in a metal layer below the designated signal net layer coincides with the designated conductor and thus overlaps at least a portion of it in a plan view.
Oh differs from the claimed invention in that it does not explicitly disclose wherein the second upper blockage layer overlaps at least a portion of the second metal layer and the third metal layer in a plan view.
Detecheverry teaches wherein the second upper blockage layer overlaps at least a portion of the second metal layer and the third metal layer in a plan view; Detecheverry [0060], [0062], and [0066] teach filling structure pattern layers formed in successive metal layers that occupy the region of the inductive element in plan view while being kept off the inductor path.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine Oh, Huda, and Lee with Detecheverry to dispose the fill-control layers at levels above the passive element in addition to below it, with a reasonable expectation of success as the references address controlling fill around back end of line passive elements.
In regards to claim 11 (Oh) shows the integrated circuit design system of claim 10:
wherein when the processor generates the second upper blockage layer, the processor is further configured to: generate a third blockage layer disposed at a third level, which is higher than the second level from the substrate; and Oh [Column 5 Lines 65 - Column 6 Lines 10] teaches that the blocking is applied in additional layers above the designated signal net layer, the number of layers above being selectable.
generate a fourth blockage layer disposed at a fourth level, which is higher than the third level from the substrate. Oh [Column 5 Lines 65 - Column 6 Lines 10] teaches that the blocking is applied in additional layers above the designated signal net layer, the number of layers above being selectable.
In regards to claim 12 (Oh) shows the integrated circuit design system of claim 11:
wherein when the processor generates the second lower blockage layer, the processor is further configured to: generate a fifth blockage layer disposed at a fifth level, which is lower than the first level from the substrate; and Oh [Column 5 Lines 65 - Column 6 Lines 10] teaches that the blocking is applied in additional layers below the designated signal net layer, generally the same number of layers below as above.
generate a sixth blockage layer disposed at a sixth level, which is lower than the fifth level from the substrate. Oh [Column 5 Lines 65 - Column 6 Lines 10] teaches that the blocking is applied in additional layers below the designated signal net layer, generally the same number of layers below as above.
In regards to claim 13 (Oh) shows:
An integrated circuit design system using a computing system, the integrated circuit design system comprising; Oh [Column 7 Lines 60 - Column 8 Lines 5] teaches a system for locating dummy fills in an integrated circuit, implemented with a metal conductor identification processor, an exclusion zone processor, and a dummy fill locator.
a memory configured to store an instruction; and Oh [Column 8 Lines 55 - 65] teaches a system memory that stores the program instructions executed by the system.
a processor configured to execute the instruction to cause the integrated circuit design system to design an integrated circuit, Oh [Column 8 Lines 65 - Column 9 Lines 5] teaches a microprocessor that, using instructions retrieved from memory, controls the reception and manipulation of input data to design the dummy-fill layout of the integrated circuit.
wherein the integrated circuit includes a substrate, Oh [Column 4 Lines 50 - 55] teaches an integrated circuit chip having multiple metal layers in which a lower layer is a substrate.
select the first metal layer; Oh [Column 7 Lines 1 - 10] teaches identifying a metal conductor of a designated critical net located in a corresponding signal net layer at a level of the layered structure.
generate a first blockage layer disposed at the first level, surrounding the first metal layer; Oh [Column 5 Lines 35 - 55] and [Column 6 Lines 5 - 20] teach delineating a net blocking exclusion zone extending omnidirectionally around the designated metal conductor in the layer that contains that conductor.
generate a second blockage layer disposed at the second level, surrounding the second metal layer; Oh [Column 6 Lines 5 - 20] teaches delineating an exclusion zone surrounding a selected metal conductor in the layer that contains it, applied to each identified conductor.
generate at least one lower blockage layer disposed at a level lower than the first level from the substrate. Oh [Column 5 Lines 50 - 60] and [Column 7 Lines 5 - 20] teach that each metal layer below the designated signal net layer also has a net blocking exclusion zone within the net blocking distance.
Oh differs from the claimed invention in that it does not explicitly disclose a front end of line (FEOL) in at least a portion of the substrate and on the substrate, a back end of line (BEOL) formed on the FEOL, and a passive element formed in the BEOL; wherein the passive element includes a first metal layer included in the BEOL and disposed at a first level from the substrate, and a second metal layer included in the BEOL, disposed at a second level higher than the first level from the substrate and connected to the first metal layer through a via; and generate at least one upper blockage layer disposed at a level higher than the second level from the substrate.
Lee teaches a passive element formed in the BEOL, wherein the passive element includes a first metal layer included in the BEOL and disposed at a first level from the substrate, and a second metal layer included in the BEOL, disposed at a second level higher than the first level from the substrate; Lee [0011] and [0013] teach a back end of line passive element, such as an inductor, formed in the interlevel dielectric layers, and Lee [0015] teaches a metal layer Mn-1 at a first level and an overlying metal layer Mn at a higher level.
Lee teaches and connected to the first metal layer through a via; Lee [0015] teaches that a via plug layer Vn-1 electrically connects the metal layer Mn-1 to the overlying metal layer Mn.
Lee differs from the claimed invention in that it does not explicitly disclose a front end of line (FEOL) in at least a portion of the substrate and on the substrate, a back end of line (BEOL) formed on the FEOL; and generate at least one upper blockage layer disposed at a level higher than the second level from the substrate.
Huda teaches a front end of line (FEOL) in at least a portion of the substrate and on the substrate, a back end of line (BEOL) formed on the FEOL; Huda [0018] teaches a front end of line (FEOL) layer formed before the first metallization and including device components in and on the substrate, and a back end of line (BEOL) layer formed after the first metallization and containing wires and vias.
Huda differs from the claimed invention in that it does not explicitly disclose generate at least one upper blockage layer disposed at a level higher than the second level from the substrate.
Detecheverry teaches generate at least one upper blockage layer disposed at a level higher than the second level from the substrate; Detecheverry [0066] teaches that all or part of the filling structure pattern layers may be located above the inductive element, so that the inductive element is located between a lower shield and at least one filling structure pattern layer above it.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Oh and Huda to expressly designate the front end of line and back end of line layers of the integrated circuit whose fill is being controlled, with a reasonable expectation of success as both references address computer-aided layout of integrated circuit metallization and fill.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine Oh and Huda with Lee to apply the exclusion-zone and dummy-fill control to a back end of line passive element formed of two metal layers connected by a via, with a reasonable expectation of success as the references address managing dummy fill around sensitive back end of line structures.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine Oh, Huda, and Lee with Detecheverry to dispose the fill-control layers at levels above the passive element in addition to below it, with a reasonable expectation of success as the references address controlling fill around back end of line passive elements.
In regards to claim 14 (Oh) shows the integrated circuit design system of claim 13:
wherein when the processor generates the upper blockage layer, the processor is configured to: generate a third blockage layer disposed at a third level, which is higher than the second level from the substrate; and Oh [Column 5 Lines 65 - Column 6 Lines 10] teaches that the blocking is applied in additional layers above the designated signal net layer, the number of layers above being selectable.
generate a fourth blockage layer disposed at a fourth level, which is higher than the third level from the substrate. Oh [Column 5 Lines 65 - Column 6 Lines 10] teaches that the blocking is applied in additional layers above the designated signal net layer, the number of layers above being selectable.
In regards to claim 15 (Oh) shows the integrated circuit design system of claim 14:
insert a first dummy pattern into the third level, wherein the first dummy pattern does not overlap the third blockage layer. Oh [Column 7 Lines 15 - 25] teaches that the dummy fill locations are placed only within the permissible areas outside of the blocked zones, so the dummy fills do not overlap the designated conductor.
In regards to claim 16 (Oh modified by Huda and Lee) does not show: wherein the first dummy pattern overlaps at least a portion of the first metal layer and the second metal layer in a plan view.
Detecheverry teaches wherein the first dummy pattern overlaps at least a portion of the first metal layer and the second metal layer in a plan view; Detecheverry [0060], [0062], and [0066] teach filling structure pattern layers formed in successive metal layers that occupy the region of the inductive element in plan view while being kept off the inductor path.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine Oh, Huda, and Lee with Detecheverry to dispose the fill-control layers at levels above the passive element in addition to below it, with a reasonable expectation of success as the references address controlling fill around back end of line passive elements.
In regards to claim 17 (Oh) shows the integrated circuit design system of claim 13:
wherein when the processor generates the lower blockage layer, the processor is configured to: generate a fifth blockage layer disposed at a fifth level, which is lower than the first level from the substrate. Oh [Column 5 Lines 50 - 60] and [Column 7 Lines 5 - 20] teach that each metal layer below the designated signal net layer also has a net blocking exclusion zone within the net blocking distance.
In regards to claim 18 (Oh) shows the integrated circuit design system of claim 17:
wherein when the processor generates the lower blockage layer, the processor is further configured to generate a sixth blockage layer disposed at a sixth level, which is lower than the fifth level from the substrate. Oh [Column 5 Lines 65 - Column 6 Lines 10] teaches that the blocking is applied in additional layers below the designated signal net layer, generally the same number of layers below as above.
In regards to claim 19 (Oh) shows:
A computing system comprising; Oh [Column 7 Lines 60 - Column 8 Lines 5] teaches a system for locating dummy fills in an integrated circuit, implemented with a metal conductor identification processor, an exclusion zone processor, and a dummy fill locator.
a memory configured to store an instruction; and Oh [Column 8 Lines 55 - 65] teaches a system memory that stores the program instructions executed by the system.
a processor configured to execute the instruction to cause the computing system to design an integrated circuit, Oh [Column 8 Lines 65 - Column 9 Lines 5] teaches a microprocessor that, using instructions retrieved from memory, controls the reception and manipulation of input data to design the dummy-fill layout of the integrated circuit.
wherein the integrated circuit includes a substrate, Oh [Column 4 Lines 50 - 55] teaches an integrated circuit chip having multiple metal layers in which a lower layer is a substrate.
select a first metal layer included in the BEOL and disposed at a first level from the substrate; Oh [Column 7 Lines 1 - 10] teaches identifying a metal conductor of a designated critical net located in a corresponding signal net layer at a level of the layered structure.
generate a first blockage layer disposed at the first level, and surrounding the first metal layer; Oh [Column 5 Lines 35 - 55] and [Column 6 Lines 5 - 20] teach delineating a net blocking exclusion zone extending omnidirectionally around the designated metal conductor in the layer that contains that conductor.
generate at least one first upper blockage layer disposed at a level higher than the first level from the substrate; Oh [Column 5 Lines 50 - 60] teaches that each metal layer above the designated signal net layer has a net blocking exclusion zone similar to that of the designated layer.
generate at least one first lower blockage layer disposed at a level lower than the first level from the substrate; Oh [Column 5 Lines 50 - 60] and [Column 7 Lines 5 - 20] teach that each metal layer below the designated signal net layer also has a net blocking exclusion zone within the net blocking distance.
generate a second blockage layer disposed at the first level, and surrounding the second metal layer; Oh [Column 6 Lines 5 - 20] teaches delineating an exclusion zone surrounding a selected metal conductor in the layer that contains it, applied to each identified conductor.
generate a third blockage layer disposed at the second level, and surrounding the third metal layer; Oh [Column 6 Lines 5 - 20] teaches delineating an exclusion zone surrounding a selected metal conductor in the layer that contains it, applied to each identified conductor.
generate at least one second lower blockage layer disposed at a level lower than the first level from the substrate. Oh [Column 5 Lines 50 - 60] and [Column 7 Lines 5 - 20] teach that each metal layer below the designated signal net layer also has a net blocking exclusion zone within the net blocking distance.
Oh differs from the claimed invention in that it does not explicitly disclose a front end of line (FEOL) formed in at least a portion of the substrate and on the substrate and a back end of line (BEOL) formed on the FEOL; select a passive element, which includes a second metal layer that is included in the BEOL, is disposed at the first level from the substrate, and does not overlap the first metal layer, and a third metal layer that is included in the BEOL, is disposed at a second level that is higher than the first level from the substrate, and is connected to the second metal layer through a via; and generate at least one second upper blockage layer disposed at a level higher than the second level from the substrate.
Lee teaches select a passive element, which includes a second metal layer that is included in the BEOL, is disposed at the first level from the substrate, and does not overlap the first metal layer, and a third metal layer that is included in the BEOL, is disposed at a second level that is higher than the first level from the substrate; Lee [0011] and [0013] teach a back end of line passive element, such as an inductor, formed in the interlevel dielectric layers, and Lee [0015] teaches a metal layer Mn-1 at a first level and an overlying metal layer Mn at a higher level.
Lee teaches and is connected to the second metal layer through a via; Lee [0015] teaches that a via plug layer Vn-1 electrically connects the metal layer Mn-1 to the overlying metal layer Mn.
Lee differs from the claimed invention in that it does not explicitly disclose a front end of line (FEOL) formed in at least a portion of the substrate and on the substrate and a back end of line (BEOL) formed on the FEOL; and generate at least one second upper blockage layer disposed at a level higher than the second level from the substrate.
Huda teaches a front end of line (FEOL) formed in at least a portion of the substrate and on the substrate and a back end of line (BEOL) formed on the FEOL; Huda [0018] teaches a front end of line (FEOL) layer formed before the first metallization and including device components in and on the substrate, and a back end of line (BEOL) layer formed after the first metallization and containing wires and vias.
Huda differs from the claimed invention in that it does not explicitly disclose generate at least one second upper blockage layer disposed at a level higher than the second level from the substrate.
Detecheverry teaches generate at least one second upper blockage layer disposed at a level higher than the second level from the substrate; Detecheverry [0066] teaches that all or part of the filling structure pattern layers may be located above the inductive element, so that the inductive element is located between a lower shield and at least one filling structure pattern layer above it.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Oh and Huda to expressly designate the front end of line and back end of line layers of the integrated circuit whose fill is being controlled, with a reasonable expectation of success as both references address computer-aided layout of integrated circuit metallization and fill.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine Oh and Huda with Lee to apply the exclusion-zone and dummy-fill control to a back end of line passive element formed of two metal layers connected by a via, with a reasonable expectation of success as the references address managing dummy fill around sensitive back end of line structures.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine Oh, Huda, and Lee with Detecheverry to dispose the fill-control layers at levels above the passive element in addition to below it, with a reasonable expectation of success as the references address controlling fill around back end of line passive elements.
In regards to claim 20 (Oh) shows the computing system of claim 19:
wherein, when the instruction is executed by the processor, the processor is further configured to: insert a first dummy pattern near the first metal layer at the first level; Oh [Column 4 Lines 55 - 65] and [Column 7 Lines 15 - 25] teach locating dummy metal fills in the designated signal net layer as well as in upper and lower metal layers, only outside the blocked zones.
insert a second dummy pattern into a level higher than the first level from the substrate; and Oh [Column 4 Lines 55 - 65] and [Column 7 Lines 15 - 25] teach locating dummy metal fills in the designated signal net layer as well as in upper and lower metal layers, only outside the blocked zones.
insert a third dummy pattern into a level lower than the first level from the substrate. Oh [Column 4 Lines 55 - 65] and [Column 7 Lines 15 - 25] teach locating dummy metal fills in the designated signal net layer as well as in upper and lower metal layers, only outside the blocked zones.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANWER AHMED ALAWDI whose telephone number is (703)756-1018. The examiner can normally be reached Monday - Friday 8:00 am - 5:30 pm.
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/ANWER AHMED ALAWDI/
Examiner, Art Unit 2851 /JACK CHIANG/ Supervisory Patent Examiner, Art Unit 2851
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