DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This non-final office action is responsive to Applicants' application filed on 04/10/24. Claims 1-14 are presented for examination and are pending for the reasons indicated herein below.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Objections
The claims are objected to because they include reference characters which are not enclosed within parentheses. Reference characters corresponding to elements recited in the detailed description of the drawings and used in conjunction with the recitation of the same element or group of elements in the claims should be enclosed within parentheses so as to avoid confusion with other numbers or characters which may appear in the claims. See MPEP § 608.01(m).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8, 11 rejected under 35 U.S.C. 103 as being unpatentable over Narimani et al. (US 20150200602 A1 and hereinafter as Nari) in view of Mihalache (AU 2015414494 A1 and hereinafter as Miha)
Regarding claim 1. Nari teaches a five-level DC-AC converter [fig 1-3, ¶6], comprising: a positive DC voltage input point; a negative DC voltage input point [101/102];
a third circuit connected across the first common point and the second common point; wherein the third circuit comprises: six switches S3a, S4a, S5a, S4na, S5na, and S3na connected together [circuit between S1-S6];
at least first and second flying capacitors C1a and C2a connected together across a connection point between switches S3a and S4a and a connection point between switches S5na and S3na [c1/c2];
at least first and second diodes D1 and D2 connected together across a connection point between switches S4a and S5a and a connection point between switches S4na and S5na [d1/d2];
a common point between first and second flying capacitors C1a and C2a connected to a common point between diodes D1 and D2 [119]; and an output point between switches S5a and S4na that outputs five voltage levels [¶6].
However, Nari does not explicitly mention a circuit comprising three capacitors C1, C2, C3 connected across the positive and negative DC input points, wherein a first dc-link voltage is provided at a connection between the capacitors C1 and C2 and the positive DC voltage input point, and a second dc-link voltage is provided at a connection between the capacitors C2 and C3 and the negative DC voltage input point; a first circuit connected across the first dc-link voltage comprising a switch S1a and a switch S1na connected together at a first common point; a second circuit connected across the second dc-link voltage comprising a switch S2a and a switch S2na connected together at a second common point.
Miha teaches a circuit comprising three capacitors C1, C2, C3 connected across the positive and negative DC input points [see fig 4, C1-C3], wherein a first dc-link voltage is provided at a connection between the capacitors C1 and C2 and the positive DC voltage input point [see 42], and a second dc-link voltage is provided at a connection between the capacitors C2 and C3 and the negative DC voltage input point [see 44]; a first circuit connected across the first dc-link voltage comprising a switch S1a and a switch S1na connected together at a first common point [upper S1/S1N]; a second circuit [lower S1/S1N] connected across the second dc-link voltage comprising a switch S2a and a switch S2na connected together at a second common point.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the features of Miha in order to provide symmetrical voltage distribution across converter which provide a stable connection and improve efficiency and utilization of lower voltage rated devices.
Regarding claim 2. Nari as modified teaches the five-level DC-AC converter of claim 1, wherein a blocking voltage of each switch is substantially the same [substantially is interpreted as a relative term and thus it is understood that the limitation follows the reference on record].
Regarding claim 3. Nari as modified teaches the five-level DC-AC converter of claim 1, wherein a blocking voltage of each switch is approximately Vdc/4 [approximately is interpreted as a relative term and thus it is understood that the limitation follows the reference on record].
Regarding claim 4. Nari as modified teaches the five-level DC-AC converter of claim 1, wherein capacitor voltage is substantially balanced across all operating points of the converter [substantially is interpreted as a relative term and thus it is understood that the limitation follows the reference on record].
Regarding claim 5. Nari as modified teaches the five-level DC-AC converter of claim 1, except wherein the capacitors C1 and C3 are substantially the same value and the capacitor C2 is of a smaller value than C1 or C3. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify a specific threshold value which would better align the circuit towards design requirements, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art.
Regarding claim 6. Nari as modified teaches the five-level DC-AC converter of claim 1, comprising a controller [122 Nari] that generates switching signals for switches of the DC-AC converter;
wherein the switching signals control switching states of the switches to regulate capacitor voltages under all operating conditions [intended design requirements] of the DC-AC converter and to generate the five output voltage levels [function of controller 122].
Regarding claim 8. Nari as modified teaches the five-level DC-AC converter of claim 6, wherein the switching states include redundant switching states [see claim 1 of Nari].
Regarding claim 11. Nari teaches a three-phase five-level DC-AC converter [fig 1-3, ¶6], comprising: a positive DC voltage input point; a negative DC voltage input point [101/102];
a third circuit connected across the first common point and the second common point; wherein the third circuit comprises: six switches S3a, S4a, S5a, S4na, S5na, and S3na connected together [circuit between S1-S6]; at least first and second flying capacitors C1a and C2a connected together across a connection point between switches S3a and S4a and a connection point between switches S5na and S3na [c1/c2];
at least first and second diodes D1 and D2 connected together across a connection point between switches S4a and S5a and a connection point between switches S4na and S5na [d1/d2]; a common point between first and second flying capacitors C1a and C2a connected to a common point between diodes D1 and D2 [119]; and an output point between switches S5a and S4na that outputs five voltage levels corresponding to one of the three phases [¶6 and ¶11].
However, Nari does not explicitly mention a circuit comprising three capacitors C1, C2, C3 connected across the positive and negative DC input points, wherein a first dc-link voltage is provided at a connection between the capacitors C1 and C2 and the positive DC voltage input point, and a second dc-link voltage is provided at a connection between the capacitors C2 and C3 and the negative DC voltage input point; wherein each phase of the three-phase converter comprises: a first circuit connected across the first dc-link voltage comprising a switch S1a and a switch S1na connected together at a first common point; a second circuit connected across the second dc-link voltage comprising a switch S2a and a switch S2na connected together at a second common point.
Miha teaches a circuit comprising three capacitors C1, C2, C3 connected across the positive and negative DC input points [see fig 4, C1-C3], wherein a first dc-link voltage is provided at a connection between the capacitors C1 and C2 and the positive DC voltage input point [see 42], and a second dc-link voltage is provided at a connection between the capacitors C2 and C3 and the negative DC voltage input point [see 44]; wherein each phase of the three-phase converter comprises: a first circuit connected across the first dc-link voltage comprising a switch S1a and a switch S1na connected together at a first common point [upper S1/S1N]; a second circuit connected across the second dc-link voltage comprising a switch S2a and a switch S2na connected together at a second common point [lower S1/S1N]. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the features of Miha in order to provide symmetrical voltage distribution across converter which provide a stable connection and improve efficiency and utilization of lower voltage rated devices.
Claims 9-10, 12 rejected under 35 U.S.C. 103 as being unpatentable over Narimani et al. (US 20150200602 A1 and hereinafter as Nari) in view of Mihalache (AU 2015414494 A1 and hereinafter as Miha) and further in view of Rufer (US 7180270 B2)
Regarding claim 9. Nari as modified teaches the five-level DC-AC converter of claim 1. However, Nari as modified does not explicitly mention the circuit implemented in a DC-AC grid-tie converter.
Rufer teaches a circuit implemented in a DC-AC grid-tie converter [abstract]. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the features of Rufer in order to provide power to the grid system.
Regarding claim 10. Nari as modified teaches a circuit comprising the five-level DC-AC converter of claim 1 [as shown in claim 1]. However, Nari as modified does not explicitly mention a DC-AC grid-tie converter. Rufer teaches a DC-AC grid-tie converter [abstract]. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the features of Rufer in order to provide power to the grid system.
Regarding claim 12. Nari as modified teaches a circuit comprising the five-level three-phase DC-AC [¶11] converter of claim 11. However, Nari as modified does not explicitly mention a DC-AC grid-tie converter. Rufer teaches a DC-AC grid-tie converter [abstract]. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the features of Rufer in order to provide power to the grid system.
Allowable Subject Matter
Claims 7 and 13-14 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if the claim objections stated above were overcome.
Examiner Note
The examiner cites particular columns and lines numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bryan Perez whose telephone number is (571)272-8837. The examiner can normally be reached on Mon.-Fri. (7:30 – 5:00).
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Monica Lewis, can be reached on (571) 272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRYAN R PEREZ/Examiner, Art Unit 2838