DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-10 and 12-19 are rejected under 35 U.S.C. 103 as being unpatentable over Ahn et al. (US PGPub 2021/0118391), Kwon et al. (US PGPub 2021/0193047), Gandhi et al. (US PGPub 2024/0096275) and Lim et al. (US PGPub 2022/0358872).
Regarding claim 1, Ahn discloses a method comprising:
determining a brightness level associated with a brightness mode of a display ([0058], “the power management circuit 120 may generate the panel driving voltages having first voltage levels in response to the bank select signal BSS having a first level in a first mode (e.g., a two-dimensional (2D) mode, a standard dynamic range (SDR) mode, etc.), and may generate the panel driving voltages having second voltage levels in response to the bank select signal BSS having a second level in a second mode (e.g., a three-dimensional (3D) mode, a high dynamic range (HDR) mode, etc.)” where SDR and HDR are brightness modes);
determining an electroluminescence voltage based on the brightness level associated with the brightness mode of the display ([0064], “The DC-DC converter 230 may generate panel driving voltages having the first voltage levels based on the first voltage information VI1 or the second voltage information VI2, depending on which it receives from the voltage information selecting circuit 220. The panel driving voltages generated by the DC-DC converter 230 may include an analog driving voltage AVDD and a half analog driving voltage HAVDD provided to a data driver, and may further include a high gate voltage VGH and a low gate voltage VGL provided to a gate driver” where AVDD is the electroluminescence voltage); and
supplying an electroluminescence voltage to a display panel ([0058], “Accordingly, the voltage levels of the panel driving voltages may be efficiently changed according to an operating mode of the display device 100”);
wherein the display is an organic light-emitting diode display ([0053], “The display panel 110 may be a liquid crystal display (LCD) panel where each pixel PX includes a switching transistor and a liquid crystal capacitor coupled to the switching transistor, or an organic light emitting diode (OLED) display panel where each pixel PX includes at least one capacitor, at least one transistor and an OLED”).
While Ahn teaches the use of a processor (element 1110), it has been known that a scaler is a specific type of processor. Additionally, while Ahn teaches adjusting an electroluminescent voltage ([0064], generating voltages for AVDD), it has been known to supply an electroluminescent voltage that is less than or equal to the maximum electroluminescent voltage to a display panel. In a similar field of endeavor of adjusting an electroluminescent voltage in a display device, Kwon discloses a scaler ([0041], “The host system 10 may include a system on chip (SoC) including a scaler”); determining, by a timing controller ([0052], “the timing controller 20 may appropriately shift the ELVDD reference profile PF1”), a maximum electroluminescence voltage ([0053], “In the ELVDD reference profile PF1, ELVDD adjusting levels for adjusting the high-potential pixel voltage ELVDD to be applied to the pixels P of an image may be defined”).
In view of the teachings of Ahn and Kwon it would have been obvious to use the scaler, as taught by Kwon, to perform the functions of the processor of Ahn, as a known specific type of processor. Additionally, it would have been obvious to one of ordinary skill in the art to vary the electroluminescent voltage according to brightness, as taught by Kwon, in the system of Ahn, in order to reduce power consumption (Kwon: [0063]).
While the combination of Ahn and Kwon discloses generating power voltages based on a brightness mode, it has been known to perform a mapping between maximum electroluminescence voltage and brightness levels. Additionally, while Ahn and Kwon discloses a power management circuit, a PMIC is a specific type of known power management circuit. In a similar field of endeavor of display devices, Gandhi discloses determining the maximum electroluminescence voltage based on a mapping of the maximum electroluminescence voltage to the brightness level associated with the brightness mode of the display ([0034], “In such an embodiment, a look-up-tables (LUTs) (not shown) may be used to program ELVDD vs. DBV settings” and [0021], “having the capability to vary ELVDD, shown as 2.9V and 3.0V, respectively, allows a variable increase in data range when needed for pixels to achieve higher luminance output. Although two increases in ELVDD are shown in FIG. 1B, it is understood by one skilled in the art, that any number of increases may be used to enable higher capability in special high brightness modes”);
providing the maximum electroluminescence voltage to a power management integrated circuit ([0027], “The power management subsystem 3010 may be implemented as a power management integrated circuit (PMIC) 3100 configured to enable a variable ELVDD reference voltage to achieve higher peak luminance while minimizing the static power cost incurred at lower luminance”), subsequent to determining the maximum electroluminescence voltage based on the mapping of the maximum electroluminescence voltage to the maximum brightness level (where the voltage can only be provided after it is determined) and
supplying, by the power management integrated circuit, an electroluminescence voltage that is less than the maximum electroluminescence voltage to a display panel ([0032], “Variable ELVDD features implemented in the display driver integrated circuit 3300 allows for a settable ELVDD at each calibrated brightness tap, similar to other pixel and emission voltages”).
In view of the teachings of Ahn, Kwon and Gandhi, it would have been obvious to one of ordinary skill in the art to including the mapping relationship of Gandhi within the power management system of Ahn and Kwon, for the purpose of providing a variable ELVDD reference voltage to achieve higher peak luminance while minimizing the static power cost incurred at lower luminance (Gandhi: [0027]).
While the combination of Ahn, Kwon and Gandhi teaches a plurality of brightness modes, it has been known to have the brightness mode be in response to receiving a change. In a similar field of endeavor of power management in display devices, Lim discloses selecting a brightness mode of a display in response to receiving a change notification event ([0132]-[0133], “The current sensor 200 transmits a current sensing value CL to the signal controller 150. The current sensing value CL may be indicative of the luminance of the image displayed by the display unit 100”…” The signal controller 150 may control the driving of the first power supply 130 and the second power supply 140 according to the current sensing value CL”); determining a maximum brightness level associated with the brightness mode of the display subsequent to the selecting of the brightness mode based on the change notification event ([0133], “The signal controller 150 may control the driving of the first power supply 130 and the second power supply 140 according to the current sensing value CL. The first power supply 130 and the second power supply 140 may supply the power voltages ELVDD1, ELVDD2, ELVSS1, and ELVSS2 for driving respective pixels. For example, the signal controller 150 may transmit the control signal CONT3 to the first power supply 130 so that the first power supply 130 may transmit the power voltages ELVDD1 and ELVSS1 to the display unit 100. Further, the signal controller 150 may transmit the control signal CONT4 to the second power supply 140 so that the second power supply 140 may transmit the power voltages ELVDD2 and ELVSS2 to the display unit 100. The first power supply 130 and the second power supply 140 may be connected to the voltage supply lines formed on the display unit 100. In addition, the first power supply 130 and the second power supply 140 may generate an additional voltage for driving pixels and may supply the same”).
In view of the teachings of Ahn, Kwon, Gandhi and Lim, it would have been obvious to one of ordinary skill in the art to include the mode information of Lim within the system of Ahn, Kwon and Gandhi, as a known alternative implementation in display brightness control and also for the purpose of providing device efficiency by using power with relatively high efficiency (Lim: [0007]).
Regarding claim 2, the combination of Ahn, Kwon, Gandhi and Lim further discloses wherein the brightness mode is mapped to a maximum brightness level value (Gandhi: [0034], “In such an embodiment, a look-up-tables (LUTs) (not shown) may be used to program ELVDD vs. DBV settings” and [0021], “having the capability to vary ELVDD, shown as 2.9V and 3.0V, respectively, allows a variable increase in data range when needed for pixels to achieve higher luminance output. Although two increases in ELVDD are shown in FIG. 1B, it is understood by one skilled in the art, that any number of increases may be used to enable higher capability in special high brightness modes”).
Regarding claim 3, the combination of Ahn, Kwon, Gandhi and Lim further discloses wherein the maximum brightness level is equal to or less than the maximum brightness level value (Gandhi: [0021], “having the capability to vary ELVDD, shown as 2.9V and 3.0V, respectively, allows a variable increase in data range when needed for pixels to achieve higher luminance output”).
Regarding claim 5, the combination of Ahn, Kwon, Gandhi and Lim further discloses wherein the maximum brightness level value is mapped to a maximum electroluminescence voltage (Gandhi: [0034], “In such an embodiment, a look-up-tables (LUTs) (not shown) may be used to program ELVDD vs. DBV settings”).
Regarding claim 6, the combination of Ahn, Kwon, Gandhi and Lim further discloses wherein an electroluminescence voltage that is less than or equal to the maximum electroluminescence voltage is supplied by a power management integrated circuit (Gandhi: [0027], “The power management subsystem 3010 may be implemented as a power management integrated circuit (PMIC) 3100 configured to enable a variable ELVDD reference voltage to achieve higher peak luminance while minimizing the static power cost incurred at lower luminance”).
Regarding claim 7, the combination of Ahn, Kwon, Gandhi and Lim further discloses in response to detecting a change in the brightness mode, adjusting the electroluminescence voltage supplied by the power management integrated circuit (Ahn: [0058], “the power management circuit 120 may generate the panel driving voltages having first voltage levels in response to the bank select signal BSS having a first level in a first mode (e.g., a two-dimensional (2D) mode, a standard dynamic range (SDR) mode, etc.), and may generate the panel driving voltages having second voltage levels in response to the bank select signal BSS having a second level in a second mode (e.g., a three-dimensional (3D) mode, a high dynamic range (HDR) mode, etc.). Accordingly, the voltage levels of the panel driving voltages may be efficiently changed according to an operating mode of the display device 100”).
Regarding claim 8, the combination of Ahn, Kwon, Gandhi and Lim further discloses an information handling system (Ahn: 0099] and fig. 14, electronic device 1100), comprising:
a processor (Ahn: [0100], “The processor 1110 may be hardware for performing various computing functions or tasks”); and
a memory storing instructions that when executed cause the processor to perform operations (Ahn: [0101], “The memory device 1120 may store data for operations of the electronic device 1100”) including:
the steps of the method of claim 1 and therefore interpreted and rejected based on similar reasoning.
Claims 9, 10 and 12-14 are system claims drawn to the method of claims 2, 3 and 5-7 respectively and are therefore interpreted and rejected based on similar reasoning.
Regarding claim 15, the combination of Ahn, Kwon, Gandhi and Lim further discloses a non-transitory computer-readable medium to store instructions that are executable to perform operations (Ahn: [0101], “The memory device 1120 may store data for operations of the electronic device 1100”) comprising:
the steps of the method of claim 1 and therefore interpreted and rejected based on similar reasoning.
Claims 16-19 are computer-readable medium claims drawn to the method of claims 2, 3, 5 and 6 respectively and are therefore interpreted and rejected based on similar reasoning.
Claims 4, 11 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ahn, Kwon, Gandhi and Lim in view of Pyun et al. (US PGPub 2023/0290303).
Regarding claim 4, while the combination of Ahn, Kwon, Gandhi and Lim teaches the power management circuit performs mode selection based on data type (Ahn: [0058]), user mode selection has been a known alternative to automatic mode selection. In a similar field of endeavor of mode selection, Pyun discloses wherein the brightness mode setting is selected by a user ([0118], “The display mode set by the user may include a set mode, a standard dynamic range (SDR) mode, or a high dynamic range (HDR) mode”).
In view of the teachings of Ahn, Kwon, Gandhi, Lim and Pyun, it would have been obvious to one of ordinary skill in the art to include the user mode selection of Pyun in the method of Ahn, Kwon, Gandhi and Lim, for the purpose of providing user selection which is known to offer the user greater flexibility since the user can choose based on their specific needs, while automatic selection might not always make the optimal choice for every situation.
Claim 11 is a system claim drawn to the method of claim 4 and is therefore interpreted and rejected based on similar reasoning.
Claim 20 is a computer-readable medium claim drawn to the method of claim 4 and is therefore interpreted and rejected based on similar reasoning.
Response to Arguments
Applicant’s arguments with respect to claims 1, 8 and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/EJF/
/BENJAMIN C LEE/Supervisory Patent Examiner, Art Unit 2629
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