DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 6, 10-16 are rejected under 35 U.S.C. 102(a)(1)(2) as being anticipated by Kim et al US 11189491 B2 hereinafter, "Kim".
Regarding claim 1, Kim discloses a method of forming a pattern, the method comprising: forming a first recess (Fig 12B. First recesses R1 and second recesses R2) in a substrate (substrate 101);
forming a first mask layer (Fig 13 mask material solution layer 201 which "may include a carbon material… In an implementation, the mask material solution may be, e.g., a spin-on hardmask solution" [Col 3 Lines 55-60]) on the substrate that extends into the first recess (shown in Fig 13);
performing a heat treatment process on the first mask layer ("the mask material solution layer 201 may be cured…. The first annealing process may be performed at a temperature of about 80 degrees Celsius to about 250 degrees Celsius for about 10 seconds to about 5 minutes" [Col 9 lines 5-15]);
removing an upper portion of the first mask layer to form a first mask in the first recess (mask material layer undergoes a second annealing process which "may evaporate a solvent and a remaining fluorine additive 202 from the non-cured mask material solution layer 201" [Fig 15, Col 11 lines 8-10]), the first mask comprising a lower portion of the first mask layer (201 was cured into the first mask pattern 301 shown in Fig 17);
forming a second mask (additional mask layer 401 Fig 18) on the substrate and the first mask, the second mask (Fig 19 additional mask patterns PM) comprising a material having a tolerance with respect to an etching process that is greater than that of the first mask ("401 may include, e.g., a silicon oxynitride layer" [Col 11 Lines 25-26], and it is possible for a silicon oxynitride (SiON) layer to achieve increased etch selectivity through iterative nitridizing cycles as disclosed in Jang et al. US6297162 B1, therefore the layer 401 disclosed in Kim has the ability to cover the second mask limitations of claim 1);
and performing an etching process on the substrate using the second mask as an etching mask to form the pattern on the substrate (Fig 19 additional mask patterns PM and openings OP1 and OP2).
Regarding claim 2, Kim discloses The method according to claim 1, wherein the first mask layer comprises spin-on-hardmask (SOH) (Kim Col 3 Lines 55-60, see discussion of claim 1 above), and wherein the second mask comprises amorphous carbon layer (ACL) (the material for the additional mask layer 401 is not limited in Kim and may contain other materials than the SiON mentioned above).
Regarding claim 3, Kim discloses The method according to claim 1, wherein the heat treatment process comprises a baking process that is performed at a temperature of about 145℃ to about 155℃ for about 60 seconds to about 150 seconds (see discussion of claim 1 above and Kim [Col 9 lines 5-15]).
Regarding claim 4, Kim discloses The method according to claim 1, wherein the removing the upper portion of the first mask layer comprises performing a rinse process using an organic solvent ("a rinse process may be performed to remove the upper portion of the mask material solution layer 201. The liquid material may include, e.g., a thinner, an alcohol, or a developer." [Col 6 lines 62-67]. It is well-known in the relevant arts that most thinners contain volatile organic compounds, alcohols are organic compounds containing hydroxyl groups, and developers commonly include alkaline organic compounds [see MPEP 2144.03 and Myers, Brian. (2005). Common solvents used in organic chemistry: Table of Properties. Division of Organic Chemistry, American Chemical Society]).
Regarding claim 6, Kim discloses The method according to claim 5, wherein an upper surface of the first mask layer is closer to the substrate on a portion of the substrate having the first recess thereon than on a portion of the substrate spaced apart from the first recess (201 Fig 3A and Fig 10), and wherein an upper surface of the second mask layer has a uniform height with respect to the substrate. (401 Fig 18)
Regarding claim 10, Kim discloses The method according to claim 1, wherein the substrate comprises a first region and a second region surrounding the first region, wherein the first recess extends into the first region of the substrate, and wherein the performing the etching process on the substrate comprises forming a second recess that extends into the second region of the substrate (regions 101a and 101b in Fig 19).
Regarding claim 11, Kim discloses The method according to claim 10, wherein a width and a depth of the second recess are greater than a width and a depth, respectively, of the first recess (see Fig 19, recess on the left is greater in width and see Fig 13 which displays differencing depths between the recesses due to an uneven mask layer and also regarding the depth, "the first recess R1 may have a bottom surface BS1 at a level substantially the same as or different from that of a bottom surface BS2 of the second recess R2" [Col 3 Lines 37-40] Fig 2).
Regarding claim 12, Kim discloses The method according to claim 10, wherein the forming the first recess comprises forming a plurality of first recesses spaced apart from each other and extending into the substrate (Fig 11 first recesses on the right side), the first recess being one of the plurality of first recesses, and wherein the performing the etching process on the substrate comprises forming the second recess between neighboring ones of the plurality of first recesses on the first region of the substrate (the first pattern P1 and second pattern P2 that create these recesses could be repeated next to each other, where the second recesses R2 would be in between first recesses R1, see Fig 2 and “the first patterns PT1 and the second patterns PT2 may include regularly repeating patterns along a first direction D1” [Col 2 lines 52-55]), the second recess having a width and a depth greater than a width and a depth, respectively, of each of the plurality of first recesses (the width of R2 > R1, and for the depth, "the first recess R1 may have a bottom surface BS1 at a level substantially the same as or different from that of a bottom surface BS2 of the second recess R2" [Col 3 Lines 37-40] Fig 2).
Regarding independent claim 13, Kim discloses A method of forming a pattern, the method comprising: forming a recess in a substrate (R1 and R2 Fig 12B); forming a first mask layer on the substrate that extends into the recess (210), wherein an upper surface of the first mask layer is closer to the substrate on a portion of the substrate having the recess thereon than on a portion of the substrate spaced apart from the recess (Fig 13); removing an upper portion of the first mask layer to form a first mask in the recess (removal of 202 in Fig 15-16), the first mask comprising a portion of the first mask layer; forming a second mask on the substrate and the first mask (PM Fig 19), the second mask comprising a material different from that of the first mask ([Col 11 lines 25-26]), and an upper surface of the second mask having a uniform height with respect to the substrate (this uniformity is not explicitly stated for the mask layer 401; however, the entire method disclosed in Kim serves to "provide a method of forming a mask pattern having improved flatness" with the goal of reducing "non-uniform thickness and a non-flat top surface" in hardmasks that makes it "difficult to accurately perform an exposure process" [Kim Col 13 Lines 13-20]. Kim also states "the mask pattern 301 may have a flat top surface, and the additional mask layer 401 may be formed to have a flat top surface" [Col 11 Line 27]. Therefore, the upper surface of 401 disclosed by Kim has a flat top and also must preserve the uniform height of each mask above the substate); and performing an etching process on the substrate using the second mask as an etching mask to form the pattern on the substrate (PM Fig 19).
Regarding claim 14, Kim discloses The method according to claim 13, wherein the first mask layer comprises spin-on-hardmask (SOH), and wherein the second mask comprises amorphous carbon layer (ACL) (Kim Col 3 Lines 55-60, see discussion of claim 1 above).
Regarding claim 15, Kim discloses The method according to claim 13, wherein the removing the upper portion of the first mask layer comprises performing a rinse process using an organic solvent ("a rinse process may be performed to remove the upper portion of the mask material solution layer 201. The liquid material may include, e.g., a thinner, an alcohol, or a developer." [Col 6 lines 62-67]. It is well-known in the relevant arts that most thinners contain volatile organic compounds, alcohols are organic compounds containing hydroxyl groups, and developers commonly include alkaline organic compounds [see MPEP 2144.03 and Myers, Brian. (2005). Common solvents used in organic chemistry: Table of Properties. Division of Organic Chemistry, American Chemical Society]).
Regarding claim 16, Kim discloses The method according to claim 15, further comprising, prior to removing the upper portion of the first mask layer, performing a heat treatment process on the first mask layer (see discussion of claim 1 above and Kim [Col 9 lines 5-15]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Jiang et al. “Process Optimization of Amorphous Carbon Hard Mask in Advanced 3D-NAND Flash Memory Applications”. (2021) Electronics, 10(12), 1374 hereinafter “Jiang”.
See claim 5: The method according to claim 1, wherein the forming the second mask comprises: performing a deposition process on the substrate and the first mask layer to form a second mask layer; and patterning the second mask layer to form the second mask. Kim discloses the method of claim 1 but fails to clearly disclose a description of a deposition process to form a second mask layer. However, in the same field of endeavor, Jiang discloses findings related to optimizing the variables in plasma-enhanced chemical vapor deposition (PECVD) while depositing amorphous carbon layers. Jiang, published in 2021, discloses the benefits of using amorphous carbon hard masks especially for its “high transparency, high etch selectivity, high durability for plasma, …” [Introduction lines 13-15].
Therefore, it would have been obvious to one having ordinary skill in the art, to apply deposition such as the PECVD process disclosed in Jiang to the formation of the second mask layer in Kim to “achieve sufficient etch selective ratio and film uniformity” [Conclusion lines 1-6].
Regarding claim 5, Kim in view of Jiang discloses the method according to claim 1, wherein the forming the second mask comprises: performing a deposition process (PECVD from Jiang) on the substrate (Kim Fig 13 substate 101) and the first mask layer (201) to form a second mask layer (401); and patterning the second mask layer to form the second mask (401 into Fig 19 PM).
Claims 7, 8, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Jiang, further in view of Park et al. US 9634012 B2, hereinafter “Park”.
Kim in view of Jiang discloses the method according to claim 5, but both references fail to disclose the third and fourth mask layers described in claim 7.
However, in the same field of endeavor, Park discloses a method of forming active patterns and manufacturing a semiconductor device. Kim clearly discloses a method of forming patters, but the combined teachings of Kim and Park disclose a method of manufacturing a semiconductor device that is functional for more applications. Park, in Figures 4-11 and Figure 42, discloses the method of creating the extra mask layers as well as patterns for forming device structures such as gates and a capacitor. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to preserve the patterns created in Kim and combine the disclosed method steps in Park for the purpose of overall creating a fully functional semiconductor device ([Park Col 1 lines 25-35] and see MPEP 2143 1A).
Regarding claim 7, Kim in view of Jiang further in view of Park discloses the method according to claim 5 (disclosed by Kim and Jiang, discussed above), further comprising: sequentially stacking a third mask layer (Modify the method of making patterns up to Fig 19 disclosed in Kim by adding more mask layers and method steps disclosed in Park, beginning in Park Fig 4 and the discussion thereof. The layer 150 in Park Fig 4 is an oxynitride, "for example, plasma enhanced silicon oxynitride (PE-SiON)" [Park Col 7 lines 35-37], so the layer 150 from Park Fig 4 is the same material as the previously defined second mask layer 401 disclosed in Kim Fig 18; therefore, allow the modification of the extra masks given in Park to be added on the second mask layer 401, thereby preserving the patterns created in Kim and adding more steps disclosed in Park for the purpose of overall creating a fully functional semiconductor device (see MPEP2143 1A).
Let the third mask be defined by mask 162 on the second mask Park Fig 4 "the first to fourth masks 162, 164, 172 and 174, respectively, may be formed by forming a second photoresist pattern (not shown) on the second mask layer, and sequentially etching the second and first mask layers using the second photoresist pattern as an etching mask" [Col 8 lines 4-9]) and a fourth mask layer (not shown, but used to etch the mask 162 in Fig 4) on the second mask layer; performing a photo process on the fourth mask layer to form a fourth mask (photoresist mask not shown, discussed in [Col 8 lines 4-9]); performing an etching process on the third mask layer using the fourth mask as an etching mask to form a third mask ([Col 8 lines 4-9]); and performing an etching process on the second mask layer using the third mask as an etching mask to form the second mask (Park Fig 11 shows the result of a dry etching process that occurred through the third mask 162 and reached the surface of the "second mask layer" which is 150 in Park and would synonymously be layer 401 in Kim once modified [see Park Col 9 lines 35-45]).
Regarding claim 8, Kim in view of Jiang further in view of Park discloses the method according to claim 7, wherein the third mask layer comprises silicon nitride (“mask layer {162} may be formed of an oxynitride, for example, PE-SiON” [Park Col 7 lines 61-65]), and wherein the fourth mask layer comprises a photoresist layer (Park Fig 4 photoresist layer (not shown) described in [Col 8 lines 4-9]).
Regarding claim 19, Kim in view of Jiang further in view of Park discloses the method according to claim 17 (see discussion of claim 17 below disclosed by Kim in view of Park only), wherein forming the second mask comprises: performing a deposition process (PECVD from Jiang) on the substrate and the first mask layer to form a second mask layer (Kim substrate 101, first mask layer 201, and second mask layer 401); and patterning the second mask layer to form the second mask (PM Fig 19), wherein an upper surface of the first mask layer on the first region of the substrate is closer to the substrate than on the second region of the substrate spaced apart from the first recess (see Kim Fig 4A height difference delta D1), and wherein an upper surface of the second mask layer has a uniform height with respect to the substrate (Fig 18 and [Col 13 lines 13-20]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Min et al. US 9589960 B1, hereinafter “Min”. Kim discloses the method of claim 1 but does not disclose using the third mask as an etching mask to remove an upper portion of the substrate.
However, in the same field of endeavor, Min discloses a method a creating a buried gate structure that uses multiple masks to create a recess and protect the substrate area around it.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of formation of the recess disclosed in Kim to include the additional third mask layer disclosed in Min to protect the surrounding substrate while creating the recess (see Min Fig 5B and discussion thereof [Col 10 lines 16-25]).
Regarding claim 9, it is the examiner's understanding of the figures, relevant text, and language of claim 9, that "a third mask" refers to mask layer 10 as seen in the instant application Fig 2 because the "first mask layer" in claim 9 must be referring to the specification's "second mask layer 20" which is the spin-on-hardmask (SOH) that is heated to form second mask 25 in Fig 5 [0023-0025]. Then, in Fig 7, the "third mask layer 30" is added, which would correspond to the second mask that is referred to in claim 1 and claimed to comprise amorphous carbon layer (ACL) [0030]. The ordering/numbering language throughout the claims seems to be consistent; however, this numbering is not consistent in the specification. For the record, a detailed description of the layers described below will be provided as to lessen any confusion. In the instant application Fig 3-7, it should be clear that 25 is the first mask (SOH), 30 is the second mask (ACL), and 10 is the third mask. Layer 10 is deposited first, and etched to create the first recesses 102.
Regarding claim 9, Kim in view of Min discloses The method according to claim 1, wherein the forming the first recess (Min Fig 9D two recesses) on the substrate (11) comprises:
forming a third mask (hard mask layer 17) on the substrate;
and performing an etching process using the third mask as an etching mask to remove an upper portion of the substrate (see Fig 5B gate trench 18),
wherein the first mask layer (capping layer 33 "may include a silicon oxide … may be a nitride-oxide-nitride structure" [Col 19 lines 35-40]) is formed on the third mask, and wherein an upper surface of the first mask is substantially coplanar with an upper surface of the third mask (see Fig 9E).
Claims 17, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Park et al. US 9634012 B2, hereinafter “Park”. Kim discloses the method of claim 1 which is similar to the first few lines in the method of claim 17, but Kim fails to disclose forming gate, isolation, bit line, and capacitor structures.
However, in the same field of endeavor, Park discloses a method of forming active patterns and manufacturing a semiconductor device which can be added to the method disclosed in Kim to create a device with uniform layers and multiple applications.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to preserve the patterns created in Kim and combine the disclosed method steps in Park the create the gate, isolation, bit line, and capacitor structures to create a fully functional semiconductor device ([Park Col 1 lines 25-35] and see MPEP 2143 1A).
Regarding independent claim 17, Kim in view of Park discloses method of manufacturing a semiconductor device (Park Fig 42), the method comprising: forming a first recess in a first region of a substrate (Kim Fig 12B recesses R1 and substrate 101), the substrate comprising the first region and a second region; forming a first mask layer (Kim 201) on the substrate that extends into the first recess; performing a heat treatment process on the first mask layer (Kim [Col 9 Lines 5-15]); removing an upper portion of the first mask layer to form a first mask in the first recess (first mask pattern 301 Kim Fig 17), the first mask comprising a portion of the first mask layer; forming a second mask (401 Kim Fig 18) on the substrate and the first mask, the second mask comprising a material having a tolerance with respect to an etching process that is greater than that of the first mask (Kim [Col 11 lines 25-26] and see Jang et al. US 6297162 B2 for further clarification); performing an etching process using the second mask as an etching mask on the substrate and the first mask to form second and third recesses (the second mask 401 is used as an etching mask to create the openings OP1 and OP2 in Fig 19) in the first and second regions (101a and 101b), respectively, of the substrate, a first active pattern being defined by the first and second recesses on the first region of the substrate (Kim Fig 6 region 101a) and a second active pattern being defined by the third recess on the second region of the substrate (Kim Fig 6 region 101b); forming an isolation structure in the first to third recesses ("the substrate 101 may have various device isolation structures" [Kim Col 2 lines 35-40];
forming a gate structure through the first active pattern and the isolation structure in the first region of the substrate (Park gate structure 360 Fig 42, "a first gate structure may be formed through the first active patterns" [Col 3 lines 24-25]); forming a bit line structure (bit line structure 520 Fig 42) on a portion of the first active pattern and a portion of the isolation structure; forming a contact plug structure (contact plug 573 Fig 42) on the portion of the first active pattern; and forming a capacitor on the contact plug structure (capacitor 620 Fig 42).
Regarding claim 18, Kim in view of Park discloses the method according to claim 17, wherein the first mask layer comprises spin-on-hardmask (SOH) (Kim Col 3 Lines 55-60, see discussion of claim 1 above), and wherein the second mask comprises amorphous carbon layer (ACL) (the material for the additional mask layer 401 is not limited in Kim and may contain other materials than the SiON mentioned above).
Regarding claim 20, Kim in view of Park discloses the method according to claim 17, wherein the forming the first recess comprises forming a plurality of first recesses spaced apart from each other and extending into the substrate (R1 Kim Fig 12A), the first recess being one of the plurality of first recesses, and wherein the performing the etching process using the second mask (401, see etching process between Park Figs 19-21 that creates holes H1 and H2 all the way down to the substrate 101) comprises forming the second recess between neighboring ones of the plurality of first recesses (see Kim Fig 2 that displays the patterns and recesses, “the first patterns PT1 and the second patterns PT2 may include regularly repeating patterns along a first direction D1” [Col 2 lines 52-55]), the second recess having a width and a depth greater than a width and a depth, respectively, of each of the plurality of first recesses (the width of R2 > R1, and for the depth, "the first recess R1 may have a bottom surface BS1 at a level substantially the same as or different from that of a bottom surface BS2 of the second recess R2" [Col 3 Lines 37-40] Fig 2).
Conclusion
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Kye et al. US 2017/0069726 A1 which discloses a method for manufacturing a semiconductor structure including a memory cell region and a peripheral circuit employing multiple hard mask layers
Lee et al. US 2023/0035456 A1 which discloses a method of forming a wiring structure within patterns created by multiple etching masks
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA MICKEY whose telephone number is (571)270-3109. The examiner can normally be reached M-F, 8am to 5pm ET.
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/TERESA N MICKEY/Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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