DETAILED ACTION
This communication is in response to the Application No. 18/631,945 filed on April 10, 2024
in which Claims 1-12 are presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-12 are rejected on the ground of nonstatutory double patenting as being unpatentable over Claims 1-10 of U.S. Patent No. 12,632,717. Although the claims at issue are not identical, they are not patentably distinct from each other because the subject matter claimed in the instant application is disclosed by the claims of U.S. Patent No. 11,783,189, since the instant application claims common subject matter.
Note: The bolded portions below highlight the differences between the instant application and the Patent, which illustrates the anticipatory relationship of the claim limitations at issue:
Instant Application (18/631,945)
U.S. Patent (US 12,632,717)
Claim 1: A neuromorphic device comprising a control unit,
wherein the control unit is configured to be connectable to a memristor having electrical characteristics in which conductance change occurs stochastically when a writing signal is applied to the memristor,
wherein the writing signal is determined based on a necessary value of the conductance change amount of the memristor which is calculated from an update value of a weight of a neural network and an expected value by which the conductance of the memristor changes when a reference writing signal is applied to the memristor.
Claim 1: A neuromorphic device comprising a control unit,
wherein the control unit is configured to be connectable to a memristor having electrical characteristics in which conductance change occurs stochastically when a writing signal is applied to the memristor,
wherein the writing signal is determined based on a necessary value of the conductance change amount of the memristor which is calculated from an update value of a weight of a neural network and an expected value by which the conductance of the memristor changes when a reference writing signal is applied to the memristor,
and wherein the magnetic domain wall moving element includes a first ferromagnetic layer including a magnetic domain wall, a second ferromagnetic layer, and a nonmagnetic layer interposed between the first ferromagnetic layer and the second ferromagnetic layer.
Claim 2: The neuromorphic device according to claim 1, wherein the expected value is calculated as a product of a probability with which the conductance of the memristor changes when the reference writing signal is applied to the memristor and an ideal value when the conductance of the memristor changes ideally when the reference writing signal is applied to the memristor.
Claim 2: The neuromorphic device according to claim 1, wherein the expected value is calculated as a product of a probability with which the conductance of the memristor changes when the reference writing signal is applied to the memristor and an ideal value when the conductance of the memristor changes ideally when the reference writing signal is applied to the memristor.
Claim 3: The neuromorphic device according to claim 1, wherein the control unit is configured to set the expected value based on the conductance of the memristor.
Claim 3: The neuromorphic device according to claim 1, wherein the control unit is configured to set the expected value based on the conductance of the memristor.
Claim 4: The neuromorphic device according to claim 1, wherein the control unit is configured to set the expected value based on an application voltage of the reference writing signal.
Claim 4: The neuromorphic device according to claim 1, wherein the control unit is configured to set the expected value based on an application voltage of the reference writing signal.
Claim 5: The neuromorphic device according to claim 1,
wherein the control unit includes a temperature sensor,
and wherein the control unit is configured to set the expected value based on a temperature measured by the temperature sensor.
Claim 5: The neuromorphic device according to claim 1,
wherein the control unit includes a temperature sensor,
and wherein the control unit is configured to set the expected value based on a temperature measured by the temperature sensor.
Claim 6: The neuromorphic device according to claim 1, further comprising a memristor array connected to the control unit,
wherein the memristor array includes a plurality of memristors,
and wherein at least one of the plurality of memristors is the memristor.
Claim 6: The neuromorphic device according to claim 1, further comprising a memristor array connected to the control unit,
wherein the memristor array includes a plurality of memristors,
and wherein at least one of the plurality of memristors is the memristor.
Claim 7: The neuromorphic device according to claim 1, further comprising a memristor array connected to the control unit,
wherein the memristor array includes a plurality of the memristors,
and wherein the control unit is configured to set the expected value based on a position of the memristor in the memristor array.
Claim 7: A neuromorphic device comprising a control unit,
wherein the control unit is configured to be connectable to a memristor having electrical characteristics in which conductance change occurs stochastically when a writing signal is applied to the memristor,
wherein the writing signal is determined based on a necessary value of the conductance change amount of the memristor which is calculated from an update value of a weight of a neural network and an expected value by which the conductance of the memristor changes when a reference writing signal is applied to the memristor,
wherein the memristor array includes a plurality of the memristors,
and wherein the control unit is configured to set the expected value based on a position of the memristor in the memristor array.
Claim 8: The neuromorphic device according to claim 1, further comprising:
a semiconductor wafer;
and a memristor array connected to the control unit and formed on the semiconductor wafer,
wherein the memristor array includes a plurality of the memristors,
and wherein the control unit is configured to set the expected value based on a position of the memristor on the semiconductor wafer.
Claim 8: A neuromorphic device comprising a control unit,
a semiconductor wafer;
and a memristor array connected to the control unit and formed on the semiconductor wafer,
wherein the control unit is configured to be connectable to a memristor having electrical characteristics in which conductance change occurs stochastically when a writing signal is applied to the memristor,
wherein the writing signal is determined based on a necessary value of the conductance change amount of the memristor which is calculated from an update value of a weight of a neural network and an expected value by which the conductance of the memristor changes when a reference writing signal is applied to the memristor,
wherein the memristor array includes a plurality of the memristors,
and wherein the control unit is configured to set the expected value based on a position of the memristor on the semiconductor wafer.
Claim 9: The neuromorphic device according to claim 1, further comprising a memristor array connected to the control unit,
wherein the memristor array includes a plurality of the memristors,
and wherein the control unit is configured to set the expected value based on behavior of the conductance change when the reference writing signal is applied to at least one memristor in the memristor array.
Claim 9: A neuromorphic device comprising a control unit,
and a memristor array connected to the control unit,
wherein the control unit is configured to be connectable to a memristor having electrical characteristics in which conductance change occurs stochastically when a writing signal is applied to the memristor,
wherein the writing signal is determined based on a necessary value of the conductance change amount of the memristor which is calculated from an update value of a weight of a neural network and an expected value by which the conductance of the memristor changes when a reference writing signal is applied to the memristor,
wherein the memristor array includes a plurality of the memristors,
and wherein the control unit is configured to set the expected value based on behavior of the conductance change when the reference writing signal is applied to at least one memristor in the memristor array.
Claim 10: The neuromorphic device according to claim 9, wherein the memristor in which the behavior of the conductance change when the reference writing signal is applied thereto is evaluated is a reference element for evaluation.
Claim 10: The neuromorphic device according to claim 9, wherein the memristor in which the behavior of the conductance change when the reference writing signal is applied thereto is evaluated is a reference element for evaluation.
Claim 11: The neuromorphic device according to claim 1, wherein the memristor is a magnetic domain wall moving element,
and wherein the magnetic domain wall moving element includes a first ferromagnetic layer including a magnetic domain wall, a second ferromagnetic layer, and a nonmagnetic layer interposed between the first ferromagnetic layer and the second ferromagnetic layer.
Claim 1: A neuromorphic device comprising a control unit,
wherein the control unit is configured to be connectable to a memristor having electrical characteristics in which conductance change occurs stochastically when a writing signal is applied to the memristor,
wherein the writing signal is determined based on a necessary value of the conductance change amount of the memristor which is calculated from an update value of a weight of a neural network and an expected value by which the conductance of the memristor changes when a reference writing signal is applied to the memristor,
and wherein the magnetic domain wall moving element includes a first ferromagnetic layer including a magnetic domain wall, a second ferromagnetic layer, and a nonmagnetic layer interposed between the first ferromagnetic layer and the second ferromagnetic layer.
Claim 12: A method of controlling a neuromorphic device, the method comprising:
a preliminary evaluation step of calculating an expected value by which conductance of a memristor changes when a reference writing signal is applied to the memristor, the memristor having electrical characteristics in which conductance change occurs stochastically when a writing signal is applied to the memristor;
a weight updating step of calculating an update value of a weight through learning using a neural network;
a conductance converting step of calculating a necessary value of the conductance change amount of the memristor from the update value of the weight;
and a signal determining step of determining the writing signal which is actually applied to the memristor based on the necessary value and the expected value.
Claim 1: A neuromorphic device comprising a control unit,
wherein the control unit is configured to be connectable to a memristor having electrical characteristics in which conductance change occurs stochastically when a writing signal is applied to the memristor,
wherein the writing signal is determined based on a necessary value of the conductance change amount of the memristor which is calculated from an update value of a weight of a neural network and an expected value by which the conductance of the memristor changes when a reference writing signal is applied to the memristor,
and wherein the magnetic domain wall moving element includes a first ferromagnetic layer including a magnetic domain wall, a second ferromagnetic layer, and a nonmagnetic layer interposed between the first ferromagnetic layer and the second ferromagnetic layer.
Instant claims are anticipated by the patent claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12 are rejected under 35 U.S.C. 103 as being unpatentable over Al Misba et al. (hereafter Al Misba, a non-patent literature reference titled “Energy efficient learning with low resolution stochastic domain wall synapse for deep neural network”) in view of Nugent et al. (hereinafter Nugent) (US 9679242).
Regarding Claim 1, Al Misba teaches:
a neuromorphic device comprising a control unit (Al Misba, Page 6 – Section III, “Fig. 2b given that the peripheral circuitry is designed to provide the appropriate scaling”, thus a control unit is disclosed),
wherein the control unit is configured to be connectable to […] having electrical characteristics in which conductance change occurs stochastically when a writing signal is applied to […] (Al Misba, Page 4 – Section II, “a combination of fixed amplitude and fixed time current pulse ‘‘or clocking signal’’ injected in the heavy metal layer and a varying amplitude ‘‘control’’ voltage pulse applied across the piezoelectric translates the domain wall to different distances along the racetrack. Different positions of the DW lead to different conductances of the MTJ thus forming a voltage programmable non-volatile synapse”, & Page 4 – Section II, “The distribution of equilibrium DW positions for five different programming voltages, represented by different perpendicular magnetic anisotropy (PMA) coefficient, Ku, in addition to fixed amplitude and fixed time spin orbit torque (SOT) generating current pulse (35 × 1010Am2 applied for 1 ns) in the presence of room temperature thermal noise are shown in Fig. 1c” & Page 4 – Section II, “Thus, in the presence of room temperature thermal noise and structural irregularities (edge roughness) DW motion becomes significantly stochastic. As a result, an average variance of ∼ 90 nm can be seen for different DW mean positions in our modelled racetrack”, thus wherein the control unit is configured to be connectable to […] having electrical characteristics in which conductance change occurs stochastically when a writing signal is applied to […] is disclosed, because Al Misba teaches applying a current pulse having a fixed amplitude and fixed duration together with a variable control voltage pulse to a domain wall MTJ synapse, thereby moving the domain wall to different positions and producing different conductance values. Al Misba further teaches that thermal noise and structural irregularities cause the domain wall motion, and therefore the resulting conductance change, to occur stochastically. The circuitry supplying the current and control voltage pulses corresponds to the control unit, the current pulse and control voltage pulse correspond to the writing signal, and the stochastic variation in domain wall position corresponds to stochastic variation in MTJ conductance)
wherein the writing signal is determined based on a necessary value of the conductance change amount of […] which is calculated from an update value of a weight of a neural network […] (Al Misba, Page 6 – Section III, “Finally, the derivative of the cost function with respect to the weights is calculated, which determines the weight update signal, Wij for the weights connected between layer l neuron i and layer l + 1 neuron j”, Page 6 – Section III, “We note that these high precision weights are different from the actual synaptic weights (or equivalent conductances) provided by the DW device that are quantized and of low precision. However, we use these high precision weights to update the DW device weights (conductances)”, Page 6 – Section III, “After quantization, a programming pulse is generated to update the DW device weights to the quantized value, a target that is similar to the quantized neural network learning algorithm [30]. We note that, the cost gradients with respect to the prior quantization quantities are zero, so to backpropagate gradients through weight quantization we apply ‘‘straight through estimator’’ approach similar to that used in”, Page 6 – Section III, “After each forward and backward pass in the analog crossbar array, these weights are updated according to Eq. 5. Then, these weights are clipped and quantized so that they lie between −1 to 1. After that, a programming pulse is sent to the DW device to update its synaptic weight value to the quantized value. For example, in 5-level quantization (5-state for the synaptic device) the quantized weights can be of any value from the set Wq ∈ (−1,−0.5,0,0.5,1). Five different programming voltages can be applied to the device, which results in Ku = 8, 7.75, 7.5, 7.25 and 7.0 (× 105) J m3 to achieve five different quantized weights of −1, −0.5, 0, 0.5 and −1 respectively as seen from Fig. 1d (DW device weights, Wij = < mz > according to Eq. 4)”, thus
Al Misba does not explicitly teach […] a memristor […] the memristor, and […] the memristor […] and an expected value by which the conductance of the memristor changes when a reference writing signal is applied to the memristor.
However, Nugent teaches:
[…] a memristor […] the memristor (Nugent, Abstract, “A memristor apparatus includes meta-stable switching elements and an AHAH (Anti-Hebbian and Hebbian) feedback mechanism that operates the meta-stable switching elements by controlling the electric field across the meta-stable switching elements. The meta-stable switching elements form a device with an electrical resistance”, thus […] a memristor […] the memristor is disclosed, because Nugent teaches a memristor apparatus comprising metastable switching elements that form a device having electrical resistance. Nugent’s memristor apparatus corresponds to the memristor, and the electrical resistance formed by the metastable switching elements provides the memristor’s conductance)
[…] the memristor […] and an expected value by which the conductance of the memristor changes when a reference writing signal is applied to the memristor (Nugent, Par. [0045], “Given a total of No open channels, out of N total channels, the update to the connection can be given as the difference between the plastic update, P, and the thermal breakdown, B. The plastic update and the thermal breakdown are dependant on the number of open channels. However, the plastic update can only act on closed channels. In other words, a channel, once opened, can only be closed. If it is open, the probability of closing is given by E(T) as indicated in equations ”, & Par. [0066], “The exact positions of every particle, as well as all of the forces applied to it, are not known. A computationally tractable model must consider time-averaged approximations. Random thermal motion seeks to disperse the particles through the solution. The application of a voltage difference will increase the probability that a particle will bridge the gap between pre- and post-synaptic electrodes. As a first approximation, we may treat the instantaneous probability that a connection will form, or a conduction channel will open, as proportional to the square of the voltage difference between pre- and post-synaptic electrodes”, & Par. [0101], “By varying the time periods of both the evaluate and feedback phases, as well a changing the supply voltages, one can “dial in” the correct plastic probability update”, thus […] the memristor […] and an expected value by which the conductance of the memristor changes when a reference writing signal is applied to the memristor is disclosed, because Nugent teaches calculating an update to a connection based on the difference between the probability based opening of conducting channels and the thermal closing of conducting channels. Nugent further teaches that an applied voltage difference increases the probability that a conducting channel will open and that the voltage and duration of the evaluate and feedback phases may be adjusted to obtain the appropriate probability update. The time averaged net change in the number of open conducting channels corresponds to the expected value by which conductance changes, and the applied voltage during the evaluate and feedback phases corresponds to the reference writing signal)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine Al Misba with Nugent by incorporating Nugent’s probability based memristor update model into Al Misba’s stochastic domain wall synapse programming system. Al Misba teaches calculating a neural network weight update, converting the updated weight into a target device conductance, and applying a programming pulse to obtain the target conductance, while also recognizing that thermal noise and structural irregularities cause the resulting conductance change to vary stochastically. Nugent teaches determining a connection update based on the probability that conducting channels will transition between conductive and nonconductive states in response to an applied voltage. Therefore, a POSITA would have been motivated to use Nugent’s probability based expected conductance response when determining Al Misba’s programming pulse so that the pulse accounts for both the required conductance change associated with the neural network weight update and the expected response of the device to the applied signal, thereby reducing the difference between the intended neural network weight and the actual programmed conductance and improving the reliability and accuracy of the neuromorphic learning process (Nugent, Par. [0055], “The application of a voltage gradient across pre and post synaptic electrode leads to a non zero probability that a nanowire 2231 will transition from the OFF state to the ON state. In addition, the application of a voltage to the junction in the ON state will lead to a non zero probability that nanowire 2231 will transition from the ON state to the OFF state. The application of pre and post synaptic voltage pulses, as outlined in this disclosure, leads to a reliable synaptic junction suitable for object recognition and universal logic function”)
Regarding Claim 2, Al Misba combined with Nugent teaches all the limitations of claim 1 as cited above and Nugent further teaches:
wherein the expected value is calculated as a product of a probability with which […the conductance…] of the memristor changes when the reference writing signal is applied to the memristor and an ideal value when […the conductance….] of the memristor changes ideally when the reference writing signal is applied to the memristor (Nugent, Par. [0045], “Given a total of No open channels, out of N total channels, the update to the connection can be given as the difference between the plastic update, P, and the thermal breakdown, B. The plastic update and the thermal breakdown are dependant on the number of open channels. However, the plastic update can only act on closed channels”, & Par. [0046], “In equations (3) indicated above, H(No) represents a Plasticity Probability Field (PPF), which will be discussed shortly. The stable points of equations (3) occur when the plastic update equals the thermal breakdown”, & Par. [0050], “For a given No, equation (5) provides the IP that a closed channel will open. If equations (4) and (5) are graphed, their intersection represents the equilibrium number of open channels”, & Par. [0066], “The application of a voltage difference will increase the probability that a particle will bridge the gap between pre- and post-synaptic electrodes. As a first approximation, we may treat the instantaneous probability that a connection will form, or a conduction channel will open, as proportional to the square of the voltage difference between pre- and post-synaptic electrodes”, & Par. [0118], “The attraction of particles to the pre- and post-synaptic electrode gaps correlate with an increased conductance. By providing an increased voltage difference to mirror a plasticity rule, the system can auto-regulate and converge to connection strengths suitable for information extraction”, thus wherein the expected value is calculated as a product of a probability with which […the conductance…] of the memristor changes when the reference writing signal is applied to the memristor and an ideal value when […the conductance…] of the memristor changes ideally when the reference writing signal is applied to the memristor is disclosed, because Nugent teaches determining the plastic update P based on the Plasticity Probability Field and the number N of conducting channels available to change state. The Plasticity Probability Field corresponds to the probability with which conductance changes because it represents the probability that a closed conducting channel will open in response to the applied voltage difference. The number N of available channels corresponds to the ideal value because it represents the conductance change that would occur if the available channels transitioned to the open state. The plastic update P corresponds to the expected value because it represents the probability weighted number of conducting channels expected to open, and Nugent teaches that the opening of conducting channels correlates with increased conductance)
Regarding Claim 3, Al Misba combined with Nugent teaches all the limitations of claim 1 as cited above and Nugent further teaches:
wherein […the control unit…] is configured to set the expected value based on […the conductance…] of the memristor (Nugent, Par. [0045], “Given a total of No open channels, out of N total channels, the update to the connection can be given as the difference between the plastic update, P, and the thermal breakdown, B. The plastic update and the thermal breakdown are dependant on the number of open channels”, & Par. [0073], “The accumulated probability over both the evaluate and feedback phase is generally responsible for the connection update”, & Par. [0118], “The attraction of particles to the pre and post synaptic electrode gaps correlate with an increased conductance”, thus wherein […the control unit…] is configured to set the expected value based on […the conductance…] of the memristor is disclosed or suggested, because Nugent teaches that the accumulated probability determines the connection update P and that P depends on the number of open conducting channels. Because the number of open conducting channels represents the conductance of the connection, determining P based on the number of open channels corresponds to setting the expected value based on the conductance of the memristor)
Regarding Claim 4, Al Misba combined with Nugent teaches all the limitations of claim 1 as cited above and Nugent further teaches:
wherein […the control unit…] is configured to set the expected value based on an application voltage of the reference writing signal (Nugent, Par. [0066], “The application of a voltage difference will increase the probability that a particle will bridge the gap between pre and post synaptic electrodes. As a first approximation, we may treat the instantaneous probability that a connection will form, or a conduction channel will open, as proportional to the square of the voltage difference between pre and post synaptic electrodes. The accumulation of probability is proportional to the integral of pre and post synaptic voltages over one evaluate/feedback cycle”, & Par. [0073], “The accumulated probability over both the evaluate and feedback phase is generally responsible for the connection update”, & Par. [0101], “By varying the time periods of both the evaluate and feedback phases, as well as changing the supply voltages, one can ‘dial in’ the correct plastic probability update”, thus wherein […the control unit…] is configured to set the expected value based on an application voltage of the reference writing signal is disclosed, because Nugent teaches that the applied voltage difference determines the probability that a conducting channel will open and that the accumulated probability determines the connection update. Nugent further teaches changing the supply voltage to obtain the appropriate probability update. The accumulated probability based connection update corresponds to the expected value, and the applied voltage difference and supply voltage correspond to the application voltage of the reference writing signal)
Regarding Claim 5, Al Misba combined with Nugent teaches all the limitations of claim 1 as cited above and Nugent further teaches:
wherein […the control unit…] includes a temperature sensor (Nugent, Par. [0088], “The control will allow the same chip to process many different types of data sets, and for the feedback dynamics to be modified on the fly to account for variations in parameters such as temperature, processing speed, and input data statistics”, & Par. [0101], “This can in turn be used as a mechanism for temperature compensation or to simply gain more control over the circuit parameters”, thus wherein […the control unit…] includes a temperature sensor is disclosed, because Nugent teaches electronic control that modifies the feedback dynamics to account for temperature variations and performs temperature compensation)
and wherein […the control unit…] is configured to set the expected value based on a temperature measured by the temperature sensor (Nugent, Par. [0044], “The probability that a channel will go from open to closed at any given time increment is given by a function, E(T), which can be attributed to random thermal motion or spontaneous transitions and is primarily a function of temperature”, & Par. [0045], “the update to the connection can be given as the difference between the plastic update, P, and the thermal breakdown, B”, & Par. [0088], “the feedback dynamics [can] be modified on the fly to account for variations in parameters such as temperature”, & Par. [0101], “This can in turn be used as a mechanism for temperature compensation”, thus wherein […the control unit…] is configured to set the expected value based on a temperature measured by the temperature sensor is disclosed, because Nugent teaches electronic control that modifies the probability based connection update according to temperature variations to provide temperature compensation. The connection update P corresponds to the expected value, and the temperature obtained by the temperature sensor corresponds to the temperature used by the control to modify the feedback dynamics and set the connection update)
Regarding Claim 6, Al Misba combined with Nugent teaches all the limitations of claim 1 as cited above and Nugent further teaches:
a memristor array connected to […the control unit…] (Nugent, Par. [0022], “The notion of a connection network can be applied to a nanoscale architecture of the cross bar array. Rather than a Knowm™ synapse forming a connection at the intersection of the cross bar, the connection is formed by the mechanical contact of the electrodes themselves, which are implemented as nanowires”, & Par. [0033], “a memristor apparatus can include a plurality of meta-stable switching elements, wherein the plurality of meta-stable switching elements forms a device with an electrical resistance”, & Par. [0054], “system 2200 generally includes a plurality of electrodes 2222, 2224, 2226, 2228, and 2230 arranged in a cross bar architecture”, & Par. [0152], “Neural modules, built from CMOS (or equivalent transistor-based technology), can be utilized to provide feedback to pre- and post-synaptic electrodes”, thus a memristor array connected to […the control unit…] is disclosed, because Nugent teaches a nanoscale crossbar array having metastable switching connections at the intersections of the crossbar and teaches that a plurality of metastable switching elements forms a memristor apparatus having electrical resistance. Nugent further teaches CMOS neural modules that provide feedback to the electrodes of the crossbar. The metastable switching connections arranged in the crossbar correspond to the memristor array, the CMOS neural modules correspond to the control unit, and the feedback coupling between the neural modules and the electrodes corresponds to the memristor array being connected to the control unit),
wherein the memristor array includes a plurality of memristors (Nugent, Par. [0033], “a synapse apparatus comprising a differential pair of memristor apparatuses including the memristor apparatus”, thus wherein the memristor array includes a plurality of memristors is disclosed, because Nugent teaches a synapse apparatus containing a differential pair of memristor apparatuses. The differential pair includes two memristor apparatuses and therefore corresponds to the plurality of memristors included in the memristor array),
and wherein at least one of the plurality of memristors is the memristor (Nugent, Par. [0033], “a synapse apparatus comprising a differential pair of memristor apparatuses including the memristor apparatus”, thus and wherein at least one of the plurality of memristors is the memristor is disclosed, because Nugent teaches that the differential pair of memristor apparatuses includes the previously identified memristor apparatus. The memristor apparatus included in the differential pair corresponds to at least one of the plurality of memristors being the memristor)
Regarding Claim 7, Al Misba combined with Nugent teaches all the limitations of claim 1 as cited above and Nugent further teaches:
a memristor array connected to […the control unit…] (Nugent, Par. [0022], “The notion of a connection network can be applied to a nanoscale architecture of the cross bar array. Rather than a Knowm™ synapse forming a connection at the intersection of the cross bar, the connection is formed by the mechanical contact of the electrodes themselves, which are implemented as nanowires”, & Par. [0033], “a memristor apparatus can include a plurality of meta-stable switching elements, wherein the plurality of meta-stable switching elements forms a device with an electrical resistance”, & Par. [0054], “system 2200 generally includes a plurality of electrodes 2222, 2224, 2226, 2228, and 2230 arranged in a cross bar architecture”, & Par. [0152], “Neural modules, built from CMOS (or equivalent transistor-based technology), can be utilized to provide feedback to pre- and post-synaptic electrodes”, thus a memristor array connected to […the control unit…] is disclosed, because Nugent teaches a nanoscale crossbar array having metastable switching connections at the intersections of the crossbar and teaches that a plurality of metastable switching elements forms a memristor apparatus having electrical resistance. Nugent further teaches CMOS neural modules that provide feedback to the electrodes of the crossbar. The metastable switching connections arranged in the crossbar correspond to the memristor array, the CMOS neural modules correspond to the control unit, and the feedback coupling between the neural modules and the electrodes corresponds to the memristor array being connected to the control unit),
wherein the memristor array includes a plurality of memristors (Nugent, Par. [0033], “a synapse apparatus comprising a differential pair of memristor apparatuses including the memristor apparatus”, thus wherein the memristor array includes a plurality of memristors is disclosed, because Nugent teaches a synapse apparatus containing a differential pair of memristor apparatuses. The differential pair includes two memristor apparatuses and therefore corresponds to the plurality of memristors included in the memristor array),
and wherein […the control unit…] is configured to set the expected value based on a position of the memristor in the memristor array (Nugent, Par. [0079], “During the evaluate phase, the post-Synaptic electrode with the higher voltage is considered the “winner” and feedback circuitry (i.e., to be discussed herein) saturates the voltages. We may view the meta-stable switch connecting the input to the PSE 1 322 as C11 and the connection between the input and PSE 2 323 as C12”, & Par. [0084], “For illustrative purposes, consider the case of a synapse in state 1 under inputs from both state 1 and state 2. Note that we must consider the updates to both C11 and C12, as it is only their relative strengths that determine the sign of the connection. The update to the synapse can be given as indicated by equation (9)”, & Par. [0085], “the variable A.sub.C11 represents the accumulation of connection formation probability on C11 and A.sub.E is the (negative) accumulation due to random thermal motion or spontaneous state transitions”, thus wherein […the control unit…] is configured to set the expected value based on a position of the memristor in the memristor array is disclosed, because Nugent teaches feedback circuitry that separately identifies the connections as C11 and C12 according to their respective locations and determines an update for each identified connection. Nugent further teaches that the update for C11 uses the accumulated connection formation probability associated specifically with C11. The accumulated connection formation probability corresponds to the expected value, and the C11 or C12 designation corresponds to the position of the memristor in the memristor array)
Regarding Claim 8, Al Misba combined with Nugent teaches all the limitations of claim 1 as cited above and Nugent further teaches:
a semiconductor wafer (Nugent, Par. [0152], “Neural modules, built from CMOS (or equivalent transistor-based technology), can be utilized to provide feedback to pre- and post-synaptic electrodes. This feedback creates the electric force that mirrors a plasticity rule capable of the above mentioned feats. The neural modules generally contain less than 40 transistors. A group of these modules can be used to isolate statistical regularities in a data stream. With today's technology, hundreds of thousands of these module groups can be built on a single integrated circuit, along with billions of self-assembling meta-stable connections”, & Par. [0158], “The design is composed of a CMOS core of about 40 transistors, as well as a meta stable switch synapse matrix formed above the CMOS core”, thus a semiconductor wafer is disclosed, because Nugent teaches a hybrid device containing a CMOS transistor core and a memristor synapse matrix fabricated above the CMOS core as part of a single integrated circuit)
and a memristor array connected to […the control unit…] and formed on the semiconductor wafer (Nugent, Par. [0144], “Meta-stable switches can be placed at the intersections of, for example, the B′ and A electrodes, which are patterned on the surface of the chip. In this example, data can be streamed into the demultiplexer and applied as input to one or more electrodes”, & Par. [0152], “Neural modules, built from CMOS (or equivalent transistor-based technology), can be utilized to provide feedback to pre- and post-synaptic electrodes. This feedback creates the electric force that mirrors a plasticity rule capable of the above mentioned feats”, & Par. [0158], “The design is composed of a CMOS core of about 40 transistors, as well as a meta-stable switch synapse matrix formed above the CMOS core. The design is relatively space-efficient, considering the power it has to implement any of the 16 total 2-input, 1-out logic functions”, thus and a memristor array connected to […the control unit…] and formed on the semiconductor wafer is disclosed, because Nugent teaches a metastable switch synapse matrix formed above a CMOS core, with the metastable switches positioned at electrode intersections patterned on the surface of the chip. Nugent further teaches CMOS neural modules that provide feedback to the synaptic electrodes. The metastable switch synapse matrix corresponds to the memristor array, the CMOS neural modules correspond to the control unit, and the semiconductor chip supporting the CMOS core and synapse matrix corresponds to the semiconductor wafer),
wherein the memristor array includes a plurality of the memristors (Nugent, Par. [0033], “a synapse apparatus comprising a differential pair of memristor apparatuses including the memristor apparatus”, thus wherein the memristor array includes a plurality of memristors is disclosed, because Nugent teaches a synapse apparatus containing a differential pair of memristor apparatuses. The differential pair includes two memristor apparatuses and therefore corresponds to the plurality of memristors included in the memristor array),
and wherein […the control unit…] is configured to set the expected value based on a position of the memristor on the semiconductor wafer (Nugent, Par. [0079], “During the evaluate phase, the post-Synaptic electrode with the higher voltage is considered the “winner” and feedback circuitry (i.e., to be discussed herein) saturates the voltages. We may view the meta-stable switch connecting the input to the PSE 1 322 as C11 and the connection between the input and PSE 2 323 as C12”, & Par. [0084], “For illustrative purposes, consider the case of a synapse in state 1 under inputs from both state 1 and state 2. Note that we must consider the updates to both C11 and C12, as it is only their relative strengths that determine the sign of the connection”, & Par. [0085], “As indicated by equation (9), the variable A.sub.C11 represents the accumulation of connection formation probability on C11 and A.sub.E is the (negative) accumulation due to random thermal motion or spontaneous state transitions”, & Par. [0144], “Meta-stable switches can be placed at the intersections of, for example, the B′ and A electrodes, which are patterned on the surface of the chip. In this example, data can be streamed into the demultiplexer and applied as input to one or more electrodes”, thus and wherein […the control unit…] is configured to set the expected value based on a position of the memristor on the semiconductor wafer is disclosed, because Nugent teaches feedback circuitry that separately identifies the metastable switch connections as C11 and C12 and determines an accumulated connection formation probability specifically for C11. Nugent further teaches that the metastable switches are positioned at respective electrode intersections patterned on the surface of the chip. The feedback circuitry corresponds to the control unit, the accumulated connection formation probability corresponds to the expected value, and the C11 or C12 electrode intersection corresponds to the position of the memristor on the semiconductor wafer)
Regarding Claim 9, Al Misba combined with Nugent teaches all the limitations of claim 1 as cited above and Nugent further teaches:
a memristor array connected to […the control unit…] (Nugent, Par. [0022], “The notion of a connection network can be applied to a nanoscale architecture of the cross bar array. Rather than a Knowm™ synapse forming a connection at the intersection of the cross bar, the connection is formed by the mechanical contact of the electrodes themselves, which are implemented as nanowires”, & Par. [0033], “a memristor apparatus can include a plurality of meta-stable switching elements, wherein the plurality of meta-stable switching elements forms a device with an electrical resistance”, & Par. [0054], “system 2200 generally includes a plurality of electrodes 2222, 2224, 2226, 2228, and 2230 arranged in a cross bar architecture”, & Par. [0152], “Neural modules, built from CMOS (or equivalent transistor-based technology), can be utilized to provide feedback to pre- and post-synaptic electrodes”, thus a memristor array connected to […the control unit…] is disclosed, because Nugent teaches a nanoscale crossbar array having metastable switching connections at the intersections of the crossbar and teaches that a plurality of metastable switching elements forms a memristor apparatus having electrical resistance. Nugent further teaches CMOS neural modules that provide feedback to the electrodes of the crossbar. The metastable switching connections arranged in the crossbar correspond to the memristor array, the CMOS neural modules correspond to the control unit, and the feedback coupling between the neural modules and the electrodes corresponds to the memristor array being connected to the control unit),
wherein the memristor array includes a plurality of memristors (Nugent, Par. [0033], “a synapse apparatus comprising a differential pair of memristor apparatuses including the memristor apparatus”, thus wherein the memristor array includes a plurality of memristors is disclosed, because Nugent teaches a synapse apparatus containing a differential pair of memristor apparatuses. The differential pair includes two memristor apparatuses and therefore corresponds to the plurality of memristors included in the memristor array),
and wherein […the control unit…] is configured to set the expected value based on behavior of the conductance change when the reference writing signal is applied to at least one memristor in the memristor array (Nugent, Par. [0020], “At least one electric pulse can be generated from one or more of the neural circuit modules to one or more of the pre-synaptic electrodes of a succeeding neuron and one or more post synaptic electrodes of one or more of the neurons of the synapse junction, thereby configuring the state of at least one meta-stable switch of a plurality of meta-stable switches disposed within the dielectric solution and at least one synapse thereof”, & Par. [0073], “The accumulated probability over both the evaluate and feedback phase is generally responsible for the connection update. By separating the process into two phases, we acquire the two behaviors necessary for a successful integration of equation (2). The decreasing update as a function of activity is provided through the “evaluate” phase while the correct update sign is accomplished with the feedback phase”, & Par. [0075], “recall that the update to the meta-stable switch, as given by a probability that a closed conducting channel will open, is given by the accumulation of probability, which is related to the integral of the voltage difference across the pre- and post-synaptic electrode. If we only consider the evaluate phase, then it is apparent that as the meta-stable connection 202 grows stronger, and the activity increases, the accumulated probability becomes smaller and approaches zero”, & Par. [0076], “If, for instance, a series of input voltage pulses is applied at the pre-synaptic input 209, then the meta-stable switch 202 would equilibrate to a value proportional to total pre-synaptic activation. This could prove a valuable electronic filter”, thus and wherein […the control unit…] is configured to set the expected value based on behavior of the conductance change when the reference writing signal is applied to at least one memristor in the memristor array is disclosed, because Nugent teaches applying electric pulses to at least one metastable switch among a plurality of metastable switches and determining the resulting connection update from the accumulated probability that conducting channels will open. Nugent further teaches that the accumulated probability varies according to the strength and activity of the connection and that repeated voltage pulses cause the switch to approach an equilibrium resistance. The accumulated probability based connection update corresponds to the expected value, the electric pulse corresponds to the reference writing signal, the metastable switch corresponds to at least one memristor in the memristor array, and the variation in the probability update and equilibrium resistance in response to the applied pulses corresponds to the behavior of the conductance change)
Regarding Claim 10, Al Misba combined with Nugent teaches all the limitations of claim 9 as cited above and Nugent further teaches:
wherein the memristor in which the behavior of […the conductance…] change when the reference writing signal is applied thereto is evaluated is a reference element for evaluation (Nugent, Par. [0073], “To demonstrate such a functionality, consider a simple Knowm-Capacitor circuit 200, as illustrated by FIG. 2”, & Par. [0074], “In general, the Knowm-Capacitor circuit 200 depicted in FIG. 2 includes a Knowm™ connection 202 disposed between a pre-synaptic input 209 and post-synaptic output 202 thereof. Note that the Knowm-Capacitor circuit 200 is connected to a capacitor 204 at the post-synaptic output 202. Capacitor 204 is in turn connected to a ground 208. The Knowm™ connection 202 can be thought of as constituting an electro-kinetic induced particle chain. The configuration of circuit 200 is presented herein for illustrative and exemplary purposes only”, & Par. [0075], “the update to the meta-stable switch, as given by a probability that a closed conducting channel will open, is given by the accumulation of probability, which is related to the integral of the voltage difference across the pre- and post-synaptic electrode”, thus wherein the memristor in which the behavior of […the conductance…] change when the reference writing signal is applied thereto is evaluated is a reference element for evaluation is disclosed, because Nugent uses the Knowm connection as an illustrative and exemplary element for demonstrating and evaluating how the metastable switch responds to an applied voltage. The Knowm connection corresponds to the memristor, its probability based resistance and conductance response corresponds to the evaluated behavior of the conductance change, and its use as the exemplary element for evaluating that response corresponds to the reference element for evaluation)
Regarding Claim 11, Al Misba combined with Nugent teaches all the limitations of claim 1 as cited above and Al Misba further teaches:
wherein […the memristor…] is a magnetic domain wall moving element (Al Misba, Page 4 -Section II, “We model our synapse on a magnetic DW based nanodevice, which is non-volatile in nature. Once the memory state (here the synaptic weight) is written, the information is retained for a long time. For the nano-synapse device, we simulated a thin ferromagnetic racetrack having a dimension of 600 nm × 60 nm × 1 nm with a DW initialized and stabilized in a notch at one end”, & Page 4 - Section II, “With this configuration, a combination of fixed amplitude and fixed time current pulse ‘‘or clocking signal’’ injected in the heavy metal layer and a varying amplitude ‘‘control’’ voltage pulse applied across the piezoelectric translates the domain wall to different distances along the racetrack”, thus wherein […the memristor…] is a magnetic domain wall moving element is disclosed, because Al Misba teaches a nonvolatile magnetic domain wall synaptic device having a domain wall initialized in a ferromagnetic racetrack and moved to different positions along the racetrack by applied current and voltage pulses. The magnetic domain wall synaptic device corresponds to the magnetic domain wall moving element)
wherein the magnetic domain wall moving element includes a first ferromagnetic layer including a magnetic domain wall, a second ferromagnetic layer, and a nonmagnetic layer interposed between the first ferromagnetic layer and the second ferromagnetic layer (Al Misba, Page 4 - Section II, “For the nano-synapse device, we simulated a thin ferromagnetic racetrack having a dimension of 600 nm × 60 nm × 1 nm with a DW initialized and stabilized in a notch at one end. In addition, we assume several engineered notches at regular intervals along the racetrack”, & Page 4 - Section II, “An insulator (MgO layer) and a reference ferromagnetic layer (one could also add a synthetic antiferromagnet (SAF) layer to cancel dipole coupling from this fixed layer) are stacked on top of the racetrack, these two layers combined with the racetrack ferromagnetic layer (free layer) forms a magnetic tunnel junction (MTJ) (see Fig. 1b), which facilitates the readout of the device”, thus wherein the magnetic domain wall moving element includes a first ferromagnetic layer including a magnetic domain wall, a second ferromagnetic layer, and a nonmagnetic layer interposed between the first ferromagnetic layer and the second ferromagnetic layer is disclosed, because Al Misba teaches a ferromagnetic racetrack containing a magnetic domain wall, an MgO insulating layer stacked on the ferromagnetic racetrack, and a reference ferromagnetic layer stacked on the MgO insulating layer. The ferromagnetic racetrack corresponds to the first ferromagnetic layer, the reference ferromagnetic layer corresponds to the second ferromagnetic layer, and the MgO insulating layer positioned between the ferromagnetic layers corresponds to the nonmagnetic layer)
Regarding Claim 12, Al Misba teaches:
a preliminary evaluation step of calculating […] conductance […] having electrical characteristics in which conductance change occurs stochastically when a writing signal is applied […] (Al Misba, Page 4 - Section II, “The distribution of equilibrium DW positions for five different programming voltages, represented by different perpendicular magnetic anisotropy (PMA) coefficient, Ku, in addition to fixed amplitude and fixed time spin orbit torque (SOT) generating current pulse (35 × 1010Am2 applied for 1 ns) in the presence of room temperature thermal noise are shown in Fig. 1c”, & Page 4 - Section II, “Thus, in the presence of room temperature thermal noise and structural irregularities (edge roughness) DW motion becomes significantly stochastic. As a result, an average variance of ∼ 90 nm can be seen for different DW mean positions in our modelled racetrack”, & Page 5 – Section II, “Equilibrium DW positions shown in Fig. 1c can be linearly mapped to a conductance value”, thus a preliminary evaluation step of calculating […] conductance […] having electrical characteristics in which conductance change occurs stochastically when a writing signal is applied […] is disclosed, because Al Misba teaches preliminarily simulating the equilibrium domain wall positions resulting from different programming signals and calculating corresponding conductance values from the equilibrium positions. Al Misba further teaches that thermal noise and structural irregularities cause the domain wall motion, and therefore the resulting conductance change, to occur stochastically)
a weight updating step of calculating an update value of a weight through learning using a neural network (Al Misba, Page 6 - Section III, “For the training of the DNN, we update the weights by calculating the gradient of a cost function with respect to the weights”, & Page 6 - Section III, “Finally, the derivative of the cost function with respect to the weights is calculated, which determines the weight update signal, ΔWij”, & Page 6 - Section III, “After each forward and backward pass in the analog crossbar array, these weights are updated according to Eq. 5”, thus a weight updating step of calculating an update value of a weight through learning using a neural network is disclosed, because Al Misba teaches training a deep neural network through forward propagation and backpropagation, calculating the derivative of a cost function with respect to each weight, and using the resulting weight update signal to update the neural network weights. The weight update signal ΔWij corresponds to the update value of the weight)
a conductance converting step of calculating a necessary value of the conductance change amount of […the memristor…] from the update value of the weight (Al Misba, Page 5 -Section III, “The conductance of the devices can be scaled linearly to represent the weights Wij of the DNN”, & Page 6 - Section III, “However, we use these high precision weights to update the DW device weights (conductances). As we apply stochastic gradient decent for optimization, these high precision weights are updated at each forward pass with an input image” and “After quantization, a programming pulse is generated to update the DW device weights to the quantized value”, thus a conductance converting step of calculating a necessary value of the conductance change amount of […the memristor…] from the update value of the weight is disclosed, because Al Misba teaches converting an updated neural network weight into a corresponding target quantized conductance and determining whether the current device conductance must be updated to that target value. The updated high precision weight corresponds to the update value of the weight, and the difference between the current conductance and the conductance corresponding to the target quantized weight corresponds to the necessary value of the conductance change amount)
a signal determining step of determining the writing signal which is actually applied […] based on the necessary value […] (Al Misba, Page 6 - Section III, “After quantization, a programming pulse is generated to update the DW device weights to the quantized value, a target that is similar to the quantized neural network learning algorithm”, & Page 6 - Section III, “Five different programming voltages can be applied to the device, which results in Ku = 8, 7.75, 7.5, 7.25 and 7.0 (× 105) J m3 to achieve five different quantized weights of −1, −0.5, 0, 0.5 and −1 respectively as seen from Fig. 1d (DW device weights, Wij = < mz > according to Eq. 4)”, & Page 7 – Section III, “if it falls outside the noise tolerance margin, a programming pulse is sent to the device to write the corresponding quantized weight”, thus a signal determining step of determining the writing signal which is actually applied […] based on the necessary value […] is disclosed, because Al Misba teaches determining whether the current device conductance must be changed to the target quantized conductance and selecting the programming voltage and current pulse corresponding to that target value. The required change from the current conductance to the target conductance corresponds to the necessary value, and the selected programming voltage and current pulse correspond to the writing signal actually applied to the device)
Al Misba does not explicitly teach […] an expected value by which […] of a memristor changes when a reference writing signal is applied to the memristor, the memristor […] to the memristor, and […] to the memristor […] and the expected value
However, Nugent teaches:
[…] an expected value by which […] of a memristor changes when a reference writing signal is applied to the memristor, the memristor […] to the memristor (Nugent, Par. [0045], “Given a total of No open channels, out of N total channels, the update to the connection can be given as the difference between the plastic update, P, and the thermal breakdown, B”, & Par. [0066], “The application of a voltage difference will increase the probability that a particle will bridge the gap between pre and post synaptic electrodes”, & Par. [0073], “The accumulated probability over both the evaluate and feedback phase is generally responsible for the connection update”, thus […] an expected value by which […] of a memristor changes when a reference writing signal is applied to the memristor, the memristor […] is disclosed, because Nugent teaches calculating a connection update based on the accumulated probability that conducting channels will change state in response to an applied voltage difference. The probability based connection update corresponds to the expected value by which the memristor conductance changes, and the applied voltage difference corresponds to the reference writing signal applied to the memristor)
[…] to the memristor […] and the expected value (Nugent, Par. [0101], “By varying the time periods of both the evaluate and feedback phases, as well a changing the supply voltages, one can ‘dial in’ the correct plastic probability update”, & Par. [0106], “By combining the accumulated probability of connection formation over both the evaluate and feedback stage, we have succeeded in designing a circuit capable of providing a feedback that mirrors the above mentioned plasticity rule”, thus […] to the memristor […] and the expected value is disclosed, because Nugent teaches selecting the voltage and application duration supplied to the memristor according to the accumulated probability based connection update. The selected voltage and application duration correspond to the writing signal applied to the memristor, and the accumulated probability based connection update corresponds to the expected value)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine Al Misba with Nugent by incorporating Nugent’s probability based memristor update model into Al Misba’s stochastic domain wall synapse programming system. Al Misba teaches calculating a neural network weight update, converting the updated weight into a target device conductance, and applying a programming pulse to obtain the target conductance, while also recognizing that thermal noise and structural irregularities cause the resulting conductance change to vary stochastically. Nugent teaches determining a connection update based on the probability that conducting channels will transition between conductive and nonconductive states in response to an applied voltage. Therefore, a POSITA would have been motivated to use Nugent’s probability based expected conductance response when determining Al Misba’s programming pulse so that the pulse accounts for both the required conductance change associated with the neural network weight update and the expected response of the device to the applied signal, thereby reducing the difference between the intended neural network weight and the actual programmed conductance and improving the reliability and accuracy of the neuromorphic learning process (Nugent, Par. [0055], “The application of a voltage gradient across pre and post synaptic electrode leads to a non zero probability that a nanowire 2231 will transition from the OFF state to the ON state. In addition, the application of a voltage to the junction in the ON state will lead to a non zero probability that nanowire 2231 will transition from the ON state to the OFF state. The application of pre and post synaptic voltage pulses, as outlined in this disclosure, leads to a reliable synaptic junction suitable for object recognition and universal logic function”)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. US 20200327406 is pertinent because it teaches training an artificial neural network for implementation using memristive devices in which trained weights are stored as programmed conductance states. The reference further teaches repeatedly updating neural network weights during an iterative training process, measuring conductance errors of programmed memristive devices, deriving probability distributions representing the stochastic conductance errors, and applying noise based on the probability distributions during training. The reference also teaches mapping trained or quantized weight values to corresponding memristor conductance states and programming the devices to store the respective weights. Because applicant’s disclosure similarly concerns neural network weight updates, memristor conductance states, stochastic conductance variations, and probabilistic characterization of memristor conductance behavior, the reference is relevant to the invention but is not relied upon in the rejection.
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/M.T.A./Examiner, Art Unit 2123
/ALEXEY SHMATOV/Supervisory Patent Examiner, Art Unit 2123
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