Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/20/2026 has been entered.
Response to Arguments
Applicant's arguments filed 1/20/2026 have been fully considered but they are not persuasive. On pages 7-10, Applicant alleges that Jiang does not teach the limitation of claim 1 “generate a set of decoded bits based on a decoding of each bit in the set of bits according to a bit priority, wherein the bit priority is based on a first error metric of each bit in the set of bits for a first number of ordered permutations of each of bits associated with the at least two subsets of bits.” While Examiner agrees that the previous action does not explicitly explain how Jiang teaches the newly amended limitation, upon further consideration Jiang does indeed teach “generate a set of decoded bits based on a decoding of each bit in the set of bits according to a bit priority, wherein the bit priority is based on a first error metric of each bit in the set of bits for a first number of ordered permutations of each of bits associated with the at least two subsets of bits.”
The first portion of the above limitation “generate a set of decoded bits based on a decoding of each bit in the set of bits according to a bit priority” is clearly taught in the previously referenced portion of Jiang: (abstract: utilize the bit index reliability sequence in a lookup table for… decoding.) The bit index reliability sequence is considered to be equivalent to the bit priority of the instant application because it is a ordering of bits, that prioritizes bits that are found to be more reliable.
The second portion of the above limitation “wherein the bit priority is based on a first error metric of each bit in the set of bits for a first number of ordered permutations of each of bits associated with the at least two subsets of bits” is also taught by Jiang. (see para. 176: The transmitter sequence identifier 210 may determine an input search sequence that includes all… of N bit indices. The transmitter sequence identifier 210 may apply a UPO (universal partial order) to an input search sequence to obtain a partial order. The UPO may define a partial order on bit reliability based on one or more properties.) Here, Jiang clearly discloses determining a partial order of each of the bits based on their reliabilities. The reliabilities of the bits is considered to be an error metric of each of the bits. (And see para. 177 and fig. 6: Depicted in Hasse diagram 600 are a set of connected nodes 605, where each node 605 corresponds to a particular bit index. The values of the bit indices of the nodes 605 may correspond to an input search sequence. The Hasse diagram 600 may represent an ordering of the bit indices into a bit reliability sequence based on applying a UPO to an input search sequence. Nodes 605 on the left (that is where (0,0,0,0) is on the far left and (1,1,1,1) is on the far right) of the Hasse diagram 600 may correspond to bit indices that are less reliable than bit indices on the right. The bit index reliability sequence may be determined by selecting the most reliable bit-index under the UPO.) Fig. 6 represents the resulting partial ordering of bits after applying the UPO. The partial ordering is considered equivalent to “a first number of ordered permutations of each of bits associated with the at least two subsets of bits.” This is because the partial ordering depicted in fig. 6 contains many ordered permutations of all the bits. While certain bits are definitively ordered (for example, (0,0,0,0) and (1,1,1,1)), they are still represented in “a first number of ordered permutations of each of bits associated with the at least two subsets of bits.” For example, the partial ordering depicted in fig. 6 contains ordered permutations: [(0000),(0001),(0010),(0100),(0011),(0101),(1000),(0110),(1001),(1010),(0111),(1100),(1011),(1101),(1110),(1111)], or:
[(0000),(0001),(0010),(0011),(0100),(1000),(0101),(1001),(0110),(0111),(1010),(1011),(1100),(1101),(1110),(1111)], and so on.
Also see Jiang (para. 163: The transmitter sequence identifier 210 identifier a bit index reliability sequence determined based on a UPO. Determining the bit index reliability sequence may involve an initial input search sequence, which may be known as an input sequence, containing all… of the bit channel indices. The transmitter sequence identifier 210 may calculate the partial order under UPO of the input search sequence and pick the most reliable bit-index under UPO. If the picked bit-index is not the same order as another bit-index in the input search sequence it may be added to the bit index reliability sequence. Elsewise, analytical methods (e.g., index weighting by the Reed Muller rule), simulations, or both… may be used to select the most reliable bit-index of that order, and that bit may be added to the bit-index reliability sequence… the method may be repeated until all of the bit-indices are selected.)
It is clear that Jiang teaches: “wherein the bit priority is based on a first error metric of each bit in the set of bits for a first number of ordered permutations of each of bits associated with the at least two subsets of bits.” As shown above, the bit-index reliability sequence is equivalent to the bit priority. The bit index reliability sequence is determined based on the reliability (an error metric) of each bit in the set of bits for a first number of ordered permutations (contained within the partial ordering derived via the UPO). The partial ordering contains all the bits, therefore including each of the bits associated with the at least two subsets of bits.
Likewise, Applicant’s arguments regarding corresponding independent claims 19 and 20, and dependent claims 2-18 are similarly not found to be convincing.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 19, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, lines 10-12 reads “wherein the bit priority is based on a first error metric of each bit in the set of bits for a first number of ordered permutations of each of bits associated with the at least two subsets of bits.” It is unclear whether “each of bits associated with the at least two subsets of bits” is equivalent to “each bit in the set of bits.” Examiner notes that claim 1 previously links these two elements together in line 6: “partition a set of bits into at least two subsets of bits.” Examiner assumes that all the bits of the original set are intended to be further contained within the at least two subsets, and if so, the claim should be updated for clarity to read: “wherein the bit priority is based on a first error metric of each bit in the set of bits for a first number of ordered permutations of each bit in the set of bits.” If all the bits of the original set are not further contained within the at least two subsets, then it is unclear how the bit priority can be based on a first error metric of each bit in the set of bits for a first number of ordered permutations for only some of the bits in the original set of bits.
It is further unclear what is exactly meant by “the bit priority is based on a first error metric of each bit in the set of bits for a first number of ordered permutations of each of bits associated with the at least two subsets of bits.” The relationship between the first error metric and the ordered permutations is unclear. Is the error metric calculated for each bit in each permutation? Does each bit somehow have its own “first number of ordered permutations?” Upon consultation of the specification and drawings, the examiner was unable to ascertain what exactly is meant by this limitation. Throughout this action, the Examiner has interpreted this limitation to mean: the bit priority is based on the following 1) a first error metric of each bit in the set of bits and 2) a first number of ordered permutations of each of the bits associated with the at least two subsets of bits.
Claims 19 and 20 contain similar issues and are rejected accordingly.
Claim Objections
Claims 5 and 6 are objected to because of the following informalities:
Claim 5, line 3 reads “the first number of ordered permutations of bits associated with the at least two subsets of bits.” Based on the amendment to claim 1, this limitation lacks antecedent basis. Appropriate correction is required.
Claim 6, line 4-5 reads “a match of the bit to be decoded between one of the first number of ordered permutations of bits and the at least two subsets of bits, and the bit priority.” Examiner believes this claim is intended to read “a match of the bit to be decoded between one of the first number of ordered permutations of bits associated with the at least two subsets of bits, and the bit priority.” But is ultimately unsure. Regardless, the limitation lacks antecedent basis based on the amendment to claim 1. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
(g)(1) during the course of an interference conducted under section 135 or section 291, another inventor involved therein establishes, to the extent permitted in section 104, that before such person’s invention thereof the invention was made by such other inventor and not abandoned, suppressed, or concealed, or (2) before such person’s invention thereof, the invention was made in this country by another inventor who had not abandoned, suppressed, or concealed it. In determining priority of invention under this subsection, there shall be considered not only the respective dates of conception and reduction to practice of the invention, but also the reasonable diligence of one who was first to conceive and last to reduce to practice, from a time prior to conception by the other.
A rejection on this statutory basis (35 U.S.C. 102(g) as in force on March 15, 2013) is appropriate in an application or patent that is examined under the first to file provisions of the AIA if it also contains or contained at any time (1) a claim to an invention having an effective filing date as defined in 35 U.S.C. 100(i) that is before March 16, 2013 or (2) a specific reference under 35 U.S.C. 120, 121, or 365(c) to any patent or application that contains or contained at any time such a claim.
Claims 1-2 and 4-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jiang (US Publication No. 20190044540).
Regarding claim 1, Jiang teaches:
An apparatus for wireless communication at a first network device, comprising: (Abstract: A wireless device… may encode a codeword using a polar code for transmission over a wireless channel.)
at least one memory; (fig. 7: memory 705)
and at least one processor coupled to the at least one memory and, based at least in part on information stored in the at least one memory, the at least one processor, individually or in any combination, is configured to: (fig. 7, encoder/decoder 710)
partition a set of bits into at least two subsets of bits based on a bit weighting metric, (fig. 20, operation 2010: recursive partitioning of a set of bit-channels of the polar code for at least a subset of polarization stages of the polar code, and, for each partition of the at least the subset of the polarization stages of the polar code, assigning portions of a number of the information bits of each partition to bit-channel sub-partitions, where at least one quantization rule is applied for determining whether to assign a first number of the information bits of a first bit-channel sub-partition of the bit-channel sub-partitions to a fixed value.)
wherein the set of bits is associated with a polar encoding and a set of information bits and a set of frozen bits; (para. 118: Channels of a polar code having higher reliabilities are used to encode information bits and the remaining channels are used to encode frozen bits.)
generate a set of decoded bits based on a decoding of each bit in the set of bits according to a bit priority, wherein the bit priority is based on a first error metric of each bit in the set of bits for a first number of ordered permutations of each of bits associated with the at least two subsets of bits; (abstract: utilize the bit index reliability sequence in a lookup table for… decoding. And para. 163: The transmitter sequence identifier 210 identifies a bit index reliability sequence based on a UPO. Determining the bit index reliability sequence may involve an initial input search sequence, which may also be known as an input sequence, containing all… of the bit channel indices [each bit in the set of bits]. The transmitter sequence identifier 210 may calculate a partial order [essentially a first number of ordered permutations of bits, for further clarification please see response to arguments] under UPO of the input search sequence and pick the most reliable [an error metric of each bit] bit-index under UPO… that bit may be added to the bit index reliability sequence. The selected bit may be removed from the input search sequence and the method above may be repeated until all… of the input bit indices are selected. And see para. 50: bit channels of a polar code may be recursively partitioned… assigning information bits to a partition may be adjusted to be compliant with a UPO.) The partial ordering contains all the bits, therefore including each of the bits associated with the at least two subsets of bits.
and transmit, for a second network device, a set of encoded bits that are based on an encoding of the set of decoded bits. (abstract: a wireless device… may encode a codeword using a polar code for transmission over a wireless channel.)
Claims 19 and 20 correspond to claim 1, and are similarly rejected.
Regarding claim 2, Jiang teaches the apparatus of claim 1. Jiang further teaches:
wherein the set of bits includes a total number of bits, and wherein the at least two subsets of bits include a second number of subsets that is one more than a base-two logarithm value of the total number of bits. (para. 198: in some cases, reliability metrics may be determined based on a recursive partitioning of bit locations… of the polar code… for example, the bit channels corresponding to the single parity check operation may be partitioned into a first, lower reliability group, while the bit channels corresponding to a repetition operation may be partitioned into a second, higher reliability group. The polarization process may continue recursively until each partition reaches a given size.) When the given size is 1, the number of subsets is equal to the total number of bit channels (bits). For any positive number of bits N, N will always be at least 1 greater than log2(N).
Regarding claim 4, Jiang teaches the apparatus of claim 1. Jiang further teaches:
wherein the first error metric is at least one of a smallest log likelihood ratio or a largest path metric. (para. 176: The UPO may define a partial order [bit priority] based on one or more properties. For example, a first property of the UPO may dictate that a bit-index i has the same or higher reliability (eg., under… maximum likelihood decoding.) Maximum likelihood decoding is based off of log likelihood ratio, and as a result, the UPO orders bits with respect to the smallest log likelihood ratio. Regarding claim 5, Jiang teaches the apparatus of claim 1. Jiang further teaches:
wherein to generate the set of decoded bits, the at least one processor is configured to: identify each of the first number of ordered permutations of bits associated with the at least two subsets of bits. (para. 6: apply a UPO to an input search sequence to obtain a partial order) A partial order is the set of possible ordered permutations with respect to the UPO. For further clarification see response to arguments.
Regarding claim 6, Jiang teaches the apparatus of claim 5. Jiang further teaches:
wherein to generate the set of decoded bits, the at least one processor is configured to: (1) identify a bit to be decoded from the set of bits based on: a match of the bit to be decoded between one of the first number of ordered permutations of bits and the at least two subsets of bits, and the bit priority; (para. 329: an order of bit indices in the bit reliability sequence is determined based on applying a UPO to an input search sequence to obtain a partial order, applying an analytical method to obtain calculated relative orders of bit indices not ordered in the partial order, and applying a simulation to refine an order of at least two bit indices selected based on the calculated relative orders, and decode the codeword based on the bit index reliability sequence.)
(2) generate a decoded bit by decoding the bit to be decoded; and (3) remove the decoded bit from the at least two subsets of bits. (para. 336: decoding the codeword includes applying a successive cancellation list decoding algorithm to a signal that includes the codeword.) Successive cancellation list decoding is well known to generate a decoded bit one at a time, and then effectively remove the decoded bit from the subsets of encoded bits.
Regarding claim 7, Jiang teaches the apparatus of claim 6. Jiang further teaches:
wherein to generate the set of decoded bits, the at least one processor is configured to repeat (1) to (3) for each bit in the set of bits (para. 336: decoding the codeword includes applying a successive cancellation list decoding algorithm to a signal that includes the codeword.) Successive cancellation list decoding is well known to repeat these steps until all bits have been decoded.
Regarding claim 8, Jiang teaches the apparatus of claim 1. Jiang further teaches:
wherein to generate the set of decoded bits based on the decoding of each bit in the set of bits according to the bit priority, the at least one processor is configured to: identify the set of information bits based on a second error metric in each bit of the set of decoded bits. (para. 9: The instructions may be operable to cause the processor to receive a codeword over a wireless channel… identify a set of bit locations of the multiple bit channels of the polar code for the multiple information bits based on a bit index reliability sequence, where the bit index reliability sequence is determined based on a binary bit weighting for the multiple bit channels that applies multiple weighting factors, and decode the received codeword according to the polar code to obtain an information bit vector at the set of bit locations.)
Regarding claim 9, Jiang teaches the apparatus of claim 8. Jiang further teaches:
wherein the second error metric is a reliability metric associated with bit locations of the set of decoded bits, and wherein a code rate for the decoding of each bit in the set of bits is based on a ratio of a number of information bits in the set of information bits to a total number of bits in the set of bits. (para. 9: The instructions may be operable to cause the processor to receive a codeword over a wireless channel… identify a set of bit locations of the multiple bit channels of the polar code for the multiple information bits based on a bit index reliability sequence, where the bit index reliability sequence is determined based on a binary bit weighting for the multiple bit channels that applies multiple weighting factors, and decode the received codeword according to the polar code to obtain an information bit vector at the set of bit locations. Also see para. 222: Rule 2 may be used to set the number of information bits Ki+ to a fixed value when the calculated number of information bits Ki exceeds a difference between the total number of bits Ni of a partition and log2(Ni). Rule 2 may be a function of a code rate of the partition.)
Regarding claim 10, Jiang teaches the apparatus of claim 9. Jiang further teaches:
wherein to identify the set of information bits based on the second error metric in each bit of the set of decoded bits, the at least one processor is configured to: calculate a second number of bits for the set of frozen bits as a difference between the total number of bits in the set of bits and the number of information bits; identify the set of frozen bits as the second number of bits that includes a lower reliability metric associated with the bit locations of the set of decoded bits than remaining bits of the set of bits; and identify the set of information bits as the remaining bits of the set of bits. (para. 118: For N channels, K information bits may be loaded into the K most reliable channels and N-K frozen bits may be loaded into the N-K least reliable channels.)
Regarding claim 11, Jiang teaches the apparatus of claim 10. Jiang further teaches:
wherein the decoding of each bit in the set of bits is associated with at least one of a binary erasure channel (BEC), an additive white Gaussian noise (AWGN) channel, or a binary symmetric channel (BSC). (para. 213: For an additive white Gaussian noise channel…)
Regarding claim 12, Jiang teaches the apparatus of claim 8. Jiang further teaches:
wherein the second error metric is at least one of a largest path metric or a cyclic redundancy check (CRC), (para. 191: The receiver sequence identifier 225 may determine a length of the codeword 320 and may select a bit index reliability sequence corresponding to the determined length. The receiver sequence identifier 225 may output the bit index reliability sequence and the representation of the codeword to decoder 230 to identify the most likely candidate path or paths for the information bits obtained from the codeword.) The most likely candidate path is considered to be a largest path metric.
and wherein the decoding of each bit in the set of bits is associated with a list decoding including a list size indicative of a number of paths in a list for the list decoding. (para. 182: in some examples, the simulation may be based on a list size applied by a successive cancellation list decoding algorithm for decoding the codeword.)
Regarding claim 13, Jiang teaches the apparatus of claim 12. Jiang further teaches:
wherein to identify the set of information bits, the at least one processor is configured to: generate, for each of the number of paths in the list and each information bit identified, a first path for a first bit value of the information bit identified and a second path for a second bit value of the information bit identified; identify, for each of the number of paths in the list and each bit, each permutation for a determination of a next bit to be decoded; and identify a set of paths based on the second error metric. (para. 191: The receiver sequence identifier 225 may determine a length of the codeword 320 and may select a bit index reliability sequence corresponding to the determined length. The receiver sequence identifier 225 may output the bit index reliability sequence and the representation of the codeword to decoder 230 to identify the most likely candidate path or paths for the information bits obtained from the codeword.)
Regarding claim 14, Jiang teaches the apparatus of claim 13. Jiang further teaches:
wherein the second error metric is the largest path metric, and wherein to identify the set of paths based on the second error metric, the at least one processor is configured to identify the set of paths that includes a lowest largest path metric value; (para. 191: The receiver sequence identifier 225 may determine a length of the codeword 320 and may select a bit index reliability sequence corresponding to the determined length. The receiver sequence identifier 225 may output the bit index reliability sequence and the representation of the codeword to decoder 230 to identify the most likely candidate path or paths for the information bits obtained from the codeword.) The most likely candidate path is considered to be a largest path metric.
or wherein the second error metric is the CRC, and wherein to identify the set of paths based on the second error metric, the at least one processor is configured to identify the set of paths that pass the CRC.
Regarding claim 15, Jiang teaches the apparatus of claim 1. Jiang further teaches:
wherein the first network device is one of a user equipment (UE) (abstract: A wireless device (e.g., a base station or user equipment (UE)).)
or a network node and the second network device is another one of the UE or the network node. (abstract: A device receiving the transmitted codeword…) This device is considered to be a network node as it is receiving a codeword from the network.
Regarding claim 16, Jiang teaches the apparatus of claim 1. Jiang further teaches:
wherein the at least one processor is further configured to: output an indication of at least one of the set of generated decoded bits or the set of encoded bits. (abstract: A wireless device… may encode a codeword for transmission over a wireless channel.) Transmitting the codeword is effectively outputting an indication of the set of encoded bits.
Regarding claim 17, Jiang teaches the apparatus of claim 16. Jiang further teaches:
wherein to output the indication of the set of generated decoded bits, the at least one processor is configured to:
transmit the indication of the set of generated decoded bits;
or store the indication of at least one of the set of generated decoded bits or the set of encoded bits. (para. 191: If the decoder is able to decode the codeword successfully, the decoder may output a bit sequence of the information vector… for use, storage, communication to another device, or the like.)
Regarding claim 18, Jiang teaches the apparatus of claim 1. Jiang further teaches:
further comprising at least one transceiver coupled to the at least one processor, wherein to transmit the set of encoded bits, the at least one processor is configured to: transmit, for the second network device and via the at least one transceiver, the set of encoded bits that are based on the encoding of the set of decoded bits. (abstract: A wireless device… may encode a codeword using a polar code for transmission… A device receiving the transmitted codeword may… determine the transmitted information bits.) The codeword, before being encoded, is considered to be the set of decoded bits.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Jiang in view of Disegni (US Publication No. 20230245699).
Regarding claim 3, Jiang teaches the apparatus of claim 1. However, Jiang fails to explicitly disclose:
wherein the bit weighting metric is a Hamming weight associated with a generator matrix, and wherein each bit included in a respective subset of the at least two subsets of bits has a same Hamming weight.
In the analogous art of polar codes, Disegni teaches:
wherein the bit weighting metric is a Hamming weight associated with a generator matrix, and wherein each bit included in a respective subset of the at least two subsets of bits has a same Hamming weight. (para. 102: given a set of codewords… information can be stored in at least two subsets of this set of codewords comprising each at least a codeword, each codeword in a same subset having a same Hamming weight.)
It would have been obvious, to one of ordinary skill in the art, having the teachings of Jiang an Disegni before them, before the effective filing date of the claimed invention, to incorporate using Hamming weight as a bit weighting metric to partition the set (taught by Disegni) into the apparatus for polar encoded communication (taught by Jiang) to allow for benefits such as the ability to determine what subset each codeword belongs to from their hamming weights (Disegni, para. 157).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACK K BARNETT whose telephone number is (571)270-0431. The examiner can normally be reached M-Th 8-5, F 8-4 EST.
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/JACK KENSINGTON BARNETT/ Examiner, Art Unit 2111
/MARK D FEATHERSTONE/ Supervisory Patent Examiner, Art Unit 2111