DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in the application.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement(s) (IDS), Form PTO-1449, filed 07 May 2024. The information therein was considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
►Claim(s) 1-2, 5-13 and 17-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang et al. (US 2020/0251149) (hereinafter, “Zhang”).
Re: independent claim 1, Zhang discloses in fig. 24 an apparatus, comprising: a first semiconductor die (900) comprising one or more memory arrays (100 in fig. 18) and a plurality of word line conductors (246), the plurality of word line conductors coupled with the one or more memory arrays and a plurality of first electrical contacts (86) that extend through at least a portion of the first semiconductor die; and a second semiconductor die (700) coupled with the first semiconductor die and comprising a plurality of word line driver circuits [0135], the plurality of word line driver circuits coupled with a plurality of second electrical contacts (784 in fig. 20A) that extend through at least a portion of the second semiconductor die, each of the plurality of second electrical contacts (784) coupled with a respective one of the plurality of first electrical contacts (86), and each of the plurality of word line driver circuits operable to bias a respective one of the plurality of word line conductors [0135].
Re: claim 2, Zhang discloses in fig. 24 the apparatus of claim 1, further comprising: a plurality of conductor portions (96) of the first semiconductor die having extents along a direction from a substrate of the first semiconductor die that are at least partially overlapping, each of the plurality of conductor portions (96) coupling a respective one of the plurality of first electrical contacts (86) with a respective one of the plurality of second electrical contacts (784).
Re: claim 5, Zhang discloses in fig. 24 the apparatus of claim 1, wherein at least one of the plurality of second electrical contacts (712) extends through a substrate of the second semiconductor die (700).
Re: claim 6, Zhang discloses in fig. 24 the apparatus of claim 5, wherein the at least one of the plurality of second electrical contacts (712) extends through a dielectric portion (711) formed through the substrate (708) of the second semiconductor die (700).
Re: claim 7, Zhang discloses in fig. 24 the apparatus of claim 1, wherein each of the plurality of second electrical contacts (784) is coupled with the respective one of the plurality of first electrical contacts (86) via an electrical coupling between a respective contact (988) at a surface of the first semiconductor die (900) and a respective contact (788) at a surface of the second semiconductor die (700).
Re: claim 8, Zhang discloses in fig. 24 the apparatus of claim 1, wherein the plurality of word line driver circuits comprises: a plurality of transistors (750) formed at least in part from a plurality of doped portions (708) of a substrate of the second semiconductor die.
Re: claim 9, Zhang discloses in fig. 24 the apparatus of claim 1, wherein the memory array comprises: a plurality of memory cells (within 100 in fig. 18) formed over a substrate of the first semiconductor die (900).
Re: claim 10, Zhang discloses in fig. 24 the apparatus of claim 1, wherein the plurality of word line conductors comprise one or more sets of word lines (246) arranged along a direction from a substrate of the first semiconductor die (900).
Re: claim 11, Zhang discloses in fig. 24 the apparatus of claim 1, wherein the first semiconductor die and the second semiconductor die are coupled in accordance with a face-to-face bonding (e.g. 700A, 900A).
Re: claim 12, Zhang discloses in fig. 24 the apparatus of claim 1, wherein the first semiconductor die and the second semiconductor die are coupled in accordance with a face-to-back bonding (e.g. 900A, 700B).
Re: independent claim 13, Zhang discloses in fig. 24 a method of forming a memory device, comprising: forming a first semiconductor die (900) comprising one or more memory arrays (100 in fig. 18) and a plurality of word line conductors (246), the plurality of word line conductors coupled with the one or more memory arrays and a plurality of first electrical contacts (86) that extend through at least a portion of the first semiconductor die; forming a second semiconductor die (700) comprising a plurality of word line driver circuits [0135]; and coupling each of the plurality of word line driver circuits with a respective one of the plurality of first electrical contacts (86), wherein each of the plurality of word line driver circuits is operable to bias a respective one of the plurality of word line conductors based at least in part on the coupling [0135].
Re: claim 17, Zhang discloses in fig. 24 the method of claim 13, further comprising: bonding a surface of the first semiconductor die (900) with a surface of the second semiconductor die (700), wherein the bonding comprises coupling first conductor portions (988) at the surface of the first semiconductor die (900) that are coupled with the plurality of first electrical contacts (86) with second conductor portions (788) at the surface of the second semiconductor die (700) that are coupled with the plurality of word line driver circuits.
Re: claim 18, Zhang discloses in fig. 24 the method of claim 13, further comprising: bonding the first semiconductor die with the second semiconductor die in accordance with a face-to-face bonding (e.g. 700A, 900A).
Re: claim 19, Zhang discloses in fig. 24 the method of claim 13, further comprising: bonding the first semiconductor die with the second semiconductor die in accordance with a face-to-back bonding (e.g. 900A, 700B).
Re: independent claim 20, Zhang discloses in fig. 24 an apparatus formed by a process, comprising: forming a first semiconductor die (900) comprising one or more memory arrays (100 in fig. 18) and a plurality of word line conductors (246), the plurality of word line conductors coupled with the one or more memory arrays and a plurality of first electrical contacts (86) that extend through at least a portion of the first semiconductor die; forming a second semiconductor die (700) comprising a plurality of word line driver circuits [0135]; and coupling each of the plurality of word line driver circuits with a respective one of the plurality of first electrical contacts (86), wherein each of the plurality of word line driver circuits is operable to bias a respective one of the plurality of word line conductors based at least in part on the coupling [0135].
►Claim(s) 13-14 and 16-18 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hou et al. (US 2023/0042438) (hereinafter, “Hou”).
Re: independent claim 13, Hou discloses in fig. 8 a method of forming a memory device, comprising: forming a first semiconductor die (900) comprising one or more memory arrays [0035] and a plurality of word line conductors (46), the plurality of word line conductors coupled with the one or more memory arrays and a plurality of first electrical contacts (981, 982, [0030]) that extend through at least a portion of the first semiconductor die; forming a second semiconductor die (700) comprising a plurality of word line driver circuits [0034]; and coupling each of the plurality of word line driver circuits with a respective one of the plurality of first electrical contacts (981, 982, [0030]), wherein each of the plurality of word line driver circuits is operable to bias a respective one of the plurality of word line conductors based at least in part on the coupling [0035].
Re: claim 14, Hou discloses in fig. 8 the method of claim 13, further comprising: bonding the second semiconductor die with the first semiconductor die (fig. 3); forming a plurality of cavities (713 in fig. 5) through the second semiconductor die (700) after the bonding; and forming a plurality of second electrical contacts (716 in fig. 6), based at least in part on depositing a conductor material [0052] in the plurality of cavities, that are electrically coupled with the plurality of first electrical contacts (981, 982, [0030]), wherein the coupling each of the plurality of word line driver circuits with the respective one of the plurality of first electrical contacts (981, 982, [0030]) is based at least in part on forming the plurality of second electrical contacts (716).
Re: claim 16, Hou discloses in fig. 8 the method of claim 14, further comprising: forming a plurality of second cavities (713) through a substrate (708) of the second semiconductor die (700); and forming a plurality of dielectric portions (714) based at least in part on depositing a dielectric material [0050] in the plurality of second cavities, wherein the plurality of cavities (713) are formed through the plurality of dielectric portions (714).
Re: claim 17, Hou discloses in fig. 8 the method of claim 13, further comprising: bonding a surface of the first semiconductor die (900) with a surface of the second semiconductor die (700), wherein the bonding comprises coupling first conductor portions (986) at the surface of the first semiconductor die (900) that are coupled with the plurality of first electrical contacts (981, 982, [0030]) with second conductor portions (786) at the surface of the second semiconductor die (700) that are coupled with the plurality of word line driver circuits [0034].
Re: claim 18, Hou discloses in fig. 8 the method of claim 13, further comprising: bonding the first semiconductor die (900) with the second semiconductor die (700) in accordance with a face-to-face bonding (fig. 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
►Claims 3-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 2020/0251149) (hereinafter, “Zhang”) in view of Lee et al. (US 10,937,667) (hereinafter, “Lee”).
Re: claim 3, Zhang discloses in fig. 24 the apparatus of claim 2.
Zhang does not expressly disclose wherein at least one of the plurality of second electrical contacts extends into a respective one of the plurality of conductor portions.
Lee discloses in fig. 2B an electrical contact (200) extending into a conductor portion (300).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have at least one of the plurality of second electrical contacts extend into a respective one of the plurality of conductor portion for the purpose of increasing the contact area between the electrical contact and the conductor portion as exemplified by Lee.
Re: claim 4, Zhang discloses in fig. 24 the apparatus of claim 2.
Zhang does not expressly disclose wherein the at least one of the plurality of second electrical contacts extends through a respective one of a plurality of second conductor portions of the second semiconductor die.
Lee discloses in fig. 2B an electrical contact (200) extending through a conductor portion (300).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have at least one of the plurality of second electrical contacts extend through a respective one of the plurality of second conductor portion of the second semiconductor die for the purpose of increasing the contact area between the electrical contact and the conductor portion and for connecting the semiconductor die to additional circuitry as exemplified by Lee.
►Claim 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hou et al. (US 2023/0042438) (hereinafter, “Hou”) in view of Lee et al. (US 10,937,667) (hereinafter, “Lee”).
Re: claim 15, Hou discloses in fig. 8 the method of claim 14, wherein: forming the first semiconductor die (900) comprises forming a plurality of first conductor portions (986) coupled with the plurality of first electrical contacts (981, 982, [0030]); forming the second semiconductor die (700) comprises forming a plurality of second conductor portions (786); and forming the plurality of cavities (713) comprises forming each of the plurality of cavities in contact with a respective one of the plurality of first conductor portions (986).
Hou does not expressly disclose wherein forming the plurality of cavities comprises forming each of the plurality of cavities through a respective one of the plurality of second conductor portions.
Lee discloses Lee discloses in fig. 2B an electrical contact (200) extending through a conductor portion (300).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the plurality of cavities through a respective one of the second conductor portion for the purpose of increasing the contact area between the electrical contact and the conductor portion and for connecting the semiconductor die to additional circuitry as exemplified by Lee.
►Claim 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hou et al. (US 2023/0042438) (hereinafter, “Hou”) in view of Zhang et al. (US 2020/0251149) (hereinafter, “Zhang”).
Re: claim 19, Hou discloses in fig. 8 the method of claim 13.
Hou does not expressly disclose bonding the first semiconductor die with the second semiconductor die in accordance with a face-to-back bonding.
However, face-to-back bonding is a bonding method common and well known in the art as exemplified by Zhang (see claim 19 rejection above).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2, 11-112 and 15-16 of U.S. Patent No. 11,984,150 (‘150). Although the claims at issue are not identical, they are not patentably distinct from each other because the limitations of the instant application are recited in the claims of ‘150 with only nominal differences that would have been obvious to one of ordinary skill in the art.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chen et al. US 2023/0005856 teach face-to-face bonding and face-to-back bonding.
The examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. When responding to this office action, applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALLISON BERNSTEIN whose telephone number is (571)272-9011. The examiner can normally be reached M-F 8AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ALLISON BERNSTEIN/Primary Examiner, Art Unit 2824 1/29/2026