Prosecution Insights
Last updated: May 29, 2026
Application No. 18/632,024

WORD LINE DRIVERS FOR MULTIPLE-DIE MEMORY DEVICES

Final Rejection §102§103
Filed
Apr 10, 2024
Priority
Aug 23, 2022 — continuation of 11/984,150
Examiner
BERNSTEIN, ALLISON
Art Unit
2824
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Micron Technology, Inc.
OA Round
2 (Final)
81%
Grant Probability
Favorable
3-4
OA Rounds
2m
Est. Remaining
84%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
729 granted / 900 resolved
+13.0% vs TC avg
Minimal +3% lift
Without
With
+2.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
12 currently pending
Career history
914
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
60.3%
+20.3% vs TC avg
§102
18.5%
-21.5% vs TC avg
§112
6.5%
-33.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 900 resolved cases

Office Action

§102 §103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Acknowledgment is made of applicant’s amendment, filed on 29 April 2026. The changes and remarks disclosed therein have been considered. Claims 1-10, 13, 17 and 20-22 are pending in the application. Claims 1, 4, 9, 13-14, 17 and 20 are currently amended. Claims 21-22 are new. Claims 1, 13 and 20 are independent claims. Terminal Disclaimer The terminal disclaimer filed on 29 April 2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of US 11,984,150 has been reviewed and is accepted. The terminal disclaimer has been recorded. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. ►Claim(s) 1-2, 5-10, 13, 17 and 20-22 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang et al. (US 2020/0251149) (hereinafter, “Zhang”). Re: independent claim 1, Zhang discloses in fig. 24 an apparatus, comprising: a first semiconductor die (900) comprising one or more memory arrays (100 in fig. 18) and a plurality of word line conductors (246), the plurality of word line conductors coupled with the one or more memory arrays and a plurality of first electrical contacts (86, 488, 684, 688) that extend through at least a portion of the first semiconductor die; and a second semiconductor die (700) coupled with the first semiconductor die in accordance with a face-to-back bonding (top surface (i.e. face-side) of 900A is bonded to the bottom surface (i.e. back-side) of 700B), the semiconductor die comprising a plurality of word line driver circuits [0135], the plurality of word line driver circuits coupled with a plurality of second electrical contacts (784 in fig. 20A, 712, 716) that extend through at least a portion of the second semiconductor die, each of the plurality of second electrical contacts (784, 712, 716) coupled with a respective one of the plurality of first electrical contacts (86, 488, 684, 688), and each of the plurality of word line driver circuits operable to bias a respective one of the plurality of word line conductors [0135]. Re: claim 2, Zhang discloses in fig. 24 the apparatus of claim 1, further comprising: a plurality of conductor portions (96) of the first semiconductor die having extents along a direction from a substrate of the first semiconductor die that are at least partially overlapping, each of the plurality of conductor portions (96) coupling a respective one of the plurality of first electrical contacts (86) with a respective one of the plurality of second electrical contacts (784). Re: claim 5, Zhang discloses in fig. 24 the apparatus of claim 1, wherein at least one of the plurality of second electrical contacts (712) extends through a substrate of the second semiconductor die (700). Re: claim 6, Zhang discloses in fig. 24 the apparatus of claim 5, wherein the at least one of the plurality of second electrical contacts (712) extends through a dielectric portion (711) formed through the substrate (708) of the second semiconductor die (700). Re: claim 7, Zhang discloses in fig. 24 the apparatus of claim 1, wherein each of the plurality of second electrical contacts (784) is coupled with the respective one of the plurality of first electrical contacts (86) via an electrical coupling between a respective contact (988) at a surface of the first semiconductor die (900) and a respective contact (788) at a surface of the second semiconductor die (700). Re: claim 8, Zhang discloses in fig. 24 the apparatus of claim 1, wherein the plurality of word line driver circuits comprises: a plurality of transistors (750) formed at least in part from a plurality of doped portions (708) of a substrate of the second semiconductor die. Re: claim 9, Zhang discloses in fig. 24 the apparatus of claim 1, wherein each memory array of the one of more memory arrays comprises: a plurality of memory cells (within 100 in fig. 18) formed over a substrate of the first semiconductor die (900). Re: claim 10, Zhang discloses in fig. 24 the apparatus of claim 1, wherein the plurality of word line conductors comprise one or more sets of word lines (246) arranged along a direction from a substrate of the first semiconductor die (900). Re: independent claim 13, Zhang discloses in fig. 24 a method of forming a memory device, comprising: forming a first semiconductor die (900) comprising one or more memory arrays (100 in fig. 18) and a plurality of word line conductors (246), the plurality of word line conductors coupled with the one or more memory arrays and a plurality of first electrical contacts (86, 488, 684, 688) that extend through at least a portion of the first semiconductor die; forming a second semiconductor die (700) comprising a plurality of word line driver circuits [0135]; bonding the first semiconductor die with the second semiconductor die in accordance with face-to-back bonding (top surface (i.e. face-side) of 900A is bonded to the bottom surface (i.e. back-side) of 700B); and coupling each of the plurality of word line driver circuits with a respective one of the plurality of first electrical contacts (86, 488, 684, 688), wherein each of the plurality of word line driver circuits is operable to bias a respective one of the plurality of word line conductors based at least in part on the coupling [0135]. Re: claim 17, Zhang discloses in fig. 24 the method of claim 13, further comprising: wherein the bonding comprises: coupling first conductor portions (988) at a surface of the first semiconductor die (900) that are coupled with the plurality of first electrical contacts (86) with second conductor portions (788) at a surface of the second semiconductor die (700) that are coupled with the plurality of word line driver circuits. Re: independent claim 20, Zhang discloses in fig. 24 an apparatus formed by a process, comprising: forming a first semiconductor die (900) comprising one or more memory arrays (100 in fig. 18) and a plurality of word line conductors (246), the plurality of word line conductors coupled with the one or more memory arrays and a plurality of first electrical contacts (86, 488, 684, 688) that extend through at least a portion of the first semiconductor die; forming a second semiconductor die (700) comprising a plurality of word line driver circuits [0135]; bonding the first semiconductor die with the second semiconductor die in accordance with face-to-back bonding (top surface (i.e. face-side) of 900A is bonded to the bottom surface (i.e. back-side) of 700B); and coupling each of the plurality of word line driver circuits with a respective one of the plurality of first electrical contacts (86, 488, 684, 688), wherein each of the plurality of word line driver circuits is operable to bias a respective one of the plurality of word line conductors based at least in part on the coupling [0135]. Re: claim 21, Zhang discloses in fig. 24 the apparatus of claim 1, wherein the plurality of second electrical contacts (including 712) extend through a semiconductor substrate (708) of the second semiconductor die. Re: claim 22, Zhang discloses in fig. 24 the method of claim 13, wherein each of the plurality of word line driver circuits is coupled with the respective one of the plurality of first electrical contacts (including 688) via a respective second electrical contact (including 712) that extends through a semiconductor substrate (708) of the second semiconductor die. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. ►Claims 3-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 2020/0251149) (hereinafter, “Zhang”) in view of Lee et al. (US 10,937,667) (hereinafter, “Lee”). Re: claim 3, Zhang discloses in fig. 24 the apparatus of claim 2. Zhang does not expressly disclose wherein at least one of the plurality of second electrical contacts extends into a respective one of the plurality of conductor portions. Lee discloses in fig. 2B an electrical contact (200) extending into a conductor portion (300). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have at least one of the plurality of second electrical contacts extend into a respective one of the plurality of conductor portion for the purpose of increasing the contact area between the electrical contact and the conductor portion as exemplified by Lee. Re: claim 4, Zhang discloses in fig. 24 the apparatus of claim 3. Zhang does not expressly disclose wherein the at least one of the plurality of second electrical contacts extends through a respective one of a plurality of second conductor portions of the second semiconductor die. Lee discloses in fig. 2B an electrical contact (200) extending through a conductor portion (300). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have at least one of the plurality of second electrical contacts extend through a respective one of the plurality of second conductor portion of the second semiconductor die for the purpose of increasing the contact area between the electrical contact and the conductor portion and for connecting the semiconductor die to additional circuitry as exemplified by Lee. Allowable Subject Matter Claims 14-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Response to Arguments Applicant's arguments filed 29 April 2026 with respect to Zhang have been fully considered but they are not persuasive. In light of the amendment filed 29 April 2026 the rejection over Hou has been withdrawn. Applicant argues that the semiconductor dies of Zhang are not bonded in accordance with face-to-back bonding. In response, the top surface (i.e. face-side) of semiconductor die 900A is bonded with a bottom surface (i.e. back-side) of semiconductor die 700B. See annotated figure below. Additionally, face-to-back bonding, back-to-back bonding and face-to-face bonding are common and well known bonding methods in the semiconductor art. PNG media_image1.png 564 704 media_image1.png Greyscale Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALLISON BERNSTEIN whose telephone number is (571)272-9011. The examiner can normally be reached M-F 8AM-5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ALLISON BERNSTEIN/Primary Examiner, Art Unit 2824 5/13/2026
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Prosecution Timeline

Apr 10, 2024
Application Filed
Feb 02, 2026
Non-Final Rejection mailed — §102, §103
Apr 29, 2026
Response Filed
May 19, 2026
Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
81%
Grant Probability
84%
With Interview (+2.7%)
2y 4m (~2m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 900 resolved cases by this examiner. Grant probability derived from career allowance rate.

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