DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Final communication in response to communication filed 12/30/25.
Response to Arguments
Applicant's arguments filed 12/30/25 have been fully considered but they are not persuasive.
With respect to claims 1 and 13, Applicant argues that Kim and Sun fail to anticipate at least the claimed feature of "a compensation transistor, wherein a first terminal of the compensation transistor receives a common voltage different from the power voltage, and wherein a voltage difference value between a voltage value at a first terminal of the driving transistor and a voltage value at a gate terminal of the driving transistor is determined," citing fig. 3, claim 8 and paragraph 0034 (describing fig. 2) in support.
In addition applicant argues that the claims disclose that the VSG of the driving transistor is based on the common voltage and that Kim and Sun do not disclose the determination of the voltage difference (VSG) based on a common voltage different from the power voltage. As evidence applicant cites paragraph [0160], figure 13 and equation Vref + Vth + (VDD - Vdata) from paragraph [0160], for the voltage at N2 (gate of drive transistor) in figure 13A of Kim.
Applicant uses the equation:
Vref - (Vref + Vth + (VDD - Vdata)) = Vdata - Vth - VDD
to determine the difference of the source and gate of the drive transistor, concluding that because Vref is cancelled in the simplification of the equation, “Kim does not disclose the claimed determination of the voltage difference based on a common voltage different from the power voltage.”
The examiner respectfully disagrees with the conclusion, that cancellation of Vref in the simplified equation means the equation to determine a VSG of the drive transistor is not based on Vref or that the amended claim language requires the determination of VSG be based on Vref/common voltage different from the power voltage.
Both Kim and applicant selectively apply Vref(Kim)/common voltage(applicant) through a transistor (T2, Kim; TC, compensation transistor in Application) to the source of the drive transistor in response to a scan signal being low. This is seen in TD2 of applicants figure 2 and for Scan(n) low in figure 13B of Kim.
The examiner respectfully disagrees with the equation to calculate VSG of the driving transistor used by applicant. Applicant cites, paragraph [0160] describing figure 13A/B of Kim, for the equation to calculate the gate voltage of N2 of drive transistor DT, but Paragraph [0160] also discloses “the high-level power voltage VDD may be applied to the source of the driving transistor DT and thus, the driving transistor DT may be turned on.” In figure 13A and paragraph [0160] transistor T3 is ON and VDD is seen at the source [N1] of the drive transistor, but it is not part of the source voltage in the equation cited above. The equation instead uses Vref alone as the source voltage despite T2 being off in figure 13A/B/paragraph [0160]. Based on this, the examiner believes the determination of the difference between the gate and source voltages of the drive transistor in figure 13A would include Vref in the equation and not be cancelled in a simplified equation.
Additionally, applicants claim does not define a specific status of the circuit when VSG of the driving transistor is being determined, as changing inputs to the circuit, seen in figures 10A, 11A, 12A and 13A of Kim, will change voltages seen at the gate and source of the drive transistor and change the equation in each status. Further, the transistors and signals controlling the voltages seen at source and gate of the drive transistor with respect to the common voltage(application)/reference voltage(references) and Power, ARVDD/VDD are the same in Kim [fig. 13A/B], MA [fig. 2, 3] and the application [fig. 1, 2, 3, 4; paragraph 0034; used as support for amendment]. The examiner believes the voltage value (Vref) used by applicant for the source voltage of the drive transistor is NOT from the same point in time to the part of the equation used for the gate voltage of the drive transistor in figure 13A, paragraph [0160], as VDD is supplied to the source of the drive transistor.
The examiner has provided new reference MA 20160253958 to additionally read on the amendments as figures 2 and 3 also have substantially similar connections and timings for Scan [low], reset and Emission signals during TD2, fig. 2 in applicants timing figures and mentioned in paragraph 0034, cited as support for the amendments.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5, 7, 8 and 21 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by MA 20160253958.
With respect to claim 1, figures 1-3 of MA discloses an electronic circuit, comprising: an electronic element [D1];
a driving transistor [DTFT], wherein a power voltage [VDD] is used to drive the electronic element via the driving transistor;
a first emitting transistor [ME], wherein a first terminal of the first emitting transistor is coupled to the power voltage [VDD], and a second terminal of the first emitting transistor is coupled to the driving transistor;
a compensation transistor [MRef], wherein a first terminal of the compensation transistor receives a common voltage [Vref] different from the power voltage [VDD], and wherein a voltage difference value between a voltage value at a first terminal of the driving transistor and a voltage value at a gate terminal of the driving transistor is determined; and
at least one capacitor [CST], wherein a first terminal of the at least one capacitor is coupled to a gate terminal of the driving transistor, wherein when the electronic element is driven, a second terminal of the at least one capacitor receives the power voltage [ME and ML2 are on at the same time].
With respect to claim 2, figures 1-3 of MA disclose the electronic circuit of claim 1, further comprising: a second emitting transistor [ML1], wherein a first terminal of the second emitting transistor is coupled to the electronic element [D1], and a second terminal of the second emitting transistor is coupled to the driving transistor [gate].
With respect to claim 3, figures 1-3 of MA disclose The electronic circuit of claim 2, wherein a gate terminal of the second emitting transistor receives an enabling signal [Scan].
With respect to claim 4, figures 1-3 of MA disclose The electronic circuit of claim 1, further comprising: a third emitting transistor [ML2], wherein a first terminal of the third emitting transistor is coupled to the power voltage [VDD], and a second terminal of the third emitting transistor is coupled to the at least one capacitor [CST].
With respect to claim 5, figures 1-3 of MA disclose The electronic circuit of claim 4, wherein a gate terminal of the third emitting transistor receives an enabling signal [Emission].
With respect to claim 7, figures 1-3 of MA disclose the electronic circuit of claim 1, further comprising: a data transistor [MD], wherein a first terminal of the data transistor receives a data signal [Vdata], a second terminal of the data transistor is coupled to the at least one capacitor [CST], and a gate terminal of the data transistor receives a scan signal [Scan].
With respect to claim 8, figures 1-3 of MA disclose the electronic circuit of claim 1, wherein a second terminal of the compensation transistor [MRef] is coupled to the second terminal of the first emitting transistor[ME], and a gate terminal of the compensation transistor receives a scan signal [Scan].
With respect to claim 21, figures 1-3 of MA disclose the electronic circuit of claim 1, wherein the voltage value at the first terminal of the driving transistor is substantially equal to the voltage value of the common voltage. [Scan low]
Claims 1-5, 7, 8, and 13-16, 21 and 22 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al. 2019/0164491.
With respect to claim 1, figures 9-13B of Kim et al. disclose an electronic circuit, comprising:
an electronic element;
a driving transistor [DT], wherein a power voltage is used to drive the electronic element via the driving transistor;
a first emitting transistor [T3], wherein a first terminal of the first emitting transistor is coupled to the power voltage, and a second terminal of the first emitting transistor is coupled to the driving transistor; and
a compensation transistor [T2], wherein a first terminal of the compensation transistor receives a common voltage [Vref] different from the power voltage [VDD], and wherein a voltage difference value between a voltage value at a first terminal of the driving transistor and a voltage value at a gate terminal of the driving transistor is determined; and
at least one capacitor [Cst], wherein a first terminal of the at least one capacitor is coupled to a gate terminal of the driving transistor,
wherein when the electronic element is driven, a second terminal of the at least one capacitor receives the power voltage [see fig. 13A].
With respect to claim 2, figures 9-13B of Kim et al. disclose the electronic circuit of claim 1, further comprising:
a second emitting transistor [T4], wherein a first terminal of the second emitting transistor is coupled to the electronic element, and a second terminal of the second emitting transistor is coupled to the driving transistor.
With respect to claim 3, figures 9-13B of Kim et al. disclose the electronic circuit of claim 2, wherein a gate terminal of the second emitting transistor receives an enabling signal [EM(n)].
With respect to claim 4, figures 9-13B of Kim et al. disclose the electronic circuit of claim 1, further comprising:
a third emitting transistor [T6], wherein a first terminal of the third emitting transistor is coupled to the power voltage, and a second terminal of the third emitting transistor is coupled to the at least one capacitor.
With respect to claim 5, figures 9-13B of Kim et al. disclose the electronic circuit of claim 4, wherein a gate terminal of the third emitting transistor receives an enabling signal [EM(n)].
With respect to claim 7, figures 9-13B of Kim et al. disclose the electronic circuit of claim 1, further comprising:
a data transistor [T7], wherein a first terminal of the data transistor receives a data signal, a second terminal of the data transistor is coupled to the at least one capacitor, and a gate terminal of the data transistor receives a scan signal [Scan(n)].
With respect to claim 8, figures 9-13B of Kim et al. disclose the electronic circuit of claim 1, further comprising:
a compensation transistor [T2], wherein a first terminal of the compensation transistor receives a common voltage [Vref], a second terminal of the compensation transistor is coupled to the second terminal of the first emitting transistor, and a gate terminal of the compensation transistor receives a scan signal [Scan(n)].
With respect to claim 13, figures 9-13B of Kim et al. disclose an electronic circuit, comprising:
an electronic element [EL];
a driving transistor [DT], wherein a first terminal of the driving transistor is coupled to a power voltage, and the power voltage is used to drive the electronic element via the driving transistor;
a first emitting transistor [T4], wherein a first terminal of the first emitting transistor is coupled to a second terminal of the driving transistor, and a second terminal of the first emitting transistor is coupled to the electronic element; and
a compensation transistor [T2], wherein a first terminal of the compensation transistor receives a common voltage [Vref] different from the power voltage[VDD], and wherein a voltage difference value between a voltage value at the first terminal of the driving transistor and a voltage value at a gate terminal of the driving transistor is determined; and
at least one capacitor [Cst], wherein a first terminal of the at least one capacitor is coupled to a gate terminal of the driving transistor,
wherein when the electronic element is driven, a second terminal of the at least one capacitor receives the power voltage. [See fig. 13A]
With respect to claim 14, figures 9-13B of Kim et al. disclose the electronic circuit of claim 13, wherein a gate terminal of the first emitting transistor receives an enabling signal. [EM(n)]
With respect to claim 15, figures 9-13B of Kim et al. disclose the electronic circuit of claim 13, further comprising:
a second emitting transistor [T6], wherein a first terminal of the second emitting transistor is coupled to the power voltage, and a second terminal of the second emitting transistor is coupled to the at least one capacitor.
With respect to claim 16, figures 9-13B of Kim et al. disclose the electronic circuit of claim 15, wherein a gate terminal of the second emitting transistor receives an enabling signal. [EM(n)]
With respect to claim 21, figures 9-13B of Kim et al disclose the electronic circuit of claim 1, wherein the voltage value at the first terminal of the driving transistor is substantially equal to the voltage value of the common voltage. [fig 11A]
With respect to claim 22 figures 9-13B of Kim et al disclose the electronic circuit of claim 13, wherein the voltage value at the first terminal of the driving transistor is substantially equal to the voltage value of the common voltage. [fig. 11A]
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-12,13-16, 18-22 are rejected under 35 U.S.C. 103 as being unpatentable over Sun et al 20160284269 in view of Kim et al.
With respect to claim 1, figures 1 of Sun et al. disclose an electronic circuit, comprising:
an electronic element D;
a driving transistor [T7], wherein a power voltage is used to drive the electronic element via the driving transistor; and
at least one capacitor [Cst], wherein a first terminal of the at least one capacitor is coupled to a gate terminal of the driving transistor,
wherein when the electronic element is driven, a second terminal of the at least one capacitor receives the power voltage [see fig. 13A].
Sun et al. does not disclose a first emitting transistor, wherein a first terminal of the first emitting transistor is coupled to the power voltage, and a second terminal of the first emitting transistor is coupled to the driving transistor;
However , figures 9-13B of Kim et al. Kim et al. disclose a first emitting transistor [T3], wherein a first terminal of the first emitting transistor is coupled to the power voltage, and a second terminal of the first emitting transistor is coupled to the driving transistor.
It would have been obvious to one skilled in the art to add another emitting transistor connected as stated above since it’s a known technique in the art.
Sun et al. does not disclose a compensation transistor, wherein a first terminal of the compensation transistor receives a common voltage different from the power voltage, and wherein a voltage difference value between a voltage value at the first terminal of the driving transistor and a voltage value at a gate terminal of the driving transistor is determined; and
However, Figure 9 of Kim discloses a compensation transistor [T2], wherein a first terminal of the compensation transistor receives a common voltage [Vref] different from the power voltage, and wherein a voltage difference value between a voltage value at the first terminal of the driving transistor and a voltage value at a gate terminal of the driving transistor is determined.
It would have been obvious to provide a compensation transistor T2 controlled by Scan signal as seen in figure 9 of Kim in Sun et al. to provide Vref to the source of the drive transistor T7, at the control of the gate/scan signal while also controlling T4 and T3 of Sun et al since it was a known technique in the art.
With respect to claim 2 the above combination discloses the electronic circuit of claim 1, further comprising:
a second emitting transistor [T6], wherein a first terminal of the second emitting transistor is coupled to the electronic element, and a second terminal of the second emitting transistor is coupled to the driving transistor.
With respect to claim 3 the above combination discloses the electronic circuit of claim 2, wherein a gate terminal of the second emitting transistor receives an enabling signal [EM].
With respect to claim 4 the above combination discloses the electronic circuit of claim 1, further comprising:
a third emitting transistor [T5], wherein a first terminal of the third emitting transistor is coupled to the power voltage, and a second terminal of the third emitting transistor is coupled to the at least one capacitor.
With respect to claim 5 the above combination discloses the electronic circuit of claim 4, wherein a gate terminal of the third emitting transistor receives an enabling signal [EM].
With respect to claim 7 the above combination discloses the electronic circuit of claim 1, further comprising:
a data transistor [T4], wherein a first terminal of the data transistor receives a data signal [Data], a second terminal of the data transistor is coupled to the at least one capacitor, and a gate terminal of the data transistor receives a scan signal [Gate].
With respect to claim 8 the above combination discloses the electronic circuit of claim 1, but does not disclose further comprising:
a second terminal of the compensation transistor is coupled to the second terminal of the first emitting transistor, and a gate terminal of the compensation transistor receives a scan signal.
With respect to claim 9 the above combination discloses, further comprising:
a first reset transistor [T2], wherein a first terminal of the first reset transistor is coupled to the power voltage, and a second terminal of the first reset transistor is coupled to the second terminal of the at least one capacitor.
With respect to claim 10 the above combination discloses the electronic circuit of claim 9, wherein a gate terminal of the first reset transistor receives a reset signal [Reset].
With respect to claim 11 the above combination discloses the electronic circuit of claim 9, further comprising:
a second reset transistor [T1], wherein a first terminal of the second reset transistor is coupled to a reset voltage [ini], and a second terminal of the second reset transistor is coupled to the first terminal of the at least one capacitor.
With respect to claim 12 the above combination discloses the electronic circuit of claim 11, wherein a gate terminal of the second reset transistor receives a reset signal [Reset].
With respect to claim 13, the above combination discloses an electronic circuit, comprising:
an electronic element [D];
a driving transistor [T7], wherein a first terminal of the driving transistor is coupled to a power voltage, and the power voltage is used to drive the electronic element via the driving transistor;
a first emitting transistor [T6], wherein a first terminal of the first emitting transistor is coupled to a second terminal of the driving transistor, and a second terminal of the first emitting transistor is coupled to the electronic element; and
a compensation transistor [T2. Kim], wherein a first terminal of the compensation transistor receives a common voltage [Vref] different from the power voltage, and wherein a voltage difference value between a voltage value at the first terminal of the driving transistor and a voltage value at a gate terminal of the driving transistor is determined; and
at least one capacitor [C1], wherein a first terminal of the at least one capacitor is coupled to a gate terminal of the driving transistor,
wherein when the electronic element is driven, a second terminal of the at least one capacitor receives the power voltage.
With respect to claim 14, the above combination discloses the electronic circuit of claim 13, wherein a gate terminal of the first emitting transistor receives an enabling signal. [EM]
With respect to claim 15, the above combination discloses the electronic circuit of claim 13, further comprising:
a second emitting transistor [T5], wherein a first terminal of the second emitting transistor is coupled to the power voltage, and a second terminal of the second emitting transistor is coupled to the at least one capacitor.
With respect to claim 16, the above combination discloses the electronic circuit of claim 15, wherein a gate terminal of the second emitting transistor receives an enabling signal. [EM]
With respect to claim 18, the above combination discloses the electronic circuit of claim 13, further comprising:
a first reset transistor [T2], wherein a first terminal of the first reset transistor is coupled to the
power voltage, and a second terminal of the first reset transistor is coupled to the second terminal of the at least one capacitor.
With respect to claim 19, the above combination discloses the electronic circuit of claim 18, wherein a gate terminal of the first reset transistor receives a reset signal. [Reset]
With respect to claim 20, the above combination discloses the electronic circuit of claim 18, further comprising:
a second reset transistor [T1], wherein a first terminal of the second reset transistor is coupled to a reset voltage [ini], and a second terminal of the second reset transistor is coupled to the first terminal of the at least one capacitor.
With respect to claim 21 the above combination discloses the electronic circuit of claim 1, wherein the voltage value at the first terminal of the driving transistor is substantially equal to the voltage value of the common voltage. [Fig. 11A]
With respect to claim 22 the above combination discloses the electronic circuit of claim 13, wherein the voltage value at the first terminal of the driving transistor is substantially equal to the voltage value of the common voltage. [Fig. 11A]
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN C JAGER whose telephone number is (571)272-7016. The examiner can normally be reached on 8:30 - 5:30 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached on (571)270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RYAN JAGER/
Primary Examiner, Art Unit 2842
1/16/26