DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in the application.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement(s) (IDS), Form PTO-1449, filed 11 April 2024. The information therein was considered.
Claim Objections
Claim 11 is objected to because of the following informalities:
Claim 11 recites “the bottom FET” which should be replaced with --the first bottom FET--.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-12, 14-17 and 19-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al. (US 2024/0313000) (hereinafter, “Kim”).
Re: independent claim 1, Kim discloses in figs. 2A-2C a semiconductor device, comprising: a top field effect transistor (FET) (including SD22); a bottom FET (including SD11); a first conductive via (222) in electrical connection with a first conductive interconnect (273) beneath the bottom FET; a second conductive via (232) in electrical connection with the first conductive via (222); and a backside top FET contact (282) in electrical connection with the top FET and with a side surface of the second conductive via (232).
Re: claim 2, Kim discloses in figs. 2A-2C the semiconductor device of claim 1, wherein the first conductive via (222) has a top surface at a height between a height of a bottom surface of the top FET (including SD22) and a height of a top surface of the bottom FET (including SD11), relative to a back side of the device.
Re: claim 3, Kim discloses in figs. 2A-2C the semiconductor device of claim 1, wherein the first conductive via (222) and the second conductive via (232) are tapered, with each having a respective top surface that is wider than a respective bottom surface (figs. 2A-2C).
Re: claim 4, Kim discloses in figs. 2A-2C the semiconductor device of claim 1, further comprising a back-end-of-line (BEOL) layer (M1-M15), above the top FET, that includes a second conductive interconnect (M1-M15).
Re: claim 5, Kim discloses in figs. 2A-2C the semiconductor device of claim 4, further comprising: a frontside bottom FET contact (231) in electrical connection to the second conductive interconnect (M4); a third via (221) in electrical connection to the frontside bottom FET contact; and a bottom FET contact (261) in electrical connection to the third via and to the bottom FET.
Re: claim 6, Kim discloses in figs. 2A-2C the semiconductor device of claim 1, wherein the second conductive via (232) has a top surface with a height greater than a height of a top surface of the top FET (including SD22), relative to a back side of the device.
Re: independent claim 7, Kim discloses in figs. 2A-2C a semiconductor device, comprising: a first stacked pair of field effect transistors (FETs), including: a first top FET (including SD22); a first bottom FET (including SD21); a first conductive via (222) in electrical connection with a first conductive interconnect (273) under the first bottom FET; a second conductive via (232) in electrical connection with the first conductive via (222); and a backside top FET contact (282) in electrical connection with the first top FET and with a side surface of the second conductive via (232); and a second stacked pair of FETs, including: a second top FET (including SD12); a second bottom FET (SD11); a frontside bottom FET contact (231) in electrical connection to a second conductive interconnect (M4) above the second top FET; a third via (221) in electrical connection to the frontside bottom FET contact (231); and a bottom FET contact (261) in electrical connection to the third via (221) and to the second bottom FET.
Re: claim 8, Kim discloses in figs. 2A-2C the semiconductor device of claim 7, wherein the first conductive via (222) has a top surface at a height between a height of a bottom surface of the first top FET (including SD22) and a height of a top surface of the first bottom FET (including SD11), relative to a back side of the device.
Re: claim 9, Kim discloses in figs. 2A-2C the semiconductor device of claim 7, wherein the first conductive via (222) and the second conductive via (232) are tapered, with each having a respective top surface that is wider than a respective bottom surface (figs, 2A-2C).
Re: claim 10, Kim discloses in figs. 2A-2C the semiconductor device of claim 7, further comprising a back-end-of-line (BEOL) layer (M1-M15), above the top FET, that includes the second conductive interconnect (M1-M15).
Re: claim 11, Kim discloses in figs. 2A-2C the semiconductor device of claim 7, further comprising a buried power distribution layer (273), below the first bottom FET (including SD21), that includes the first conductive interconnect (273).
Re: claim 12, Kim discloses in figs. 2A-2C the semiconductor device of claim 7, wherein the second conductive via (232) has a top surface with a height greater than a height of a top surface of the first top FET (including SD22), relative to a back side of the device.
Re: independent claim 14, Kim discloses in figs. 2A-2C a semiconductor device, comprising: a buried power distribution layer (273) that includes a first conductive interconnect (273); a back-end-of-line (BEOL) layer (M1-M15) that includes a second conductive interconnect (M4); a first stacked pair of field effect transistors (FETs) between the buried power distribution layer and the BEOL layer, including: a first top FET (including SD22); a first bottom FET (SD21); a first conductive via (222) in electrical connection with the first conductive interconnect (273); a second conductive via (232) in electrical connection with the first conductive via (222); and a backside top FET contact (282) in electrical connection with the first top FET and with a side surface of the second conductive via (232); and a second stacked pair of FETs between the buried power distribution layer and the BEOL layer, including: a second top FET (SD12); a second bottom FET (SD11); a frontside bottom FET contact (231) in electrical connection to the second conductive interconnect (M4); a third via (221) in electrical connection to the frontside bottom FET contact (231); and a bottom FET contact (261) in electrical connection to the third via (221) and to the second bottom FET.
Re: claim 15, Kim discloses in figs. 2A-2C the semiconductor device of claim 14, wherein the first conductive via (222) has a top surface at a height between a height of the first top FET (including SD22) and a height of the first bottom FET (including SD21).
Re: claim 16, Kim discloses in figs. 2A-2C the semiconductor device of claim 14, wherein the first conductive via (222) and the second conductive via (232) are tapered, with each having a respective top surface that is wider than a respective bottom surface (figs. 2A-2C).
Re: claim 17, Kim discloses in figs. 2A-2C the semiconductor device of claim 14, wherein the second conductive via (232) has a top surface with a height greater than a height of a top surface of the first top FET (including SD22).
Re: claim 19, Kim discloses in figs. 2A-2C the semiconductor device of claim 14, further comprising a third stacked pair of FETs between the buried power distribution layer and the BEOL layer, including: a third top FET (including SD32); a third bottom FET (SD31); a frontside top FET contact (283) in electrical connection between a third conductive interconnect (M12) in the BEOL layer and the third top FET; and a backside bottom FET contact (263) in an electrical connection between a fourth conductive interconnect (BM19) in the buried power distribution layer and the third bottom FET.
Re: claim 20, Kim discloses in figs. 2A-2C the semiconductor device of claim 19, wherein the backside bottom FET contact (263) is directly below the third bottom FET (including SD31).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2024/0313000) (hereinafter, “Kim”).
Re: claims 13 and 18, Kim discloses in figs. 2A-2C the semiconductor device of claims 7 and 14.
Kim does not disclose, wherein the first conductive via has a top surface with a height that is the same as a height of a top surface of the bottom FET contact, relative to a back side of the device.
However, the height of the first conductive via relative to the height of the bottom FET contact is a matter of design choice that would have been obvious to one of ordinary skill in the art.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Xie et al. US 2025/0081525 teach a via to avoid local interconnect shorting.
Senapati et al. US 2025/0125261 teach semiconductor structures with multi-stage vias.
The examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. When responding to this office action, applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALLISON BERNSTEIN whose telephone number is (571)272-9011. The examiner can normally be reached M-F 8AM-5PM.
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/ALLISON BERNSTEIN/Primary Examiner, Art Unit 2824 06/08/2026
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