DETAILED ACTION
This office action is in response to the filing with the office dated 04/11/2024
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. REPUBLIC OF KOREA 10-2023-0102435, filed on 08/04/2024. And application No. REPUBLIC OF KOREA 10-2023-0160705, filed on 11/20/2023
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/11/2024. Are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of 7-13 in the reply filed on 2/20/2026 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 7-9 and 11-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KIM et al. (Hereinafter, “Kim”) in the Patent Application Publication Number US 20220107355 A1.
In regards to independent claim 7, Kim teaches, “A semiconductor test apparatus, ([0002], “a substrate testing apparatus for detecting failures in a semiconductor substrate.” Reads on “semiconductor test apparatus.”)
Comprising: a lower housing that provides a test space; ([0036], “heating chuck” reads on “lower housing that provides a test space”
A window plate in the test space; ([0035], “The photographing aperture 200H of the heating chuck 200 may be an opening configured to allow the substrate S to be photographed via camera 500.” Reads on a window plate in the test space.”)
And a hot electron analysis (HEA) lens downwardly spaced apart from the window plate, ([0062], “The lens 550 may be between the camera 500 and the heating chuck 200 and is configured to collect and focus a light.” Reads on “(HEA) lens downwardly spaced apart from the window plate.”)
Wherein the window plate comprises: a plate body; and a support device coupled to the plate body, ([0032], “The support plate 110 may have a mounting opening 110H configured to contain the heating chuck 200 in a central portion thereof.” Reads on “a support device coupled to the plate body.”)
Wherein the plate body provides a plate through hole that vertically penetrates the plate body, ([0007], “The heating chuck has an aperture that extends through the first surface and the second surface in a vertical direction.” Reads on “The heating chuck has an aperture that extends through the first surface and the second surface in a vertical direction.”)
Wherein at least a portion of the support device is inserted into the plate through hole, ([0034], “In an example embodiment, the heating chuck 200 may have a first surface 200a on which the substrate S is mounted and a second surface 200b that is opposite to the first surface 200b. Also, the heating chuck 200 may have a photographing aperture 200H, which passes through the first surface 200a and the second surface 200b of the heating chuck 200 in a vertical direction.” Reads on “a portion of the support device is inserted into the plate through hole.”)
And wherein the support device provides a placement hole that is downwardly recessed from a top surface of the support device.” ([0034], “Also, the heating chuck 200 may have a photographing aperture 200H, which passes through the first surface 200a and the second surface 200b of the heating chuck 200 in a vertical direction.” Reads on, “placement hole.”)
As per claim 8, Kim teaches, “The semiconductor test apparatus of claim 7, wherein a bottom surface of the support device is exposed toward the HEA lens.” ([0062], “The lens 550 may be between the camera 500 and the heating chuck 200 and is configured to collect and focus a light.” Also see figure 2 Reads on “a bottom of the support device is expose ([0007],” The heating chuck has an aperture that extends through the first surface and the second surface in a vertical direction. The heating chuck is on the upper surface of the housing such that a portion of a lower surface of the heating chuck is exposed by the housing opening.” Reads on, “insertion member in the plate through hole, the insertion member supporting the support device.”)
As per claim 9, “The semiconductor test apparatus of claim 7, wherein the placement hole has a tetragonal shape, and wherein a width of the placement hole is in a range of about 0.5 cm to about 5 cm.” ([0036], “the photographing aperture 200H of the heating chuck 200 may have a tetragonal shape.” Furthermore, “The photographing aperture 200H of the heating chuck 200 may have a square shape having a horizontal length and a vertical length of about 5 cm,” reads on “placement hole have a tetragonal shape, and wherein a width of the placement hole is in a range of about 0.5 cm to about 5 cm.)
As per claim 11, Kim teaches, “The semiconductor test apparatus of claim 7, further comprising an insertion member in the plate through hole, the insertion member supporting the support device.”([0034], “the heating chuck 200 may have a photographing aperture 200H, which passes through the first surface 200a and the second surface 200b of the heating chuck 200 in a vertical direction.” Reads on “insertion member.”)
As per claim 12, Kim teaches “The semiconductor test apparatus of claim 7, wherein the window plate further includes a lower support member coupled to a bottom surface of the plate body, the lower support member being disposed below the plate through hole, and wherein the support device is supported by a top surface of the lower support member.” ([0037], “In an example embodiment, the heating chuck 200 may include an upper plate (refer to 210 in FIG. 4) having the first surface 200a, a lower plate (refer to 230 in FIG. 4), which is combined with the upper plate 210 and has the second surface 200b,” reads on “lower support member coupled to a bottom surface of the plate body, the lower support member being disposed below the plate through hole, and wherein the support device is supported by a top surface of the lower support member”)
As per claim 13, “The semiconductor test apparatus of claim 7, further comprising: a probe card on the window plate; and a tester configured to supply the probe card with a test power.” ([0045], “The probe device 400 may be positioned over the heating chuck 200 and may be a device configured to apply a voltage to a portion of the substrate to perform a stand-by failure test on the substrate S. The probe device 400 may include a pogo block 410, a probe card 420, and at least one probe pin 430.” Reads on, “probe card” and “tester” moreover, “test power.”)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. In view of MASUKO et al. (Hereinafter, Masuko in the Patent Application Number US 5023447 A.
As per claim 10, Kim is silent on, “The semiconductor test apparatus of claim 7, wherein the support device includes a sapphire glass.”
While Masuko teaches, “The semiconductor test apparatus of claim 7, wherein the support device includes a sapphire glass.” ([0005], “and a glass member or plate 40 of sapphire glass.” Reads on, “sapphire glass.”)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Kim by Masuko by implementing the teachings of Sapphire glass. The use of Sapphire glass is well-known in the art and would yield the predictable result of improving the lens durability. (KSR)
Closest Prior art
The following relevant prior art of record is not cited in the office action.
Kobayashi et al (US 20230110797 A1) teaches, A stage includes a base on which an object to be transported or tested is placed, four movable bodies configured to support the base in a manner so that the base can be raised and lowered, four driving motors, provided in correspondence with the four movable bodies, and configured to independently raise and lower the four movable bodies, respectively, four guides configured to guide the four movable bodies, respectively, and a support frame, having wall surfaces parallel to a raising and lowering direction of the base and continuous along a direction perpendicular to the raising and lowering direction of the base, and the four guides fixed to the wall surfaces.
Cho et al (US 20200164296 A1) teaches, Disclosed is an apparatus for collecting a by-product in a semiconductor manufacturing process. An objective of the present invention is to provide an apparatus for collecting a by-product such that exhaust gas having great amount of light gas is coagulated while having sufficient residence time in a long flow path, whereby the exhaust gas is collected as a high-density by-product. For this purpose, the apparatus includes: a housing receiving and discharging introduced exhaust gas and configured with a horizontal vortex plate; an upper plate covering an upper portion of the housing; an internal collecting tower provided with a collecting tower cover and a seed eliminating fin to extend a flow path and residence time of the exhaust gas; a heater having a heat conduction plate; and an extended discharging pipe configured to extend the flow path and residence time of the exhaust gas and discharge the exhaust gas.
Anderson et al (US 20190120874 A1) teaches, A method of testing semiconductor devices includes placing a plurality of semiconductor devices in a carrier assembly and performing at least one testing operation on the plurality of semiconductor devices while they remain inside the carder assembly.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARELL W PAXTON whose telephone number is (571)272-0521. The examiner can normally be reached Monday-Friday 8:00 am - 5:00 pm.
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/JARELL W PAXTON/Examiner, Art Unit 2858
/EMAN A ALKAFAWI/Supervisory Patent Examiner, Art Unit 2858
3/30/2026