Prosecution Insights
Last updated: May 29, 2026
Application No. 18/633,257

TIMING BASED SIGNAL VALLEY DETECTION

Final Rejection §102
Filed
Apr 11, 2024
Examiner
POOS, JOHN W
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Silicon Laboratories Inc.
OA Round
2 (Final)
94%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allowance Rate
1291 granted / 1381 resolved
+25.5% vs TC avg
Minimal +5% lift
Without
With
+4.6%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 10m
Avg Prosecution
27 currently pending
Career history
1406
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
39.9%
-0.1% vs TC avg
§102
50.7%
+10.7% vs TC avg
§112
1.0%
-39.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1381 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments with respect to claim(s) 1-6, 11, 14-15, and 19-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 9-10, and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li et al. (CN 114205952). In regard to Claim 1: Li discloses, in Figure 3, a method for controlling a switch (MOSFET of 302) comprising: generating a timestamp (Figure 4: 104 output, where 104 is part of 3062) corresponding to an estimated occurrence of a local minimum in a sensed voltage (valley bottom detection; Translation Page 2, Paragraph 2) during a first interval of a first switching cycle of a switching control signal (3064 output) based on comparison (3067) of the sensed voltage (Vcomp of 3065) to a reference voltage (Vcs of 3066) and based on a count value of a counter (Figure 7: 1041, where 1041 is part of 104); and starting a second interval (Translation Page 5, Paragraph 9) of a subsequent switching cycle of the switching control signal (3064 output) based on the timestamp (Figure 4: 104 output, where 104 is part of 3062). In regard to Claim 9: Li discloses, in Figure 3, an integrated circuit product comprising: valley detection logic (3062, 3068, 3069) configured to generate a timestamp (Figure 4: 104 output, where 104 is part of 3062) corresponding to an estimated occurrence of a local minimum in a sensed voltage (valley bottom detection; Translation Page 2, Paragraph 2) during a first interval of a first switching cycle of a switching control signal (3064 output) based on comparison (3067) of the sensed voltage (Vcomp of 3065) to a reference voltage (Vcs of 3066) and based on a count value of a first counter (Figure 7: 1041, where 1041 is a part of 104); and control logic (3064) configured to generate the switching control signal (3064 output) having an adjustable pulse width (Translation Page 5, Paragraph 11 and Page 6, Paragraph 1), the adjustable pulse width being based on the timestamp (Figure 4: 104 output, where 104 is part of 3062). In regard to Claim 10: Li discloses, in Figure 3, the integrated circuit product as recited in claim 9 further comprising: a comparator (3067) configured to generate a comparison signal (3067 output) based on the reference voltage (Vcs of 3066) and the sensed voltage (Vcomp of 3065). In regard to Claim 15: Li discloses, in Figure 3, a method for calibrating a duty cycle of a switching control signal, the method comprising: modulating a pulse width (Translation Page 5, Paragraph 11 and Page 6, Paragraph 1) of a control signal (3064 output) at a time based on a timestamp (Figure 4: 104 output, where 104 is part of 3062) corresponding to an estimated time of occurrence of a valley (valley bottom detection; Translation Page 2, Paragraph 2) in a resonant ringing of a sensed voltage (Vcomp of 3065) and a count value of a counter (Figure 7: 1041) started in response to the sensed voltage (Vcomp of 3065) crossing a threshold voltage in a first direction (Translation Page 2, Paragraph 2), the timestamp being generated based on a second count value of a second counter (Figure 7: 1042). Allowable Subject Matter Claims 2-8, 11-14, and 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to John W Poos whose telephone number is (571)270-5077. The examiner can normally be reached M-Th 8-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JOHN W POOS/Primary Examiner, Art Unit 2896
Read full office action

Prosecution Timeline

Apr 11, 2024
Application Filed
Nov 14, 2025
Non-Final Rejection mailed — §102
Feb 12, 2026
Response Filed
Apr 08, 2026
Final Rejection mailed — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
94%
Grant Probability
98%
With Interview (+4.6%)
1y 10m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1381 resolved cases by this examiner. Grant probability derived from career allowance rate.

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