DETAILED ACTION
Notice of Pre-AIA or AIA Status
Applicant’s amendment, filed 03/04/2026, for application number 18/633,397 has been received and entered into record. Claims 1-4, 6-19 are amended. Thus, claims 1-22 are presented for examination.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6, 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi et al. (US 2017/0315956 A1).
Regarding claim 1, Choi teaches a device in communication with a host device via an interface (Figure 1, PCIe system 50 and PCIe interface 300), comprising:
a clock signal generator configured to generate a first reference clock signal to be used by the device (“a clock signal generator configured to generate a second reference clock signal,” par 0006 and “The second clock signal generator 205 generates a second reference clock signal REFCLK_AIC.” Par 0034 and Figure 1, clock generators 105 and 205) [the “second reference clock signal” corresponds to the first reference clock signal]; and
a reference clock signal selection circuit (Figure 2, clock selection circuit 280A) coupled to be in communication with the clock signal generator to receive the first reference clock signal (“both the first reference clock signal REFCLK_MB and the second reference clock signal REFCLK_AIC may be supplied to the selection circuit 280A,” par 0068 and Figure 2) [selection circuit 280A is connected to CLK gen #2 205, see Figure 2] and configured to receive a second reference clock signal from the host device (Figures 1 and 2, CLK gen #1 105 (contained in motherboard/host device) produces REFCLK_MB (second reference clock signal) and provides it to physical layer 250, containing the selection circuit, through interface 300), and configured to, in response to a first reset signal received first among a plurality of reset signals from the host device, select one of the first reference clock signal and the second reference clock signal according to whether the second reference clock signal is provided from the host device (“When a reset signal PERST_N transits from a low level to a high level, it is assumed in FIGS. 4 and 5 that the reset of the PCIe device 200 is released and/or reset.” Par 0070 and “ The physical layer 250A may automatically detect whether the first reference clock signal REFCLK_MB is supplied from the PCIe host 100 or another source, and select one of the first reference clock signal REFCLK_MB and the second reference clock signal REFCLK_AIC as a reference clock signal REFCLK according to, or based on, a result of the detection.” Par 0034 and “The selector 285 may transmit one of the first reference clock signal REFCLK_MB and the second reference clock signal REFCLK_AIC to the clock gating circuit 287 in response to and/or based on the clock selection signal CLK_SEL.” Par 0050 and paragraphs 6, 18, 19 and Figures 1-4) [signal REFCLK_MB corresponds to the second reference clock signal; the REFCLK_AIC corresponds to the first reference clock signal; the selector circuit chooses between the signals based on whether the host’s clock signal REFCLK_MB is supplied; Figure 4, the selection (CLK_SEL) occurs when the PERST_N (reset signal) is enabled], wherein the reference clock signal selection circuit includes a selection circuit controller configured to: upon receiving a different reset signal other than the first reset signal, block an operation caused by the different reset signal until the one of the first and second reference clock signals is selected and the initial register values of the physical layer is set (“The clock gating circuit 287 may gate and/or block a supply of the reference clock signal REFCLK to the PLL circuit 262 before the reference clock signal is selected by the selector 285. Accordingly, a supply of an unstable and/or unwanted reference clock signal REFCLK to the PLL circuit 262 is prevented.” Par 0051 and “When a reset signal PERST_N transits from a low level to a high level, it is assumed in FIGS. 4 and 5 that the reset of the PCIe device 200 is released and/or reset.” Par 0070 and Figure 2) [the clock gating circuit is a component within the reference clock selection circuit; operation is blocked until one of the reference clock signals is selected; under BRI, this process also includes setting initial register values of the physical layer].
Regarding claim 2, Choi teaches the device of claim 1, wherein the first reset signal is a reset signal that is received first from the host device after a reference clock signal is selected before the one of the first and second reference clock signals is selected by the reference clock signal selection circuit (“the physical layer 250A may also receive a reset signal PERST_N that indicates that the PCIe device 200 is to be reset, according to at least one example embodiment.” Par 0053 and “At a first time T1, a reset of the PCIe device 200 is released (e.g., the PCIe device 200 is reset). When a reset signal PERST_N transits from a low level to a high level, it is assumed in FIGS. 4 and 5 that the reset of the PCIe device 200 is released and/or reset.” Par 0070 and “When the reset of the PCIe device 200 is released, the first counter 281A and the second counter 282A may perform a count operation starting at the first time T1.” Par 0071 and Figure 4 and 5).
Regarding claim 3, Choi teaches the device of claim 2, wherein the selection circuit controller is further configured to generate a control signal to select the one of the first and second reference clock signals in response to the first reset signal and a physical layer initialization signal (“the comparator 283A may be a programmable processing device, such as a processor, a CPU, an ASIC, etc., that is configured to generate the clock selection signal CLK_SEL based on the results of a comparison of a plurality of count values associated with a plurality of respective clock signals (e.g., REFCLK_MB_CNT, REFCLK_AIC_CNT, etc.).” par 0044 and “Additionally, the physical layer 250A may also receive a reset signal PERST_N that indicates that the PCIe device 200 is to be reset,” par 0053 and “the comparison time period may be a time period after a certain (e.g., desired) period of time elapses from a reset of the PCIe device 200,” par 0047) [the comparator corresponds to the selection circuit controller; the physical layer receives a reset signal, and this reset initializes and times comparison process and subsequent reference clock selection].
Regarding claim 4, Choi teaches the device of claim 3, wherein the physical layer initialization signal is enabled until the one of the first and second reference clock signals is selected and the initial register values of the physical layer are set (“The clock gating circuit 287 may gate and/or block a supply of the reference clock signal REFCLK to the PLL circuit 262 before the reference clock signal is selected by the selector 285.” Par 0051 and “The CPU 284B of the PCIe device 200 may write the indication data IND to the register 282B in response to the write command” par 0060) [the clock gating circuit corresponds to the physical layer; this is effectively enabled (by actively blocking) to prevent unstable signals until reference clock is selected].
Regarding claim 6, Choi teaches the device of claim 3, further comprising a reference clock signal detector configured to detect the second reference clock signal (“The second counter 282A may receive the second reference clock signal REFCLK_AIC generated from the second clock signal generator 205 of the PCIe device 200 (e.g., an internal reference clock generator, a device reference clock generator, etc.),” par 0043) [the second counter corresponds to the detector].
Regarding claim 7, Choi teaches the device of claim 6, wherein the reference clock signal selection circuit further comprises:
a detection signal generator configured to generate a detection signal upon detecting the second reference clock signal in response to the control signal (“the comparator 283A may be a programmable processing device, such as a processor, a CPU, an ASIC, etc., that is configured to generate the clock selection signal CLK_SEL based on the results of a comparison of a plurality of count values associated with a plurality of respective clock signals (e.g., REFCLK_MB_CNT, REFCLK_AIC_CNT, etc.).” par 0044);
a first counter configured to: determine a number of toggles of the first reference clock signal; and generate a first count value corresponding to the number of toggles of the first reference clock signal in response to the control signal (“the first counter 281A may receive the first reference clock signal REFCLK_MB transmitted from the PCIe host 100, count the number of toggles (or oscillations) of the first reference clock signal REFCLK_MB, and generate a first count value REFCLK_MB_CNT.” Par 0042 and “When a reset signal PERST_N transits from a low level to a high level… the first counter 281A and the second counter 282A may perform a count operation starting at the first time T1.” Par 0070-0071);
a second counter configured to: determine a number of toggles for the second reference clock signal; and generate a second count value corresponding to the number of toggles of the second reference clock signal in response to the control signal (“The second counter 282A may receive the second reference clock signal REFCLK_AIC generated from the second clock signal generator 205 of the PCIe device 200 (e.g., an internal reference clock generator, a device reference clock generator, etc.), count the number of toggles (or oscillations) of the second reference clock signal REFCLK_AIC, and generate a second count value REFCLK_AIC_CNT.” Par 0043 and “When a reset signal PERST_N transits from a low level to a high level… the first counter 281A and the second counter 282A may perform a count operation starting at the first time T1.” Par 0070-0071);
a reference clock signal comparator configured to compare the first count value with the second count value (“The comparator 283A may be a logic gate that compares the first count value REFCLK_MB_CNT with the second count value REFCLK_AIC_CNT, generates a clock selection signal CLK_SEL according to a result of the comparison based on desired criteria, and outputs the clock selection signal CLK_SEL to the selector 285.” Par 0044); and
a reference clock signal selector configured to select the one of the first and second reference clock signals based on the detection signal and a comparison result of the reference clock signal comparator (“The selector 285 may transmit one of the first reference clock signal REFCLK_MB and the second reference clock signal REFCLK_AIC to the clock gating circuit 287 in response to and/or based on the clock selection signal CLK_SEL.” Par 0050 and “The comparator 283A may be a logic gate that compares the first count value REFCLK_MB_CNT with the second count value REFCLK_AIC_CNT, generates a clock selection signal CLK_SEL according to a result of the comparison based on desired criteria, and outputs the clock selection signal CLK_SEL to the selector 285.” Par 0044).
Claims 8-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 2015/0131766 A1).
Regarding claim 8, Chen teaches a device in communication with a host device via an interface (Figure 1 and 4), comprising:
a receiver configured to receive a data set and a skip ordered set (SKP OS) from the host device based on a first reference clock signal (“The PLL 110 receives a radio frequency (RF) signal SIG from an external apparatus… The PLL 110 locks a phase and/or a frequency of the RF signal SIG to generate a recovery clock signal RCLK and received data DAT.” par 0020 and “the value X and the first timing value can also be applied to calculate a longest time of inserting an SKP ordered set.” Par 0046) [the PLL corresponds to the receiver that extracts data and reference clocking information (RF signal) from an external device while managing the timing for skip ordered sets; the RCLK corresponds to the first reference clock signal];
an elastic buffer coupled to the receiver and configured to store the data set and the skip ordered set (“The data buffer unit 130 writes the received data DAT into the position of a write-in address WR_ADD in an elastic buffer of the data buffer unit 130 according to a frequency of the recovery clock signal RCLK,” par 0020 and “the value X and the first timing value can also be applied to calculate a longest time of inserting an SKP ordered set.” Par 0046) [the elastic buffer is coupled to the PLL 110, see Figure 1];
a buffer state detector coupled to the elastic buffer and configured to detect a state of the elastic buffer (“The control unit 140 can determine whether the elastic buffer 132 is full/ empty according to whether the overflow signal or the underflow signal is received form the elastic buffer 132.” Par 0045); and
a spread spectrum clocking selection circuit coupled to the receiver (Figure 1, control unit 150 is coupled to PLL 110) and configured to determine whether to activate spread spectrum clocking (SSC) based on a comparison between a number of times the first reference clock signal is toggled while the skip ordered set is continuously received and a first reference value, and a state of the elastic buffer (“Referring to FIG. 4 and FIG. 6, in step S601, the control unit 140 first determines whether the RF signal SIG is received.” Par 0044 and “the RF signal SIG can be a spread spectrum clock (SSC) signal. The SSC signal has a SSC period.” Par 0043 and “ in step S603, the control unit 140 determines whether the elastic buffer 132 is full/empty, or whether the first timing value is greater than the value X [reference value].” par 0045 and “the value X and the first timing value can also be applied to calculate a longest time of inserting an SKP ordered set.” Par 0046 and paragraphs 27-32) [the control unit compares the recovery clock’s period count (toggles) against a reference value (X) and the buffer’s state to determine frequency adjustments for SSC signals and calculate skip ordered set timing].
Regarding claim 9, Chen teaches the device of claim 8, wherein the spread spectrum clocking selection circuit comprises:
a skip ordered set detector (control unit 140, Figure 1) configured to detect the skip ordered set received through the receiver (“the value X and the first timing value can also be applied to calculate a longest time of inserting an SKP ordered set.” Par 0046 and Figures 1, 4 and 5);
a skip ordered set counter configured to: determine a number of toggles of the first reference clock signal while the skip ordered set is received (“The timer in the control unit 140 can accumulate a first timing value … for counting the number of periods of the recovery clock signal RLCK.” Par 0044) [the device’s internal timer corresponds to the counter]; and generate a count value corresponding to the number of toggles of the first reference clock signal during a receiving interval of the skip ordered set (“The timer in the control unit 140 can accumulate a first timing value,… The control unit 140 can check whether the first timing value reaches a value X, ” par 0044) [the timing value is the generated count that represents the accumulation of clock toggles used to measure the interval against the reference value];
a skip ordered set comparator configured to compare the count value with a predetermined reference value (“in step S605, the control unit 140 determines whether the first timing value is smaller than the value X,” par 0047 and “the value X and the first timing value can also be applied to calculate a longest time of inserting an SKP ordered set.” Par 0046); and
a mode selector configured to select, based on a comparison result of the skip ordered set comparator and a state of the elastic buffer, one of a first mode and a second mode, wherein in the first mode, the spread spectrum clocking is activated, and in the second mode, the spread spectrum clocking is deactivated (“When the control unit 140 determines that the first timing value is smaller than the value X in the step S605, and the elastic buffer 132 is full, the control unit 140 … increase the frequency of the local clock signal LCLK” par 0047 and “When the control unit 140 determines that the first timing value is smaller than the value X, and determines that the elastic buffer 132 is empty in the step S608, the control unit 140 … decrease the frequency of the local clock signal LCLK” par 0048 and “After the control unit 140 confirms that the elastic buffer 132 does not have the situation of overflow or underflow (full/empty) in the several SSC periods, the control unit 140 … maintains the frequency of the local clock signal LCLK.” Par 0050).
Regarding claim 10, Chen teaches the device of claim 9, wherein the skip ordered set comparator is configured to: output a signal corresponding to the first mode upon determination that the count value is less than a first reference value (“When the control unit 140 determines that the first timing value is smaller than the value X in the step S605, the control unit 140 executes a step S606 to add the digital value in the control signal CS by 1,” par 0047 and “When the control unit 140 determines that the first timing value is smaller than the value X, and determines that the elastic buffer 132 is empty in the step S608, the control unit 140 executes a step S609 to decrease the digital value in the control signal CS by 1,” par 0048); or output a signal corresponding to the second mode upon determination that the count value is greater than a second reference value that is greater than the first reference value (“If the determination result of the step S610 is affirmative, i.e. the current second timing value of the second timer reaches the SSC period, the control unit 140 maintains the setting of the digital value in the control signal CS,” par 0049 and “After the control unit 140 confirms that the elastic buffer 132 does not have the situation of overflow or underflow (full/empty) in the several SSC periods, the control unit 140 maintains the digital value in the control signal CS, and maintains the frequency of the local clock signal LCLK.” Par 0050).
Regarding claim 11, Chen teaches the device of claim 10, wherein the mode selector receives the signal corresponding to the first mode and selects the first mode in a case that the elastic buffer is in an underflow state (“When the control unit 140 determines that the first timing value is smaller than the value X, and determines that the elastic buffer 132 is empty [underflow] in the step S608, the control unit 140 executes a step S609 to decrease the digital value in the control signal CS by 1, so as to decrease the frequency of the local clock signal LCLK generated by the local clock generator 120.” Par 0048) [the control unit (mode selector) triggers frequency adjustment when the count is less than X and the buffer is empty].
Regarding claim 12, Chen teaches the device of claim 10, wherein the mode selector receives the signal corresponding to the second mode from the skip ordered set comparator, or selects the second mode in a case that the elastic buffers is not in an underflow state (“In the step S608, the control unit 140 … determines whether the elastic buffer 132 is empty. When the determination result of the step S608 is negative, the control unit 140 executes a step S610.” Par 0048 and “If the determination result of the step S610 is affirmative, i.e. the current second timing value of the second timer reaches the SSC period, the control unit 140 maintains the setting of the digital value in the control signal CS,” par 0049 and “After the control unit 140 confirms that the elastic buffer 132 does not have the situation of overflow or underflow (full/empty) in the several SSC periods, the control unit 140 maintains the digital value in the control signal CS, and maintains the frequency of the local clock signal LCLK.” Par 0050) [the control unit maintains the clock frequency (second mode) when timing count reaches required period reference or when the buffer is not empty (not underflow state)].
Regarding claim 13, Chen teaches the device of claim 8, further comprising a clock signal generator configured to generate the first reference clock signal (“The voltage-controlled oscillator 113 generates … the frequency of the recovery clock signal RCLK” par 0036).
Regarding claim 14, Chen teaches the device of claim 13, wherein the first reference clock signal is different from a second reference clock signal generated by the host device (“The local clock generator 120 generates a local clock signal LCLK,” par 0020) [the first reference clock signal, RCLK, is different from the second reference clock signal, LCLK].
Regarding claim 15, Chen teaches the device of claim 8, further comprising a reference clock signal generator configured to generate a target reference clock signal having a spread spectrum from the first reference clock signal upon activation of the spread spectrum clocking (“The local clock generator 120 generates a local clock signal LCLK, and determines a frequency of the local clock signal LCLK under control of a control signal CS.” Par 0020 and “the frequency of the local clock signal is correspondingly adjusted according to the relationship, such that the local clock signal is synchronized to the clock signal of a receiver circuit.” Par 0011).
Regarding claim 16, Chen teaches a method of operating an interface device in communication with a host device, comprising:
generating a first reference clock signal (“The local clock generator 120 generates a local clock signal LCLK, and determines a frequency of the local clock signal LCLK under control of a control signal CS.” Par 0020);
selecting one of a common clock mode and a separate clock mode based on a comparison between the first reference clock signal generated by the interface device and a second clock signal received from the host device (“The logic control unit 1143 compares the contents of the sampling data SD1 and SD2 to determine a relationship between the frequency of the recovery clock signal RCLK and the frequency of the RF signal SIG, and generates and adjusts the frequency difference signal FD according to the relationship between the frequencies of the recovery clock signal RCLK and the RF signal SIG.” par 0038 and paragraphs 26-29 and Figure 3) [the device maintains frequency when signals are rather close, see paragraph 26, (common clock mode) or adjusts the frequency to compensate for a frequency difference, see paragraphs 27-29, (separate clock mode)];
receiving a data set and a skip ordered set (SKP OS) from the host device based on the first reference clock signal according to the separate clock mode (“The PLL 110 receives a radio frequency (RF) signal SIG from an external apparatus…to generate a recovery clock signal RCLK and received data DAT.” par 0020 and “the value X and the first timing value can also be applied to calculate a longest time of inserting an SKP ordered set.” Par 0046);
storing the data set and the skip ordered set in an elastic buffer (“The data buffer unit 130 writes the received data DAT into the position of a write-in address WR_ADD in an elastic buffer of the data buffer unit 130 according to a frequency of the recovery clock signal RCLK,” par 0020 and “the value X and the first timing value can also be applied to calculate a longest time of inserting an SKP ordered set.” Par 0046); and
determining whether to apply spread spectrum clocking (SSC) to the first reference clock signal based on a comparison between a number of times the first reference clock signal is toggled while the skip ordered set is continuously received and a first reference value, and a state of the elastic buffer (“The control unit 140 can determine whether the elastic buffer 132 is full/ empty according to whether the overflow signal or the underflow signal is received form the elastic buffer 132.” Par 0045 and “the first timing value … counting the number of periods of the recovery clock signal RLCK.” Par 0044 and “ the RF signal SIG can be a spread spectrum clock (SSC) signal.” Par 0043 and “the value X and the first timing value can also be applied to calculate a longest time of inserting an SKP ordered set.” Par 0046) [the control unit decides whether to adjust the frequency (activate SSC) by comparing the number of toggles (first timing value) of the reference clock against a reference value (X) while simultaneously monitoring the buffer’s state and calculating the SKP ordered set timing].
Regarding claim 17, Chen teaches the method of claim 16, wherein the selecting the one of the common clock mode and the separate clock mode is performed in response to an initial toggling of a reset signal received from the host device (“in step S601, the control unit 140 first determines whether the RF signal SIG is received… The control unit 140 resets a timer (a first timer) in the step S602” Par 0044 and “the calibration mode can be used when the electronic apparatus initiates the transmission interface,” par 0051 and paragraphs 26-29).
Regarding claim 18, Chen teaches the method of claim 16, wherein the determining whether to apply the spread spectrum clocking comprises:
comparing a receiving interval of the skip ordered set with a predetermined first interval (“The control unit 140 can check whether the first timing value reaches a value X,” par 0044 and “the value X and the first timing value can also be applied to calculate a longest time of inserting an SKP ordered set.” Par 0046);
detecting the state of the elastic buffer in response to the receiving interval shorter than the predetermined first interval (“In the step S608, the control unit 140 determines whether the first timing value is smaller than the value X, and determines whether the elastic buffer 132 is empty.” Par 0048); and
activating application of the spread spectrum clocking in response to detection of an underflow state of the elastic buffer (“When the control unit 140 determines that the first timing value is smaller than the value X, and determines that the elastic buffer 132 is empty in the step S608, the control unit 140 … decrease the frequency” par 0048 and “frequency of the local clock signal is correspondingly adjusted according to the relationship, such that the local clock signal is synchronized to the clock signal of a receiver circuit.” Par 0011) [the receiving interval of the SKP set (first timing value) compares it to the predetermined interval (value X) and triggers frequency synchronization (activating SSC logic) when it detects empty buffer (underflow)].
Regarding claim 19, Chen teaches the method of claim 16, wherein the determining whether to apply the spread spectrum clocking comprises:
comparing a receiving interval of the skip ordered set with a predetermined second interval (“The control unit 140 can check whether the first timing value reaches a value X,” par 0044 and “the value X and the first timing value can also be applied to calculate a longest time of inserting an SKP ordered set.” Par 0046); and
deactivating application of the spread spectrum clocking in response to the receiving interval longer than the predetermined second interval (“in step S603, the control unit 140 determines whether the elastic buffer 132 is full/empty, or whether the first timing value is greater than the value X.” par 0045 and “the control unit 140 maintains the setting of the digital value in the control signal CS,… If the determination result of the step S610 is affirmative, i.e. the current second timing value of the second timer reaches the SSC period, the control unit 140 maintains the setting of the digital value in the control signal CS,” par 0049 and “the control unit 140 maintains the digital value in the control signal CS, and maintains the frequency of the local clock signal LCLK.” Par 0050 and paragraphs 26-29) [the device compares the receiving interval of the SKP set against the reference and deactivates frequency adjustments when the interval is longer or once the measurement reaches the full duration of the SSC period].
Response to Arguments
Applicant's arguments filed 03/04/2026 regarding claim 1 have been fully considered but they are not persuasive.
Regarding claim 1, Applicant argues that Choi does not teach “block an operation caused by a reset signal.” Examiner respectfully disagrees. The clock gating circuit blocks the supply of the reference clock signal to the transceiver and PLL (thus preventing any further operations) until a selection is finalized following the reset signal’s release. See paragraphs 51 and 65.
Applicant argues that Choi does not distinguish among multiple reset signals received from a host device. Examiner respectfully disagrees. Choi discloses a reset and the T1-T3 timing sequence which describes a response that applies to any reset event within a series. So, Choi maps to a plurality of reset signals by specifying that the physical layer handles initialization and maintenance (covering both initial and subsequent resets), which encompasses any first or different reset event. See paragraphs 29, 47 and 51 and Figures 4 and 5.
Applicant also argues that Choi does not disclose the timing feature of “until the one of the first and second reference clock signals is selected and initial register values of the physical layer are set.” Examiner respectfully disagrees. Choi does describe a clock gating circuit blocking the clock signal throughout the initialization period until selection is finalized at time T3, which occurs after configuration data (i.e. clock selection indicator) is present in the physical layer. See paragraph 51.
Regarding claim 8, Applicant argues that Park does not teach “the reference clock signal selection circuit includes a selection circuit controller configured to, upon receiving a different reset signal other than the first reset signal, block an operation caused by the different reset signal until the one of the first and second reference clock signals is selected and initial register values of a physical layer are set.” However, this limitation is not recited in the amended claim 8. Examiner is unsure of the arguments regarding this limitation in claim 8.
However, Applicant’s arguments with respect to claim(s) 8 and 16 amended limitation (comparison of the first reference signal toggle value and first reference value) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
No additional arguments were presented as to the remaining claims. As such, the rejection is maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/AYMAN FATIMA/Examiner, Art Unit 2176
/JAWEED A ABBASZADEH/Supervisory Patent Examiner, Art Unit 2176