DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a response to the election/restriction filed 12/23/2025. Claims 1-5 and 7-10 are pending and are under examination. Claims 11-20 have been canceled.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-5 and 7-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 1, the recitation of “the output signals” (line 12) is indefinite because it is incorrect. Since, a phase selecting circuit, configured to select one of the candidate clock signals be the output signal, thus, “the output signals” should be “an output signal”. Paragraph 0018 states “The decoder 209 turns on at least one of the switches SW_1, SW_2, SW_3, SW_4 and SW_5 according to a control code CC to select at least one of the candidate clock signals CLK_C1...CLK_CN as the output clock signal ”. Thus, Since, the metes and bounds of the claim cannot be determined renders the claim indefinite.
Claims 2-5 and 7-10 are indefinite because of the technical deficiencies of claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 and 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Araki et al. (US 2004/0257124) in view of Doris et al. (USP 9,287,135).
Regarding claim 1, Araki et al.’s figure 7 shows A multi-phase clock signal generating circuit, configured to generate a plurality of output clock signals with different phases, comprising: a charge pump (33), configured to generate a control voltage according to a reference clock signal (CLKI) and a target clock signal (an input supplied to frequency divider 36); a delay circuit (35), comprising a delay chain with a plurality of delay units (42; figure 8), configured to generate a plurality of candidate clock signals (CLKV1 to CLKV5) and the target clock signal according to the control voltage; and a phase selecting circuit (23), configured to select one of the candidate clock signals as the output signals (this construes to be at least one of the candidate clock signals selected as the output signal as noted in under the 35 USC 112, second paragraph above), the delay units respectively comprises a plurality of inverters (42; figure 8).
Araki et al. does not disclose each inverter comprising at least one FinFEt.
Doris et al. teaches that FinFET has advantages over bulk metal oxide semiconductor FET (MOSFET) in the aspects of: reduced leakage, excellent sub-threshold slop, and better voltage gain without degradation of noise or linearity. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to have Araki et al.’s delay unit comprise FinFET transistors for the purpose of reducing leakage as taught by Doris et al. reference.
Regarding claim 2, the delay circuit further comprises: a voltage to current circuit (44, 41; figure 8), configured to receive the control voltage (Vc) to generate a plurality of control currents to the delay units.
Regarding claim 4, a frequency divider (36), configured to receive the target clock signal to generate a frequency-divided signal; and a phase frequency detector (32), configured to control the charge pump according to the frequency-divided signal and the reference clock signal.
Regarding claim 5, wherein the inverters are single end inverters (42).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Araki et al. (US 2004/0257124), Doris et al. (USP 9,287,135) and further in view of Bell et al. (USP 10,756,710).
Regarding claim 3, the combination of Araki et al. and Doris et al. shows a multi-phase clock signal generating circuit comprising all the aspects of the present invention as noted above except a NAND gate, comprising: a first input terminal, configured to receive an enable signal; a second input terminal, coupled to an output terminal of a last one of the delay units; and an output terminal coupled to an input terminal of a first one of the delay units as called for in claim 3.
Bell et al.’s figure 7 shows except a NAND gate (705), comprising: a first input terminal, configured to receive an enable signal (Enable); a second input terminal, coupled to an output terminal of a last one of the delay units; and an output terminal coupled to an input terminal of a first one of the delay units. This configuration is to enable/disable the delay units to a predetermined state, thus, to control its operation with a known state. Thus, it would have been obvious to person skilled in the art before the effective filing date of the invention to have Bell et al.’s NAND gate in Araki et al.’s circuit arrangement for the purpose of enabling/disabling the delay units to a predetermined state, thus, to control its operation with a known state as taught by Bell et al. reference.
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Araki et al. (US 2004/0257124) and Doris et al. (USP 9,287,135) and further in view of Finn (USP 10,505,542).
Regarding claims 7-8, Araki et al.’s figures 7-8 shows a multi-phase clock signal generating circuit comprising all the aspects of the present invention as noted above except wherein the delay units are differential/pseudo differential delay units as called for in claims 7-8. However, Finn teaches that differential signaling offers better noise immunity thus is suitable for higher speeds (see column 4, lines 11-26). Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to have Araki et al.’s delay units being differential delay units for the purpose of less susceptible to noise and obtaining a higher speed as taught by Finn. Therefore, outside of any non-obvious results, the obviousness of using differential signaling to obtain higher speed will not be patentable under 35USc 103.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Araki et al. (US 2004/0257124) and Doris et al. (USP 9,287,135) and further in view of Sekerli et al. (US 2022/0253082).
Regarding claim 9, the combination of Araki et al. and Doris et al. references shows a multi-phase clock signal generating circuit comprising all the aspects of the present invention as noted above except a LDO (Low-dropout regulator), configured to provide power to the charge pump, the delay chain and the phase selecting circuit as called for in claim 9.
Sekerli et al. teaches that LDO is low noise power supply regulator (see paragraph 0002). Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to have used LDO regulator in Araki et al.’s circuit arrangement for the purpose of less susceptible to noise as taught by Sekerli et al. reference.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Araki et al. (US 2004/0257124) and Doris et al. (USP 9,287,135) and further in view of Yu et al. (US 2020/0366535).
Regarding claim 10, the combination of Araki et al. and Doris et al. references shows a multi-phase clock signal generating circuit comprising all the aspects of the present invention as noted above except a self-bias buffer, configured to buffer the output clock signals.as called for in claim 10.
Yu et al.’s figure 12 shows the usage of self-biasing buffers 1210 and 1215 to buffer an output signal. Furthermore, self-biasing buffer is known to offer a simplified design, reduced component count, and improved performance stability against variations in temperature and device characteristics. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to include Yu et al.’s self-biasing buffer in Araki et al.’s circuit arrangement for the purpose of providing a stable output clock signals against variations in temperature and device characteristics.
Response to Arguments
Applicant's arguments filed 12/23/2025 have been fully considered but they are not persuasive. Applicant argues that Doris’s FinFet advantages different from the FinFet of the present invention found not persuasive. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., FinFET is a three-dimensional transistor that can improve circuit control and reduce
leakage current, shorten the gate length of the transistor, have higher saturation currents and transduction, and lower parasitic capacitance) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Furthermore, applicant's argument based on the fact that the inventor has recognized another advantage which would flow naturally from following the suggestion of the prior art cannot be the basis for patentability when the differences would otherwise be obvious. See Ex parte Obiaya, 227 USPQ 58, 60 (Bd. Pat. App. & Inter. 1985). In this instant, the alleged benefits of using FinFET “can improve circuit control and reduce leakage current, shorten the gate length of the transistor, have higher saturation currents and transduction, and lower parasitic capacitance” would have been inherently present in the combined references. Thus, the rejection is deemed proper. Claims 1-5 and 7-10 remain rejected.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN THIEU LAM whose telephone number is (571)272-1744. The examiner can normally be reached Monday-Friday, 8:30 am to 5:00 pm.
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/TUAN T LAM/Primary Examiner, Art Unit 2842 2/12/2026