DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a response to the amendment filed 5/5/2026. Claims 1-2, 5 and 7-10 are pending and are under examination. Claims 11-20 have been canceled.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Araki et al. (US 2004/0257124) in view of Suzuki (USP 7,151,417).
Regarding claim 1, Araki et al.’s figure 7 shows A multi-phase clock signal generating circuit, configured to generate a plurality of output clock signals with different phases, comprising: a charge pump (33), configured to generate a control voltage according to a reference clock signal (CLKI) and a target clock signal (an input signal supplied to frequency divider 36 from the delay circuit 35); a delay circuit (35), comprising a delay chain with a plurality of delay units (42; figure 8), configured to generate a plurality of candidate clock signals (CLKV1 to CLKV5) and the target clock signal according to the control voltage; and a phase selecting circuit (23), configured to select one of the candidate clock signals as an output signal; wherein the multi-phase clock signal generating circuit further comprises: a frequency divider (36), configured to receive the target clock signal to generate a frequency-divided signal (CLKC); and a phase frequency detector (32), configured to control the charge pump according to the frequency-divided signal and a reference clock signal (CLKI).
Araki et al. does not show a NAND gate, comprising: a first input terminal, configured to receive an enable signal; a second input terminal, coupled to receive an output of a last one of the delay units; and an output terminal, coupled to an input terminal of a first one of the delay units; and an inverter, coupled to the output terminal of the NAND gate, configured to output the target clock signal to the frequency divider as called for in claim 1.
Suzuki’s figure 3 shows a NAND gate (370), comprising: a first input terminal, configured to receive an enable signal (EN); a second input terminal, coupled to an output terminal of a last one of the delay units (325); and an output terminal coupled to an input terminal of a first one of the delay units (310) and an inverter (330) coupled to the output of the NAND gate. This configuration is to enable/disable the delay units to a predetermined state, thus, to control its operation with a known state. Thus, it would have been obvious to person skilled in the art before the effective filing date of the invention to have Suzuki’s NAND gate and inverter (330) in Araki et al.’s circuit arrangement for the purpose of enabling/disabling the delay units to a predetermined state, thus, to control its operation with a known state as taught by Suzuki reference.
Regarding claim 2, the delay circuit further comprises: a voltage to current circuit (44, 41; figure 8), configured to receive the control voltage (Vc) to generate a plurality of control currents to the delay units.
Regarding claim 5, wherein the inverters are single end inverters (42).
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Araki et al. (US 2004/0257124) and Suzuki (USP 7,151,417) and further in view of Finn (USP 10,505,542).
Regarding claims 7-8, Araki et al.’s figures 7-8 shows a multi-phase clock signal generating circuit comprising all the aspects of the present invention as noted above except wherein the delay units are differential/pseudo differential delay units as called for in claims 7-8. However, Finn teaches that differential signaling offers better noise immunity thus is suitable for higher speeds (see column 4, lines 11-26). Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to have Araki et al.’s delay units being differential delay units for the purpose of less susceptible to noise and obtaining a higher speed as taught by Finn. Therefore, outside of any non-obvious results, the obviousness of using differential signaling to obtain higher speed will not be patentable under 35USc 103.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Araki et al. (US 2004/0257124) and Suzuki (USP 7,151,417) and further in view of Sekerli et al. (US 2022/0253082).
Regarding claim 9, the combination of Araki et al. and Suzuki references shows a multi-phase clock signal generating circuit comprising all the aspects of the present invention as noted above except a LDO (Low-dropout regulator), configured to provide power to the charge pump, the delay chain and the phase selecting circuit as called for in claim 9.
Sekerli et al. teaches that LDO is low noise power supply regulator (see paragraph 0002). Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to have used LDO regulator in Araki et al.’s circuit arrangement for the purpose of less susceptible to noise as taught by Sekerli et al. reference.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Araki et al. (US 2004/0257124) and Suzuki (USP 7,151,417) and further in view of Yu et al. (US 2020/0366535).
Regarding claim 10, the combination of Araki et al. and Suzuki references shows a multi-phase clock signal generating circuit comprising all the aspects of the present invention as noted above except a self-bias buffer, configured to buffer the output clock signals.as called for in claim 10.
Yu et al.’s figure 12 shows the usage of self-biasing buffers 1210 and 1215 to buffer an output signal. Furthermore, self-biasing buffer is known to offer a simplified design, reduced component count, and improved performance stability against variations in temperature and device characteristics. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to include Yu et al.’s self-biasing buffer in Araki et al.’s circuit arrangement for the purpose of providing a stable output clock signals against variations in temperature and device characteristics.
Conclusion
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/TUAN T LAM/Primary Examiner, Art Unit 2836 6/16/2026
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