DETAILED ACTION
This office action is in response to the filling with the office dated 04/12/2024
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In regards to independent claim 1, the limitation “wherein M>m, and T, M, N and m are positive integers.” In this claim, “M” and “m” represents multiple Identifications for example M is depicted as “test results, mismatch counts, and sample chips.” While “m” is classified as sample chips and test results. Making it unclear to which “M” is greater than “m.” Referring to the specification [0006] the variable M is depicted as sample chips, test results and mismatch counts. And the variable m is labeled as sample chips and test results. Making the specification devoid of teaching which variable is greater than as well as which are the positive integers. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
In regards to independent claim 9, the limitation “wherein M>m, and T, M, N and m are positive integers.” In this claim, “M” and “m” represents multiple Identifications for example M is depicted as “test results, mismatch counts, and sample chips.” While “m” is classified as sample chips and test results. Making it unclear to which “M” is greater than “m.” Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
As per claims 2-8 and 10 are rejected under 112(b) as they depend from the rejected claims 1 and 9 which do not rectify the defect.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Referring to the specification [0006] the variable M is depicted as sample chips, test results and mismatch counts. And the variable m is labeled as sample chips and test results. Making it unclear to which “M” is greater than “m.” The specification does not provide valid explanation that allow the reader to distinguish among the different definitions of M and m.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over WANG et al. (Hereinafter, “Wang”) in the Patent Application Publication Number US 20230213575 A1. In view of CHEN et al. (Hereinafter, “Chen”) In the Application Publication Number US 20160377678 A1.
As per independent claim 1, Wang teaches, “A test method for testing a circuit design,” ([0009], “a method for designing a scan chain and testing a target circuit” reads on “testing a circuit design.”) “Comprising: inputting T test patterns into M sample chips to generate M test results,” ([0017], “the number of test signal ST samples (also referred to as test patterns) increases with the complexity of the target circuit 20. When the number of test patterns (hereinafter referred to as test pattern count) increases, a time required to test the chip during the scan phase is thereby extended.” [0019], “the selected nodes are nodes among the target circuit 20 that have a certain level of influence on the calculation results (and/or test results) generated by the target circuit.” Reads on “test patterns into M sample chips to generate M test results.”)
“Wherein each sample chip is implemented with the circuit design and has N sensor positions;” ([0012], “the target circuit 20 represents a logically functional part of a chip, and the scan chain 10 is the part of the chip used to test the target circuit 20 during a scan phase.” Reads on “sample chip” and “has sensor N positions.”)
Wang is silent on, “obtaining M mismatch counts of each sensor position according to the M test results; obtaining a mismatch parameter of the each sensor position according to the M mismatch counts of the each sensor position;”
Chen teaches, “obtaining M mismatch counts of each sensor position according to the M test results; obtaining a mismatch parameter of the each sensor position according to the M mismatch counts of the each sensor position;” ([0028], “Total MisMatch Count (TMMC),” reads on “mismatch counts,” “test results” and “mismatch parameter.”)
“Selecting m sample chips from the M sample chips according to the M mismatch counts and the mismatch parameter of the each sensor position; selecting m test results from the M test results according to the m sample chips; and analyzing the m test results to obtain at least one critical point of the circuit design;” ([0034], “separation condition” reads on “selecting sample chips,” as well as “selecting m test results.”) Moreover ([0034], “the separation condition could be further analyzed to generate a featured scan pattern.” Reads on “analyzing the m test results to obtain at least one critical point of the circuit design.”)
Wang teaches, “wherein M>m, and T, M, N and m are positive integers.” Due to the uncertainly of the limitation of which M is greater than m the examiner interprets this as positive integers, ([0004], ”wherein M and N are positive integers no greater than a number of the plurality of test points” reads on “positive integers.”)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Wang in view of Chen, by incorporating the teachings of Chen on Total MisMatch Count (TMMC) for it’s efficiency advantages. As Chen discloses, ([0028], ”a total mismatch count corresponding to all test responses of each DUT will be calculated as a feature value. The principle of the TMMC feature is that a total mismatch count of an SLT-pass device is usually lower than the total mismatch count of an SLT-fail device. Using the TMMC as a failure feature, the device could be predicted as a SLT-pass device or a SLT-fail device without actually performing the SLT.”) Therefore, one would have been motivated to combine the teachings of Chen on The Total Mismatch Count as it would yield the predictable result of quality control improvement while testing circuits faster and efficiently, resulting in an increase of productivity. (KSR)
As per claim 2, Wang teaches, “The test method of claim 1, wherein the T test patterns are automatic test pattern generation (ATPG) patterns.” ([0014], “the test signal ST is generated by an automatic test pattern generation (ATPG) tool.” Reads on “automatic test pattern”)
As per claim 3, Wang is silent on, “The N sensor positions are generated according to n1 scan-out pins and n2 test cycles, n1 and n2 are positive integers, and N is a product of n1 and n2.”
Chen teaches, “The N sensor positions are generated according to n1 scan-out pins and n2 test cycles, n1 and n2 are positive integers, and N is a product of n1 and n2.” ([0029], “During the scan test operation, pattern sets are loaded into ATE memory one at a time. In this scheme, response grid positions in each pattern set and scan output are grouped to form one PS-SO-MMC failure feature. Assuming R pattern sets, N patterns, C cycles per pattern, and S scan outputs, there would be R×S failure features. Each feature would contain (N/R)×C grid positions. The mismatch count corresponding to a specific scan output with respect to a specific pattern set will be calculated.” Reads on “sensor positions are generated according to n1 scan-out pins and n2 test cycles” and “N is a product of n1 and n2.”)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify Wang in view of Chen by implementing the teachings of the scan output pin would enhance test results documentation as Chen further discloses, ([0029], “This scheme relates to the way scan patterns are organized for the ATE. Due to memory restriction of the ATE, the complete set of scan patterns is split into multiple pattern sets, each containing a smaller number of patterns. During the scan test operation, pattern sets are loaded into ATE memory one at a time. In this scheme, response grid positions in each pattern set and scan output are grouped to form one PS-SO-MMC failure feature.”) Scan outputs is a well-known testing method in the industry and by combining this would yield the predictable result of enhance monitoring of the chip making it easier to identify defects. (KSR)
As per claim 4, Wang teaches, “The test method of claim 3, wherein n2 is determined according to a length of a scan chain of the M sample chips.” ([0017], “when the number of test points TP in the scan chain 10 increases, the area of the circuit occupied by the test points TP also increases. In addition, the number of test signal ST samples (also referred to as test patterns) increases with the complexity of the target circuit 20. When the number of test patterns (hereinafter referred to as test pattern count) increases, a time required to test the chip during the scan phase is thereby extended.” Reads on “length of a scan chain.”)
As per claim 5, Wang teaches, “wherein when the T test patterns are inputted into the M sample chips,” ([0017], “ ST samples (also referred to as test patterns,” Wang further teaches [0014], “configured to transmit the received test signal ST into the target circuit 20.” Reads on “test patterns are inputted into the M sample chips”)
Wang is silent on, “at least one test voltage supplied to the M sample chips is lowered to be less than a predetermined voltage level, and/or at least one test frequency used for the M sample chips is set to exceed a predetermined frequency.”
Chen teaches, “at least one test voltage supplied to the M sample chips is lowered to be less than a predetermined voltage level, and/or at least one test frequency used for the M sample chips is set to exceed a predetermined frequency.” ([0023], “the stress conditions may refer to operating the DUT with lower operating voltage or higher operating frequencies than its nominal supply voltage and maximum operating frequency. For example, if the data sheet of the DUT specifies nominal supply at 1.2 V and maximum operating frequency at 1200 MHz.”)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Wang in view of Chen by combining the teachings of Chen which discloses further of testing a chip as it is a well-known method in the art to test a circuit chip by means of voltage injection. This ensures the chip would operate as it should according to the specification and also doubles as a way for testing the min/max tolerance it can handle before failure. (KSR)
As per claim 6, Wang is silent on “wherein the mismatch parameter of the each sensor position is a median of the M mismatch counts of the each sensor position.”
Chen teaches, “wherein the mismatch parameter of the each sensor position is a median of the M mismatch counts of the each sensor position.” ([0028], “a total mismatch count corresponding to all test responses of each DUT will be calculated as a feature value.” Reads on “median of the M mismatch counts.”)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Wang in view of Chen, by incorporating the teachings of Chen on Total MisMatch Count (TMMC) for it’s efficiency advantages. ([0028], ”a total mismatch count corresponding to all test responses of each DUT will be calculated as a feature value. The principle of the TMMC feature is that a total mismatch count of an SLT-pass device is usually lower than the total mismatch count of an SLT-fail device. Using the TMMC as a failure feature, the device could be predicted as a SLT-pass device or a SLT-fail device without actually performing the SLT.”)
Therefore, one would have been motivated to combine the teachings of Chen on The Total Mismatch Count would yield the predictable result to improve quality control while testing circuits faster and efficiently, resulting in an increase of productivity. (KSR)
As per claim 7, Wang is silent on, ““wherein analyzing the m test results to obtain the at least one critical point of the circuit design comprises: performing a failure diagnosis operation using the m test results to obtain x candidate points.”
Chen teaches, “wherein analyzing the m test results to obtain the at least one critical point of the circuit design comprises: performing a failure diagnosis operation using the m test results to obtain x candidate points; ([0033], “decision tree classification” reads on “performing a failure diagnosis” and “results to obtain x candidate points”) “And performing an analysis operation with the x candidate points and the m sample chips to select the at least one critical point from the x candidate points; wherein x is a positive integer.” ([0033], “best failure feature” reads on “critical point”.)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify Wang by Chen which teaches decision tree classification which performs fault diagnosis and failure analysis. This method is well known in the art and is a staple for quality control. One would have been motivated to implement this in their diagnostics testing to ensure satisfactory levels with consumers in the chip industry. (KSR)
In regards to independent claim 9, Wang teaches, “a test device for testing a circuit design,” ([0014], “automatic test pattern generation (ATPG) tool” reads on “a test device for testing a circuit design.”)
“Comprising: a test pattern unit configured to input T test patterns into M sample chips to generate M test results,” ([0017], “the number of test signal ST samples (also referred to as test patterns) increases with the complexity of the target circuit 20. When the number of test patterns (hereinafter referred to as test pattern count) increases, a time required to test the chip during the scan phase is thereby extended.” [0019], “the selected nodes are nodes among the target circuit 20 that have a certain level of influence on the calculation results (and/or test results) generated by the target circuit.” Reads on “test patterns into M sample chips to generate M test results,”)
“wherein the M sample chips are implemented with the circuit design, and each sample chip has N sensor positions;” ([0012], “the target circuit 20 represents a logically functional part of a chip, and the scan chain 10 is the part of the chip used to test the target circuit 20 during a scan phase.” Reads on “sample chip” and “has sensor N positions.”)
Wang is silent on, “And a processing unit configured to receive the M test results.”
Chen teaches, “a processing unit configured to receive the M test results” ([0022], “transition delay fault scan patterns using on-chip-clock (OCC) are applied to a device under test (DUT) on automated test equipment (ATE) under stress conditions.” [0029], “During the scan test operation, pattern sets are loaded into ATE memory one at a time.”
“Obtain M mismatch counts of each sensor position according to the M test results, obtain a mismatch parameter of the each sensor position according to the M mismatch counts of the each sensor position,” ([0028], “Total MisMatch Count (TMMC),” reads on “mismatch counts,” “test results” and “mismatch parameter.”)
“Select m sample chips from the M sample chips according to the M mismatch counts and the mismatch parameter of the each sensor position, select m test results from the M test results according to the m sample chips,” ([0034], “separation condition” reads on “selecting sample chips,” as well as “selecting m test results.”)
“And analyze the m test results to obtain at least one critical point of the circuit design;” ([0034], “The separation condition could be further analyzed to generate a featured scan pattern.” Reads on “analyzing the m test results to obtain at least one critical point of the circuit design.”)
Wang teaches, “Wherein M>m, and T, M, N and m are positive integers” Due to the uncertainly of the limitation of which M is greater than m the examiner interprets this as positive integers, ([0004], ”wherein M and N are positive integers no greater than a number of the plurality of test points” reads on “positive integers.”)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Wang by Chen, by incorporating the teachings of Chen on Total MisMatch Count (TMMC) for it’s efficiency advantages. ([0028], ”a total mismatch count corresponding to all test responses of each DUT will be calculated as a feature value. The principle of the TMMC feature is that a total mismatch count of an SLT-pass device is usually lower than the total mismatch count of an SLT-fail device. Using the TMMC as a failure feature, the device could be predicted as a SLT-pass device or a SLT-fail device without actually performing the SLT.”) Therefore, one would have been motivated to combine the teachings of Chen on The Total Mismatch Count would yield the predictable result to improve quality control while testing circuits faster and efficiently, resulting in an increase of productivity. (KSR)
As per claim 10, Wang is silent on, “The test device of claim 9, wherein the N sensor positions are generated according to n1 scan-out pins and n2 test cycles, n1 and n2 are positive integers, N is a product of n1 and n2.”
Chen teaches, “The test device of claim 9, wherein the N sensor positions are generated according to n1 scan-out pins and n2 test cycles, n1 and n2 are positive integers, N is a product of n1 and n2,” ([0029], “During the scan test operation, pattern sets are loaded into ATE memory one at a time. In this scheme, response grid positions in each pattern set and scan output are grouped to form one PS-SO-MMC failure feature. Assuming R pattern sets, N patterns, C cycles per pattern, and S scan outputs, there would be R×S failure features. Each feature would contain (N/R)×C grid positions. The mismatch count corresponding to a specific scan output with respect to a specific pattern set will be calculated.” Reads on “sensor positions are generated according to n1 scan-out pins and n2 test cycles” and “N is a product of n1 and n2.”)
Chen is silent on, “And n2 is determined according to a length of a scan chain of the M sample chips.”
Wang teaches, “And n2 is determined according to a length of a scan chain of the M sample chips.” ([0016] “The greater the number of test points TP in the scan chain 10, the more nodes in the target circuit 20 can be tested and observed, i.e., the higher the test coverage. The higher the test coverage, the greater the testability of the chip. Generally, a chip needs to be scanned before it can be tape-out, and there is a minimum test coverage requirement to ensure that the chip functions properly. Therefore, the higher the test coverage is, the more reliable the test results are and the easier it is to meet the minimum test coverage limit.”)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify Wang by Chen, implementing the teachings of the scan output pin would enhance test results documentation as Chen further discloses, ([0029], “This scheme relates to the way scan patterns are organized for the ATE. Due to memory restriction of the ATE, the complete set of scan patterns is split into multiple pattern sets, each containing a smaller number of patterns. During the scan test operation, pattern sets are loaded into ATE memory one at a time. In this scheme, response grid positions in each pattern set and scan output are grouped to form one PS-SO-MMC failure feature.”) Scan outputs is a well-known testing method in the industry and by combining this would yield the predictable result of enhance monitoring of the chip making it easier to identify defects. (KSR)
Claim Rejections - 35 USC § 103
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Chen, further in view of CHAKRAVARTHY et al. (Hereinafter, “Chakravathy”) In the Application Publication Number US 20100088560 A1.
As per claim 8, while Wang is silent on “The test method of claim 7, wherein the analysis operation is a Pareto analysis operation.” Chakravarthy teaches, “the analysis operation is a Pareto analysis operation”
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention, to modify Wang in view of Chen, by Chakravathy, utilizing the teachings of the Pareto analysis which discloses (Chakravathy [0011],” The proposed solutions by the above references are pre-diagnostic techniques where the grouping or clustering of ICs is done prior to the analysis to identify systematic defects and to de-emphasize random defects. Grouping or clustering is done on the basis of similar failures with respect to test vectors, scan-flops or primary outputs (POs) that failed on a particular die. Clustering approaches resolve some issues with SVD mentioned earlier. However, SVD by clustering still runs only on failed dies with systematic defects, so failed dies with random defects are not diagnosed. Failure patterns are collected on the database and Pareto analysis is performed on the `intelligently` selected failures, thus the results are obtained relatively faster.”)
One would have been motivated to implement the Pareto analysis to zero in on the root cause, that is causing the defects. Therefore, making the Pareto analysis a well-known method that used by many who are skilled in the art. (Adding a well-known technique in the art to attain a predictable/optimized outcome KSR)
Closest Prior art
The following relevant prior art of record is not cited in the office action.
Chickermane et al (US 8468404 B1) teaches, A method and system for reducing switching activity of a spreader network during a scan-load operation is disclosed. According to one embodiment, a spreader network receives a plurality of scan input signals from a tester. A linear feedback shift register of the spread network is updated using the plurality of scan input signals. Each bit of the linear feedback shift register is shifted at each shift cycle for a plurality of shift cycles. The linear feedback shift register outputs a nonlinear gating signal using a first set of outputs and a data value feeding one or more scan chains of the spreader network using a second set of outputs. The pipeline clock of a pipeline element of the scan chains is gated using the nonlinear gating signal, and the data value is fed to the scan chains based on the pipeline clock. The scan chains are fed with updated values at the pipeline stage.
LI et al (US 20260038197 A1) teaches, Systems and methods for shape completion are provided. In one embodiment, a computer implemented method includes receiving sensor data for a visualized area of an object as at least one point cloud representation. The computer implemented method also includes transforming the at least one point cloud representation into an input voxel grid of the visualized area of the object. The input voxel grid is a volumetric representation. The computer implemented method further includes encoding the input voxel grid into a partial latent vector that lies on a partial latent space. The computer implemented method yet further includes determining a mapping between the partial latent space and a complete latent space based on the sensor data. The computer implemented method includes predicting a complete latent vector based on the complete latent space. The computer implemented method also includes estimating a complete shape of an object based on the complete latent space.
Park et al (US 20230108149 A1) teaches, A method of operating an electrical test prediction apparatus includes determining a relationship between first electrical test (ET) data, corresponding to at least one shot region comprising a subset of a plurality of semiconductor chips of a wafer, and electrical die sorting (EDS) data, obtained by measuring a state of each chip on the wafer by a testing device, and predicting second ET data, corresponding to an region of the wafer other than the at least one shot region by performing machine learning on the relationship.
Franklin et al (US 20220178983 A1) teaches, Electronic device characterization platforms, systems, devices, and methods for use in testing instruments, devices, and sensors that is portable, modular, multiplexed, and automated are disclosed. The system includes a substrate, a chip adapter, such as a chip socket, and an optional housing. Chip samples to be tested can be disposed in the chip adapter and various environmental modules designed to supply different environmental conditions to the chip sample can be disposed over the chip adapter, enabling testing of the chip samples to be performed in the different environment conditions. The system can further include various connectors that allow for add-on modules to be included as part of the system. Methods of characterizing electronic devices and sensors are also disclosed.
Sonawane et al (US 20200363470 A1) teaches, Systems and methods enable the updating of tests, test sequences, fault models, and test conditions such as voltage and clock frequencies, over the life cycle of a safety critical application for complex integrated circuits and systems.
Ni et al (CN 115308562 A) teaches, The application model belongs to the technical field of computer, specifically to a chip testing method, a chip testing device, a computer readable medium and an electronic device. The chip testing method comprises: obtaining a prediction model for predicting the quality of the chip; according to the collected test data sample and the prediction model, modifying the flow of the current test flow, so as to generate the adaptability test flow of the chip to be tested; performing quality test to the chip to be tested according to the adaptability test flow, so as to obtain the quality test result of the chip to be tested; updating the test data sample according to the quality test result of the chip to be tested, and updating the prediction model according to the quality test result of the chip to be tested. The application can reduce the chip test time, reduce the chip test cost, improve the chip test efficiency and test precision.
Conclusion
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/JARELL W PAXTON/Examiner, Art Unit 2858
/EMAN A ALKAFAWI/Supervisory Patent Examiner, Art Unit 2858
3/3/2026