DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A: claims 1-8 and 10-20 in the reply filed on July 14, 2026 is acknowledged.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chow et al. US 8,278,141.
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Chow et al. US 8,278,141
Regarding claim 1, Chow et al. in Fig. 6 and col. 3, line 54-col. 7, line 36 disclose a method comprising:
interconnecting a semiconductor die 114 col. 3, line 64-col. 4, line 7 with a package substrate 102 col. 3, lines 58-67;
interconnecting a flex substrate sub-assembly 602 col. 6, line 64-col. 7, line 21 with the package substrate 102,
the flex substrate sub-assembly 602 comprising:
a flexible conductive trace, a first portion of the flexible conductive trace conductively connected to the package substrate col. 6, line 64-col. 7, line 21; and
encapsulating with an encapsulant 140 col. 7, lines 22-36 at least a portion of the semiconductor die 114 and the flex sub-assembly 602, a second portion (annotated above) of the flexible conductive trace exposed at a top surface of the encapsulant 140 col. 7, lines 32-36.
Regarding claim 2, Chow et al. in Fig. 6 and col. 3, line 54-col. 7, line 36 disclose the method of claim 1, wherein the exposed second portion (annotated above) of the flexible conductive trace is configured for attachment of an external component 136 col. 7, lines 32-36.
Regarding claim 3, Chow et al. in Fig. 6 and col. 3, line 54-col. 7, line 36 disclose the method of claim 1, wherein the flexible conductive trace is interconnected with the semiconductor die 114 by way of the package substrate 102 col. 6, line 64-col. 7, line 9.
Regarding claim 4, Chow et al. in Fig. 6 and col. 3, line 54-col. 7, line 36 disclose the method of claim 1, wherein a third portion of the flexible conductive trace is affixed to a backside of the semiconductor die col. 6, line 64-col. 7, line 9, the third portion located between the first portion and the second portion of the flexible conductive trace (annotated above).
Regarding claim 5, Chow et al. in Fig. 6 and col. 3, line 54-col. 7, line 36 disclose the method of claim 1, wherein the flex substrate sub-assembly further comprises a spacer 138 (e.g. mold cap) col. 7, lines 22-31 disposed between the second portion of the flexible conductive trace and a backside of the semiconductor die 114.
Regarding claim 6, Chow et al. in Fig. 6 and col. 3, line 54-col. 7, line 36 disclose the method of claim 1, wherein the flex substrate sub-assembly further comprises a second semiconductor die 132 col. 7, lines 10-31 conductively connected to the flexible conductive trace.
Regarding claim 7, Chow et al. in Fig. 6 and col. 3, line 54-col. 7, line 36 disclose the method of claim 1, further comprising conductively connecting an external component 136 col. 7, lines 10-21 to the exposed second portion of the flexible conductive trace, wherein the external component is characterized as one of a connector, semiconductor device, antenna, and battery col. 4, lines 38-44.
Regarding claim 8, Chow et al. in Fig. 6 and col. 3, line 54-col. 7, line 36 disclose the method of claim 7, wherein the external component 136 is interconnected with the semiconductor die 114 by way of the flexible conductive trace col. 7, lines 10-21.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chow et al. US 8,278,141 in view of Yu et al. US 2022/0173048.
Regarding claim 10, Chow et al. in Fig. 6 and col. 3, line 54-col. 7, line 36 disclose a semiconductor device comprising:
a package substrate 102 col. 3, lines 58-67;
a semiconductor die 114 col. 3, line 64-col. 4, line 7 having an active side and a backside opposite of the active side, the active side interconnected with the package substrate 102 col. 3, line 64-col. 4, line7;
a flex substrate sub-assembly 602 col. 6, line 64-col. 7, line 21 with the package substrate 102,
the flex substrate sub-assembly 602 comprising:
a flexible conductive trace, a first portion of the flexible conductive trace conductively connected to the package substrate col. 6, line 64-col. 7, line 21; and
an encapsulant 140 col. 7, lines 22-36 encapsulating at least a portion of the semiconductor die 114 and the flex sub-assembly 602, a second portion of the flexible conductive trace exposed at a top surface of the encapsulant 140 col. 7, lines 32-36 (annotated above).
Chow et al. do not expressly disclose bond pads at the active side interconnected with the package substrate.
However, Yu et al. in Fig. 5C and [0053] teach a semiconductor die 37-3 including conductive pads 373 to wire bond the active surface of the die in the stacked package structure. Yu et al. show that bond pads are used in wire bonding to electrically connect an active side of a semiconductor device.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Yu et al. in the semiconductor device of Chow et al. for the purpose of improving the structure of the stacked package.
Regarding claim 11, Chow et al. in view of Yu et al. teach the semiconductor device of claim 10. Chow et al. teach wherein a third portion of the flexible conductive trace is affixed to a backside of the semiconductor die col. 6, line 64-col. 7, line 9, the third portion located between the first portion and the second portion of the flexible conductive trace (annotated above).
Regarding claim 12, Chow et al. in view of Yu et al. teach the semiconductor device of claim 10. Chow et al. teach wherein the flex substrate sub-assembly further comprises a spacer 138 (e.g. mold cap) col. 7, lines 22-31 disposed between the second portion of the flexible conductive trace and a backside of the semiconductor die 114.
Regarding claim 13, Chow et al. in view of Yu et al. teach the semiconductor device of claim 10. Chow et al. teach wherein the flexible conductive trace is interconnected with the semiconductor die 114 by way of the package substrate 102 col. 6, line 64-col. 7, line 9.
Regarding claim 14, Chow et al. in view of Yu et al. teach the semiconductor device of claim 10. Chow et al. teach the semiconductor device of claim 10 further comprising an external component 136 col. 7, lines 32-36 conductively connected to the exposed second portion of the flexible conductive trace.
Regarding claim 15, Chow et al. in view of Yu et al. teach the semiconductor device of claim 14. Chow et al. teach wherein the external component 136 is interconnected with the semiconductor die 114 by way of the flexible conductive trace col. 7, lines 10-21.
Regarding claim 16, Chow et al. in Fig. 6 and col. 3, line 54-col. 7, line 36 disclose a method comprising:
interconnecting a semiconductor die 114 col. 3, line 64-col. 4, line 7 with a package substrate102 col. 3, lines 58-67;
interconnecting a flex substrate sub-assembly 602 col. 6, line 64-col. 7, line 21 with the package substrate 102, the flex substrate sub-assembly 602 comprising:
a flexible conductive trace, a first portion of the flexible conductive trace conductively connected to the package substrate col. 6, line 64-col. 7, line 21; and
encapsulating with an encapsulant 140 col. 7, lines 22-36 at least a portion of the semiconductor die 114 and the flex sub-assembly 602, a second portion of the flexible conductive trace exposed at a top surface of the encapsulant 140 col. 7, lines 32-36 (annotated above) and configured for attachment of an external component 136 col. 7, lines 32-36.
Chow et al. do not expressly disclose interconnecting bond pads of the semiconductor die with the package substrate.
However, Yu et al. in Fig. 5C and [0053] teach electrically connecting a semiconductor die 37-3 using conductive pads 373 to wire bond the active surface of the die in the stacked package structure. Yu et al. show that bond pads are used in wire bonding to electrically connect an active side of a semiconductor device.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Yu et al. in the semiconductor device of Chow et al. for the purpose of improving the structure of the stacked package.
Regarding claim 17, Chow et al. in view of Yu et al. teach the semiconductor device of claim 16. Chow et al. teach wherein the flexible conductive trace is interconnected with the semiconductor die 114 by way of the package substrate 102 col. 6, line 64-col. 7, line 9.
Regarding claim 18, Chow et al. in view of Yu et al. teach the semiconductor device of claim 16. Chow et al. teach wherein a third portion of the flexible conductive trace is affixed to a backside of the semiconductor die col. 6, line 64-col. 7, line 9, the third portion located between the first portion and the second portion of the flexible conductive trace (annotated above).
Regarding claim 19, Chow et al. in view of Yu et al. teach the semiconductor device of claim 18. Chow et al. in Fig. 6 and col. 3, line 54-col. 7, line 36 teach wherein the second portion of the flexible conductive trace is folded over the third portion of the flexible conductive trace such that the second portion substantially overlaps the third portion of the flexible conductive trace and a backside of the semiconductor die 114.
Regarding claim 20, Chow et al. in view of Yu et al. teach the semiconductor device of claim 16. Chow et al. teach the method of claim 16, further comprising conductively connecting an external component 136 col. 7, lines 32-36 to the exposed second portion of the flexible conductive trace (annotated above).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SONYA D MCCALL-SHEPARD whose telephone number is (571)272-9801. The examiner can normally be reached M-F: 8:30 AM-5:00 PM.
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/Sonya McCall-Shepard/ Primary Examiner, Art Unit 2898
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