Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant's submission filed on 3/13/2026 has been entered. Claims 1-20 are pending.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/30/2026 is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7-10, 13-17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Parakh et al. (US 2020/0257625 hereinafter Parakh) in view of Chaman et al. (US 2022/0182384 hereinafter Chaman).
Regarding claim 1, Parakh discloses a system comprising:
a first compute node (FIG. 1, 2A-B & 3A-B);
a storage device (FIG. 1, 2A-B & 3A-B, ¶ [0022]); and
a first data processing unit (DPU) separately connected to the first compute node and the storage device: comprising a cache, and configured to (FIG. 1, 2A-B & 3A-B, ¶ [0022]):
receive from the first compute node, a first data access request to access first data in the storage device (FIG. 1, 2A-B, 3A-B & 4, ¶ [0022]-[0024]; i.e. receiving from the client devices requests data items from the distributed caching system or the primary storage devices);
obtain the first data from the storage device based on the first data access request (FIG. 1, 2A-B, 3A-B & 4, ¶ [0022]-[0024]; i.e. obtaining the data items from the primary storage devices and/or external caches);
send the first data to the first compute node (FIG. 1, 2A-B, 3A-B & 4, ¶ [0022]-[0024], [0029]-[0030], [0052]; i.e. sending the data items to the client devices);
cache, [[after obtaining the first distributed lock,]] the first data in the cache (FIG. 1, 2A-B, 3A-B & 4, ¶ [0022]-[0024], [0029]-[0030], [0052]; i.e. storing the requested data items to the internal caches and/or external caches);
receive, from the first compute node, a second data access request to access the first data in the storage device (FIG. 1, 2A-B, 3A-B & 4, ¶ [0022]-[0024], [0029]-[0030], [0052]; i.e. receiving the subsequent requests for the data items from the client devices or another client devices);
determine, in response to the second data access request, that the first data is cached in the cache (FIG. 1, 2A-B, 3A-B & 4, ¶ [0022]-[0024], [0029]-[0030], [0052]; i.e. determining that the data items are in the internal caches or external caches); and
send the first data to the first compute node in response to the second data access request (FIG. 1, 2A-B, 3A-B & 4, ¶ [0022]-[0024], [0029]-[0030], [0052]; i.e. sending the cached data items to the client devices).
Parakh does not explicitly disclose send, to the storage device, a first lock request for a first distributed lock, wherein the first distributed lock indicates that the first DPU has a cache permission on the first data; obtain the first distributed lock from the storage device in response to the firs lock request.
However, Chaman discloses send, to the storage device, a first lock request for a first distributed lock, wherein the first distributed lock indicates that the first DPU has a cache permission on the first data; obtain the first distributed lock from the storage device in response to the firs lock request (FIG. 4-5, ¶ [0087], [0091]-[0096]).
Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine Parakh and Chaman in order to reduce latency for responding to client requests as well as reducing latency for clients storing content in the distributed storage system (Chaman, ¶ [0003]-[0006]).
Regarding claim 2, Parakh in view of Chaman discloses the system of claim 1, wherein the first data access request comprises a storage address of the first data in the storage device (Parakh, ¶ [0018], [0083]).
Regarding claim 3, Parakh in view of Chaman discloses the system of claim 1, wherein the storage device is configured to: receive the first lock request (Chaman, FIG. 4, ¶ [0082]-[0089]); determine whether conflicting distributed lock exists for the first data in response to the first lock request (Chaman, FIG. 4, ¶ [0082]-[0089]); and send the first distributed lock to the first DPU based on determining that no conflicting distributed lock exists for the first data (Chaman, FIG. 4, ¶ [0082]-[0089]).
Regarding claim 7, Parakh discloses a method implemented by a first data processing unit (DPU), the method comprising:
receiving, from a compute node, a first data access request to access first data in a storage device (FIG. 1, 2A-B, 3A-B & 4, ¶ [0022]-[0024]; i.e. receiving from the client devices requests data items from the distributed caching system or the primary storage devices);
obtaining the first data from the storage device based on the first data access request (FIG. 1, 2A-B, 3A-B & 4, ¶ [0022]-[0024], [0029]-[0030], [0052]; i.e. obtaining the data items from the primary storage devices and/or external caches);
sending the first data to the compute node (FIG. 1, 2A-B, 3A-B & 4, ¶ [0022]-[0024], [0029]-[0030], [0052]; i.e. sending the data items to the client devices);
sending, to the storage device, a first lock request for a first distributed lock, wherein the first distributed lock indicates that the first DPU has a cache permission on the first data;
obtaining the first distributed lock from the storage device in response to the first lock request;
caching, after obtaining the first distributed lock, the first data in a first cache of the DPU (FIG. 1, 2A-B, 3A-B & 4, ¶ [0022]-[0024], [0029]-[0030], [0052]; i.e. storing the requested data items to the internal caches and/or external caches of the front-end system or back-end system);
receiving, from the compute node, a second data access request to access the first data in the storage device (FIG. 1, 2A-B, 3A-B & 4, ¶ [0022]-[0024], [0029]-[0030], [0052]; i.e. receiving the subsequent requests for the data items from the client devices or another client devices);
determining, in response to the second data access request, that the first data is cached in the first cache (FIG. 1, 2A-B, 3A-B & 4, ¶ [0022]-[0024], [0029]-[0030], [0052]; i.e. determining that the data items are in the internal caches or external caches); and
sending the first data in the first cache to the compute node in response to the second data access request (FIG. 1, 2A-B, 3A-B & 4, ¶ [0022]-[0024], [0029]-[0030], [0052]; i.e. sending the cached data items to the client devices).
Parakh does not explicitly disclose sending, to the storage device, a first lock request for a first distributed lock, wherein the first distributed lock indicates that the first DPU has a cache permission on the first data; obtaining the first distributed lock from the storage device in response to the first lock request.
However, Chaman discloses sending, to the storage device, a first lock request for a first distributed lock, wherein the first distributed lock indicates that the first DPU has a cache permission on the first data; obtaining the first distributed lock from the storage device in response to the first lock request (FIG. 4-5, ¶ [0087], [0091]-[0096]).
Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine Parakh and Chaman in order to reduce latency for responding to client requests as well as reducing latency for clients storing content in the distributed storage system (Chaman, ¶ [0003]-[0006]).
Regarding claim 8, Parakh in view of Chaman discloses the method of claim 7, wherein the first data access request comprises a storage address of the first data in the storage device (Parakh, ¶ [0018], [0083]).
Regarding claim 9, Parakh in view of Chaman discloses the method of claim 7, further comprising: receiving, from the compute node, a third data access request to access second data in the storage device (Chaman, FIG. 4, ¶ [0082]-[0089]); determining that the second data is not cached in the first cache of the first DPU(Chaman, FIG. 4, ¶ [0082]-[0089]); determining that the second data is cached in a second cache of a second DPU (Chaman, FIG. 4, ¶ [0082]-[0089]); sending, to the second DPU, a request for the second data (Chaman, FIG. 4, ¶ [0082]-[0089]); obtaining the second data from the second DPU in response to the request (Chaman, FIG. 4, ¶ [0082]-[0089]); and sending the second data to the compute node (Chaman, FIG. 4, ¶ [0082]-[0089]).
Regarding claim 10, Parakh in view of Chaman discloses the method of claim 9, further comprising: receiving, from the compute node, a third data access request to update the first data; and requesting, based on the third data access request, the storage device to update the first data (Parakh, ¶ [0047]-[0048], [0110]-[0113]).
Regarding claim 13, Parakh in view of Chaman discloses the method of claim 7, further comprising: receiving, from a second DPU, a request for the first data (Parakh, FIG. 1, 2A-B, 3A-B & 4, ¶ [0022]-[0027]); and sending the first data in the first cache to the second DPU in response to the request (Parakh, FIG. 1, 2A-B, 3A-B & 4, ¶ [0022]-[0027]).
Regarding claim 14, Parakh discloses a first data processing unit; (DPU) comprising:
a communication interface (FIG. 1, 2A-B & 3A-B, ¶ [0022]-[0024]);
a first cache (FIG. 1, 2A-B & 3A-B); and
at least one integrated circuit configured to (FIG. 1, 2A-B & 3A-B):
receive, from a compute node via the communication interface, a first data access request to access first data in a storage device (FIG. 1, 2A-B, 3A-B & 4, ¶ [0022]-[0024]; i.e. receiving from the client devices requests data items from the distributed caching system or the primary storage devices);
obtain the first data from the storage device based on the first data access request (FIG. 1, 2A-B, 3A-B & 4, ¶ [0022]-[0024], [0029]-[0030], [0052]; i.e. obtaining the data items from the primary storage devices and/or external caches);
send the first data to the compute node (FIG. 1, 2A-B, 3A-B & 4, ¶ [0022]-[0024], [0029]-[0030], [0052]; i.e. sending the data items to the client devices);
cache, after obtaining the first distributed lock, the first data in the first cache (FIG. 1, 2A-B, 3A-B & 4, ¶ [0022]-[0024], [0029]-[0030], [0052]; i.e. storing the requested data items to the internal caches and/or external caches);
receive, from the compute node, a second data access request to access the first data in the storage device (FIG. 1, 2A-B, 3A-B & 4, ¶ [0022]-[0024], [0029]-[0030], [0052]; i.e. receiving the subsequent requests for the data items from the client devices or another client devices);
determine, in response to the second data access request, that the first data is cached in the first cache (FIG. 1, 2A-B, 3A-B & 4, ¶ [0022]-[0024], [0029]-[0030], [0052]; i.e. determining that the data items are in the internal caches or external caches); and
send the first data in the first cache to the compute node in response to the second data access request (FIG. 1, 2A-B, 3A-B & 4, ¶ [0022]-[0024], [0029]-[0030], [0052]; i.e. sending the cached data items to the client devices).
Parakh does not explicitly disclose send, to the storage device, a first lock request for a first distributed lock, wherein the first distributed lock indicates that the first DPU has a cache permission on the first data; obtain, from the storage device, the first distributed lock based on the first lock request.
However, Chaman discloses send, to the storage device, a first lock request for a first distributed lock, wherein the first distributed lock indicates that the first DPU has a cache permission on the first data; obtain, from the storage device, the first distributed lock based on the first lock request (FIG. 4-5, ¶ [0087], [0091]-[0096]).
Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine Parakh and Chaman in order to reduce latency for responding to client requests as well as reducing latency for clients storing content in the distributed storage system (Chaman, ¶ [0003]-[0006]).
Regarding claim 15, Parakh in view of Chaman discloses the first DPU of claim 14, wherein the first data access request comprises a storage address of the first data in the storage device (Parakh, ¶ [0018], [0083]).
Regarding claim 16, Parakh in view of Chaman discloses the first DPU of claim 14, wherein the at least one integrated circuit is further configured to: receiving, from the compute node, a third data access request to access second data in the storage device (Chaman, FIG. 4, ¶ [0082]-[0089]); determining that the second data is not cached in the first cache of the first DPU (Chaman, FIG. 4, ¶ [0082]-[0089]); determining that the second data is cached in the second cache of a second DPU (Chaman, FIG. 4, ¶ [0082]-[0089]); sending, to the second DPU, a request for the second data; obtaining the second data from the second DPU in response to the request (Chaman, FIG. 4, ¶ [0082]-[0089]); and sending the second data to the compute node (Chaman, FIG. 4, ¶ [0082]-[0089]).
Regarding claim 17, Parakh in view of Chaman discloses the first DPU of claim 14, wherein the at least one integrated circuit is further configured to: receive, from the compute node, a third data access request to update the first data; and request, based on the third data access request, the storage device to update the first data (Parakh, ¶ [0047]-[0048], [0110]-[0113]).
Regarding claim 20, Parakh in view of Chaman discloses the first DPU of claim 14, wherein the at least one integrated circuit is further configured to: receive, from a second DPU, a request for the first data (Parakh, FIG. 1, 2A-B, 3A-B & 4, ¶ [0022]-[0027]); and send the first data in the cache to the second DPU in response to the request (Parakh, FIG. 1, 2A-B, 3A-B & 4, ¶ [0022]-[0027]).
Claims 4-6, 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Parakh et al. (US 2020/0257625 hereinafter Parakh) in view of Chaman et al. (US 2022/0182384 hereinafter Chaman) and further in view of Cui et al. (US 2023/0099061 hereinafter Cui).
Regarding claim 4, Parakh in view of Chaman discloses the system of claim 3, further comprising: a second compute node; and a second DPU separately connected to the second compute node and the storage device, wherein the second DPU is configured to: receive, from the second compute node, a third data access request (Parakh, FIG. 1, 2A-B, 3A-B & 4, ¶ [0022]-[0027]).
Parakh in view of Chaman does not explicitly disclose said third data access request is to update the first data; and send, based on the third data access request, a request to the storage device to update the first data, and wherein the storage device is further configured to: recall the first distributed lock of the first DPU; and update the first data based on the request from the second DPU.
However, Cui discloses updating the first data; and send, based on the third data access request, a request to the storage device to update the first data, and wherein the storage device is further configured to: recall the first distributed lock of the first DPU; and update the first data based on the request from the second DPU (¶ [0078]-[0080]).
Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine Parakh and Cui in order to provide right-size allocation of computing resources to support text searches without resulting in computing resource waste (Cui, ¶ [0014]-[0016]).
Regarding claim 5, Parakh in view of Chaman discloses the system of claim 3, further comprising: a second compute node; and a second DPU separately connected to the second compute node and the storage device (Parakh, FIG. 1, 2A-B, 3A-B & 4, ¶ [0022]-[0027]).
Parakh in view of Chaman does not explicitly disclose wherein the second DPU is configured to send, to the storage device, a second lock request for a second distributed lock, wherein the second distributed lock indicates that the second DPU has an update permission on the first data, wherein the storage device is further configured to authorize the second distributed lock for the second DPU in response to the second lock request, and wherein the second DPU is further configured to: receive, from the second compute node, a fourth data access request to update the first data; obtain the first data from the storage device based on the second distributed lock; and update the first data based on the fourth data access request.
However, Cui discloses wherein the second DPU is configured to send, to the storage device, a second lock request for a second distributed lock, wherein the second distributed lock indicates that the second DPU has an update permission on the first data, wherein the storage device is further configured to authorize the second distributed lock for the second DPU in response to the second lock request, and wherein the second DPU is further configured to: receive, from the second compute node, a fourth data access request to update the first data; obtain the first data from the storage device based on the second distributed lock; and update the first data based on the fourth data access request (¶ [0078]-[0080]).
Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine Parakh and Cui in order to provide right-size allocation of computing resources to support text searches without resulting in computing resource waste (Cui, ¶ [0014]-[0016]).
Regarding claim 6, Parakh in view of Chaman in view of Cui discloses the system of claim 5, further comprising: a third compute node; and a third DPU separately connected to the third compute node and the storage device, wherein the third DPU is configured to: receive, from the third compute node, a fifth data access request to access the first data in the storage device; determine that the first data is stored in the cache of the first DPU; obtain the first data from the first DPU; and send the first data to the third compute node (Parakh, FIG. 1, 2A-B, 3A-B & 4, ¶ [0022]-[0030], [0052]).
Regarding claim 12, Parakh in view of Chaman discloses the method of claim 9.
Parakh in view of Chaman does not explicitly disclose sending, to the storage device, a second lock request for a second distributed lock, wherein the second distributed lock indicates that the DPU has an update permission on the first data; obtaining, from the storage device, the second distributed lock; receiving, from the compute node after obtaining the second distributed lock, a fourth data access request to update the first data; and updating the first data in the first cache based on the fourth data access request.
However, Cui discloses sending, to the storage device, a second lock request for a second distributed lock, wherein the second distributed lock indicates that the DPU has an update permission on the first data; obtaining, from the storage device, the second distributed lock; receiving, from the compute node after obtaining the second distributed lock, a fourth data access request to update the first data; and updating the first data in the first cache based on the fourth data access request (¶ [0078]-[0080]).
Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine Parakh and Cui in order to provide right-size allocation of computing resources to support text searches without resulting in computing resource waste (Cui, ¶ [0014]-[0016]).
Regarding claim 19, Parakh in view of Chaman discloses the first DPU of claim 16.
Parakh in view of Chaman does not explicitly disclose sending, to the storage device, a second lock request for a second distributed lock, wherein the second distributed lock indicates that the first DPU has an update permission on the first data; obtaining, from the storage device, the second distributed lock; receiving, from the compute node after obtaining the second distributed lock, a fourth data access request to update the first data; and updating the first data in the first cache based on the fourth data access request.
However, Cui discloses wherein the at least one integrated circuit is further configured to: send, to the storage device, a second lock request for a second distributed lock, wherein the second distributed lock indicates that the first DPU has an update permission on the first data; obtain, from the storage device, the second distributed lock; receive, from the compute node after obtaining the second distributed lock, a fourth data access request to update the first data; and update the first data in the first cache based on the fourth data access request (¶ [0078]-[0080]).
Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine Parakh and Cui in order to provide right-size allocation of computing resources to support text searches without resulting in computing resource waste (Cui, ¶ [0014]-[0016]).
Claims 11 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Parakh et al. (US 2020/0257625 hereinafter Parakh) in view of Chaman et al. (US 2022/0182384 hereinafter Chaman) and further in view of Sproat et al. (US 11,216,316 hereinafter Sproat).
Regarding claim 11, Parakh in view of Chaman discloses the method of claim 9.
Parakh in view of Chaman does not explicitly discloses deleting the first distributed lock; and deleting the first data in the first cache based on an indication of the storage device.
However, Sproat discloses deleting the first distributed lock; and deleting the first data in the first cache based on an indication of the storage device (col. 4, lines 20-30, col. 7, lines 11-67).
Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date to combine Parakh and Sproat in order to improve the performance of the digital storage or memory management (Sproat, col. 5, line 17-col. 6, line 6).
Regarding claim 18, Parakh in view of Chaman discloses the first DPU of claim 16.
Parakh in view of Chaman does not explicitly disclose wherein the at least one integrated circuit is further configured to: delete the first distributed lock; and delete the first data in the first cache based on an indication of the storage device.
However, Sproat discloses wherein the at least one integrated circuit is further configured to: delete the first distributed lock; and delete the first data in the first cache based on an indication of the storage device (col. 4, lines 20-30, col. 7, lines 11-67).
Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine Parakh and Sproat in order to improve the performance of the digital storage or memory management (Sproat, col. 5, line 17-col. 6, line 6).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.D.N/Examiner, Art Unit 2435
/AMIR MEHRMANESH/Supervisory Patent Examiner, Art Unit 2435
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