Prosecution Insights
Last updated: October 02, 2026
Application No. 18/633,932

DYNAMICALLY POWER ON/OFF PROCESSING CLUSTERS DURING EXECUTION

Non-Final OA §103§DP
Filed
Apr 12, 2024
Priority
Apr 21, 2017 — continuation of 10/528,118 +1 more
Examiner
NGUYEN, PHIL K
Art Unit
2176
Tech Center
2100 — Computer Architecture & Software
Assignee
Intel Corporation
OA Round
5 (Non-Final)
82%
Grant Probability
Favorable
5-6
OA Rounds
2m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
453 granted / 549 resolved
+27.5% vs TC avg
Moderate +14% lift
Without
With
+14.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
19 currently pending
Career history
567
Total Applications
across all art units

Statute-Specific Performance

§101
7.3%
-32.7% vs TC avg
§103
52.7%
+12.7% vs TC avg
§102
19.9%
-20.1% vs TC avg
§112
12.0%
-28.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 549 resolved cases

Office Action

§103 §DP
DETAILED ACTION Claims 1,3,21,22,24,27,28,30,33 are pending. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp. Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b). Claim(s) 1,3,21,22,24,27,28,30,33 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim1-12 of US Patent No. 10,528,118 B2 and claims 1-21 of US Patent No. 11, 989, 076. Although the conflicting claims are not identical, they are not patentably distinct from each other because the claims are directed to substantially the same subject matter involving selectively controlling the processing resources based on the workload utilization for the processing resources. Claim Rejections - 35 USC § 103 The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action: (a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made. Claims 1,3,21,22,24,27,28,30,33 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Kaburlasos (US Publication US 20160054782 A1) and in view of Kuroda et al1 (US 20160048199 A1) and in further view of Sato (US Publication 20160292120 A1). The teachings of Kaburlasos and Kuroda as disclosed in the previous office action are hereby incorporated by reference to the extent applicable to the amended claims. Applicant has amended independent claims 1, 22 and 28 to incorporate the limitations that (1) transmit state information relating to the workload from the first set of processing resources to the second set of processing resources. Regarding limitation (1), Kaburlasos and Kuroda do not explicitly disclose (1) transmit state information relating to the workload from the first set of processing resources to the second set of processing resources. Sato discloses (1) transmit state information relating to the workload from the first set of processing resources to the second set of processing resources [0004: when the work load (task) is transferred from one of the processing circuits to the other processing circuit, the state in the processing circuit executing the work load is transferred from that processing circuit to the other processing circuit] [0005] [0007] [0031] [0036] [0047] [0052] [0054]. Thus, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kaburlasos, Kuroda and Sato together because they all directed to transferring workload between processing units. Sato’s disclosing of transmit state information relating to the workload from the first set of processing resources to the second set of processing resources would allow Kaburlasos in view of Kuroda to increase the efficiency and prevent loss or corrupted execution data by continuously executing the workload operation without delay according to the transferred workload state. Regarding claims 3 and 21, the base claim 1 is taught by Kaburlasos and in view of Kuroda and in further view of Sata as disclosed above and the additional limitations in claims 3 and 21 are taught by Kaburlasos as disclosed in the previous office action. Regarding claims 22 and 28, these claims are rejected for the same reasons as set forth in claim 1 above. Regarding claims 24 and 27, these claims are rejected for the same reasons as set forth in claims 3 and 21 taught by Kaburlasos as disclosed in the previous office action. Regarding claims 30 and 33, these claims are rejected for the same reasons as set forth in claims 3 and 21 taught by Kaburlasos as disclosed in the previous office action. Response to Arguments Applicant’s arguments filed on 04/23/2026 have been fully considered but are moot in view of new ground(s) of rejection because the arguments do not apply to any of the references being used in the current rejection. The double patenting rejection is still maintained since the terminal disclaimer has not yet filed. Conclusion Examiner's note: Examiner has cited particular paragraphs and columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner (see MPEP § 2123). Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHIL K NGUYEN whose telephone number is (571)270-3356. The examiner can normally be reached 9:30 a.m - 5 p.m. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at (571)270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PHIL K NGUYEN/Primary Examiner, Art Unit 2176 1 Kaburlasos and Kuroda were cited in the previous office action.
Read full office action

Prosecution Timeline

Show 6 earlier events
Aug 04, 2025
Final Rejection mailed — §103, §DP
Aug 08, 2025
Response after Non-Final Action
Oct 15, 2025
Request for Continued Examination
Oct 20, 2025
Response after Non-Final Action
Dec 23, 2025
Non-Final Rejection mailed — §103, §DP
Apr 23, 2026
Response Filed
Jul 16, 2026
Final Rejection mailed — §103, §DP
Aug 25, 2026
Response after Non-Final Action

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12743122
CIRCUITRY AND METHOD FOR QUANTIZATION ERROR CORRECTION FOR TIME SYNCHRONIZATION
2y 9m to grant Granted Sep 22, 2026
Patent 12737029
PROCESSORS HAVING CORE CONTROL CIRCUITS TO CONTROL CORE TRANSITIONS BETWEEN LOW POWER MODES AND RELATED METHODS
2y 6m to grant Granted Sep 15, 2026
Patent 12737021
CALIBRATION OF RESOURCE SERVER POWER ALLOCATIONS WITHIN A DATA STORAGE DEVICE USING CONFORMAL PREDICTIONS
1y 10m to grant Granted Sep 15, 2026
Patent 12724449
ASYNCHRONOUS ASIC
2y 1m to grant Granted Sep 01, 2026
Patent 12699432
CLOCK PULSE MANAGEMENT TO REDUCE PEAK POWER LEVELS
2y 7m to grant Granted Aug 04, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
82%
Grant Probability
97%
With Interview (+14.2%)
2y 8m (~2m remaining)
Median Time to Grant
High
PTA Risk
Based on 549 resolved cases by this examiner. Grant probability derived from career allowance rate.

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