DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Claim(s) 1-3,21-24,27-30, 33 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim1-12 of US Patent No. 10,528,118 B2 and claims 1-21 of US Patent No. 11, 989, 076. Although the conflicting claims are not identical, they are not patentably distinct from each other because the claims are directed to substantially the same subject matter involving selectively controlling the processing resources based on the workload utilization for the processing resources.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3,21-24,27-30, 33 are rejected under AIA 35 U.S.C. 102(a)(1) as being anticipated by Kaburlasos (US Publication US 20160054782 A1).
Regarding claim 1, Kaburlasos discloses an apparatus [Fig. 5 and/or 6] comprising:
processor circuitry [0110: processor system agent 210] coupled to a memory, the processor circuitry to:
monitor operation states associated with processing resources, wherein to monitor comprises to accumulate state information relating to the operation states and one or more workloads [0125][Fig. 17 and 0128-0131: the precise thresholds for peak and average utilization may be determined dynamically per workload and the thresholds for scaling up and down execution resources can vary] [Fig. 17, step 1704 determining peak utilization (for the active EUs) exceeds threshold][0116-0123][0128-0131][0148-0149];
identify a first operating state associated with a first set of processing resources as being a full operating state [Fig. 17, step 1704 determining peak utilization exceeds threshold (if the active EUs exceeds the peak utilization)][0128-0131][0148-0149]; and in response to identifying the first operating state as being the full operating state, power on a second set of processing resources [0128: if analysis at block 1702 indicates that peak utilization exceeded 80%, for example, within at least two of the monitor windows within the current decision window, the power controller can enable all EUs, as shown at block 1710][0129-0131][0148-0149].
Regarding claim 2, Kaburlasos discloses the apparatus of claim 1, wherein the full operating state relates to a first capacity utilization parameter corresponding to a capacity level threshold indicating a single set of processing resources is capable of processing a workload [0128-0131] [0148-0149].
Regarding claim 3, Kaburlasos does not explicitly disclose the apparatus of claim 1, wherein the first set of processing clusters comprises a plurality of register files [0034][0065][0075].
Regarding claim 7, Kaburlasos discloses the apparatus of claim 1, wherein the processor circuitry is further to: detect the first capacity utilization parameter no longer corresponding to the capacity level threshold; transmit at least a portion of the workload to a second set of processing resources; power on the second set of processing resources; and perform balancing of the power and the workload between the first set of processing resources and the second set of processing resources [0128-0131] [0148-0149].
Regarding claim 21, Kaburlasos discloses the apparatus of claim 1, wherein the processor circuitry comprises one or more of graphics processor circuitry coupled or application processor circuitry [Fig. 1] [0127-0129] [0148-0149].
Regarding claims 22-24, 26-27, these claims are rejected for the same reasons as set forth in claims 1,2,4,7 and 21.
Regarding claims 28-30,32,33, these claims are rejected for the same reasons as set forth in claims 1,2,4,7 and 21.
Response to Arguments
Applicant’s arguments filed on 06/18/2025 have been fully considered but are moot in view of new ground(s) of prior arts rejection because the arguments do not apply to any of the references being used in the current rejection. Examiner noted that there was a typo error and an overlook error in citing the reference, Park (US Patent No. 5524248) in the previous office action. Kaburlasos (US Publication US 20160054782 A1) is the correct reference and was cited in the body of rejected claims of the previous office action. Thus, the final rejection mailed out on 06/18/2025 is withdrawn and new final office action is issued.
The double patenting rejection is still maintained since the terminal disclaimer has not yet filed.
Conclusion
Examiner's note: Examiner has cited particular paragraphs and columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner (see MPEP § 2123).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHIL K NGUYEN whose telephone number is (571)270-3356. The examiner can normally be reached 9:30 a.m - 5 p.m.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at (571)270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PHIL K NGUYEN/Primary Examiner, Art Unit 2176