DETAILED ACTION
This office action is responsive to preliminary amendment filed on 5/6/2024 in this application Hu et al., U.S. Patent Application No. 18/633,961 (Filed April 12, 2024) claiming priority to PCT/CN2022/120324 (Filed 9/21/2022) claiming priority to CN202111196030.0 (filed 10/14/2021) and CN202111667437.7 (filed 12/31/2021). Claims 1 – 3 and 5 – 21 are pending.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) filed on 9/27/2024 and 1/8/2025 are in compliance with the provisions of 37 CFR 1.97, 1.98 and MPEP § 609. The references listed therein have been considered, and placed in the application file.
Claim Rejections 35 U.S.C. §103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 – 3 and 5 – 21 are rejected under 35 U.S.C. 103 as being unpatentable over Arrive, United States Patent Application Publication No. 2021/0034352 (Published February 4, 2021, filed July 22, 2020) (“Arrive”) in view of Raisch et al., United States Patent Application Publication No. 2020/0301699 (Published September 24, 2020, filed March 22, 2019) (“Raisch”).
Claim 1
With respect to claim 1, Arrive teaches the invention as claimed including a method implemented by a data processing unit (DPU) wherein the method comprises:
upgrading a first application program in application programs running on the DPU;… [memory] that is of an internal memory in the DPU {The firmware of a data processing unit is upgraded where the firmware is stored in a memory that is “located on the same electronic chip” as the DPU. Arrive at Abstract; id. at ¶¶ 0035 – 0038.}
However, Arrive doesn’t explicitly teach the limitation:
reading pre-upgrade data of the first application program from a shared storage area … and that is inaccessible to an operating system of the DPU; and restoring a service of the first application program based on the pre-upgrade data. {Raisch does teach this limitation. Raisch teaches that the method for updating a DPU application, as taught in Arrive, may include an application, such as a Code Load, running on a processing core, may be instructed by a separate orchestrating component processor to save its state to its portion of a shared memory, upgrade its application to a new version, and then retrieve the saved state to resume operation, where the data saved and retrieved includes data for processing, memory, and TCP states, and for hardware status including PCI/PCIe and memory communication status. Raisch at Abstract; id. at ¶ 0019 (OC 112 is a separate standalone computer from the cores [DPU] being upgraded); id. at ¶¶ 0024 – 0027 & 0030 – 0033; id. at ¶¶ 0020, 0021, 0029 (PCI and PCIe root complex quiesce and load the shared memory).}
Arrive and Raisch are analogous art because they are from the “same field of endeavor” and are both from the same “problem-solving area.” Specifically, they are both from the field of software updating, and both are trying to solve the problem of how to update processing units.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine updating a DPU application, as taught in Arrive, with saving and restoring state, as taught in Raisch. Raisch teaches that saving and restoring state allows for updates without disruptions. Raisch at ¶ 0009. Therefore, one having ordinary skill in the art would have been motivated to combine updating a DPU application, as taught in Arrive, with saving and restoring state, as taught in Raisch, for the purpose of using a known disruption reducing processor upgrade method with DPU that requires upgrading.}
Claim 2
With respect to claim 2, Arrive and Raisch, teach the invention as claimed including:
wherein before upgrading the first application program, the method further comprises: receiving an upgrade request from a host, wherein the upgrade request indicates to upgrade the first application program; and suspending the service and storing the pre-upgrade data in the shared storage area in response to the upgrade request. {An application, such as a Code Load, running on a processing core, may be instructed by a separate orchestrating component processor to save its state to its portion of a shared memory, upgrade its application to a new version, and then retrieve the saved state to resume operation, where the data saved and retrieved includes data for processing, memory, and TCP states, and for hardware status including PCI/PCIe and memory communication status. Raisch at Abstract; id. at ¶ 0019 (OC 112 is a separate standalone computer from the cores [DPU] being upgraded); id. at ¶¶ 0024 – 0027 & 0030 – 0033; id. at ¶¶ 0020, 0021, 0029 (PCI and PCIe root complex quiesce and load the shared memory).}
Claim 3
With respect to claim 3, Arrive and Raisch, teach the invention as claimed including:
wherein the pre-upgrade data comprises service data of the first application program and a hardware status during running of the first application program before upgrading the first application program. {An application, such as a Code Load, running on a processing core, may be instructed by a separate orchestrating component processor to save its state to its portion of a shared memory, upgrade its application to a new version, and then retrieve the saved state to resume operation, where the data saved and retrieved includes data for processing, memory, and TCP states, and for hardware status including PCI/PCIe and memory communication status. Raisch at Abstract; id. at ¶ 0019 (OC 112 is a separate standalone computer from the cores [DPU] being upgraded); id. at ¶¶ 0024 – 0027 & 0030 – 0033; id. at ¶¶ 0020, 0021, 0029 (PCI and PCIe root complex quiesce and load the shared memory).}
Claim 5
With respect to claim 5, Arrive teaches the invention as claimed including a chip comprising:
a power supply circuit configured to provide power; and an integrated circuit coupled to the power supply circuit and configured to: upgrade a first application program in application programs running on a data processing unit (DPU);… [memory] that is of an internal memory in the DPU {The firmware of a data processing unit is upgraded where the firmware is stored in a memory that is “located on the same electronic chip” as the DPU. Arrive at Abstract; id. at ¶¶ 0035 – 0038.}
However, Arrive doesn’t explicitly teach the limitation:
read pre-upgrade data of the first application program from a shared storage area … and that is inaccessible to an operating system of the DPU; and restore a service of the first application program based on the pre-upgrade data. {Raisch does teach this limitation. Raisch teaches that the method for updating a DPU application, as taught in Arrive, may include an application, such as a Code Load, running on a processing core, may be instructed by a separate orchestrating component processor to save its state to its portion of a shared memory, upgrade its application to a new version, and then retrieve the saved state to resume operation, where the data saved and retrieved includes data for processing, memory, and TCP states, and for hardware status including PCI/PCIe and memory communication status. Raisch at Abstract; id. at ¶ 0019 (OC 112 is a separate standalone computer from the cores [DPU] being upgraded); id. at ¶¶ 0024 – 0027 & 0030 – 0033; id. at ¶¶ 0020, 0021, 0029 (PCI and PCIe root complex quiesce and load the shared memory).}
Arrive and Raisch are analogous art because they are from the “same field of endeavor” and are both from the same “problem-solving area.” Specifically, they are both from the field of software updating, and both are trying to solve the problem of how to update processing units.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine updating a DPU application, as taught in Arrive, with saving and restoring state, as taught in Raisch. Raisch teaches that saving and restoring state allows for updates without disruptions. Raisch at ¶ 0009. Therefore, one having ordinary skill in the art would have been motivated to combine updating a DPU application, as taught in Arrive, with saving and restoring state, as taught in Raisch, for the purpose of using a known disruption reducing processor upgrade method with DPU that requires upgrading.}
Claim 6
With respect to claim 6, Arrive and Raisch, teach the invention as claimed including:
wherein before upgrading the first application program, the integrated circuit is further configured to: receive an upgrade request from a host, wherein the upgrade request indicates to upgrade the first application program; and suspend the service and store the pre-upgrade data in the shared storage area in response to the upgrade request. {An application, such as a Code Load, running on a processing core, may be instructed by a separate orchestrating component processor to save its state to its portion of a shared memory, upgrade its application to a new version, and then retrieve the saved state to resume operation, where the data saved and retrieved includes data for processing, memory, and TCP states, and for hardware status including PCI/PCIe and memory communication status. Raisch at Abstract; id. at ¶ 0019 (OC 112 is a separate standalone computer from the cores [DPU] being upgraded); id. at ¶¶ 0024 – 0027 & 0030 – 0033; id. at ¶¶ 0020, 0021, 0029 (PCI and PCIe root complex quiesce and load the shared memory).}
Claim 7
With respect to claim 7, Arrive and Raisch, teach the invention as claimed including:
wherein the pre-upgrade data comprises service data of the first application program and a hardware status during running of the first application program before upgrading the first application program. {An application, such as a Code Load, running on a processing core, may be instructed by a separate orchestrating component processor to save its state to its portion of a shared memory, upgrade its application to a new version, and then retrieve the saved state to resume operation, where the data saved and retrieved includes data for processing, memory, and TCP states, and for hardware status including PCI/PCIe and memory communication status. Raisch at Abstract; id. at ¶ 0019 (OC 112 is a separate standalone computer from the cores [DPU] being upgraded); id. at ¶¶ 0024 – 0027 & 0030 – 0033; id. at ¶¶ 0020, 0021, 0029 (PCI and PCIe root complex quiesce and load the shared memory).}
Claim 8
With respect to claim 8, Arrive and Raisch, teach the invention as claimed including:
wherein the shared storage area comprises sub-areas, and wherein each of the sub-areas stores service data and a hardware status of one of the application programs. {Applications, such as Code Load applications, running on a processing core, may be instructed by a separate orchestrating component processor to save state to its portion of a shared memory, upgrade to new versions, and then retrieve the saved state to resume operation, where the data saved and retrieved includes data for processing, memory, and TCP states, and for hardware status including PCI/PCIe and memory communication status. Raisch at Abstract; id. at ¶ 0019 (OC 112 is a separate standalone computer from the cores [DPU] being upgraded); id. at ¶¶ 0024 – 0027 & 0030 – 0033; id. at ¶¶ 0020, 0021, 0029 (PCI and PCIe root complex quiesce and load the shared memory); id. at ¶¶ 0015 & 0026 (plurality of portions of memory in the shared memory).}
Claim 9
With respect to claim 9, Arrive teaches the invention as claimed including a data processing unit (DPU) comprising: an internal memory configured to provide a shared storage area … and at least one chip coupled to the internal memory and configured to: upgrade the first application program; {The firmware of a data processing unit is upgraded where the firmware is stored in a memory that is “located on the same electronic chip” as the DPU. Arrive at Abstract; id. at ¶¶ 0035 – 0038.}
However, Arrive doesn’t explicitly teach the limitation:
storing pre- upgrade data of a first application program of application programs, wherein the shared storage area is inaccessible to an operating system of the DPU;… read the pre-upgrade data; and restore a service of the first application program based on the pre-upgrade data. {Raisch does teach this limitation. Raisch teaches that the method for updating a DPU application, as taught in Arrive, may include an application, such as a Code Load, running on a processing core, may be instructed by a separate orchestrating component processor to save its state to its portion of a shared memory, upgrade its application to a new version, and then retrieve the saved state to resume operation, where the data saved and retrieved includes data for processing, memory, and TCP states, and for hardware status including PCI/PCIe and memory communication status. Raisch at Abstract; id. at ¶ 0019 (OC 112 is a separate standalone computer from the cores [DPU] being upgraded); id. at ¶¶ 0024 – 0027 & 0030 – 0033; id. at ¶¶ 0020, 0021, 0029 (PCI and PCIe root complex quiesce and load the shared memory).}
Arrive and Raisch are analogous art because they are from the “same field of endeavor” and are both from the same “problem-solving area.” Specifically, they are both from the field of software updating, and both are trying to solve the problem of how to update processing units.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine updating a DPU application, as taught in Arrive, with saving and restoring state, as taught in Raisch. Raisch teaches that saving and restoring state allows for updates without disruptions. Raisch at ¶ 0009. Therefore, one having ordinary skill in the art would have been motivated to combine updating a DPU application, as taught in Arrive, with saving and restoring state, as taught in Raisch, for the purpose of using a known disruption reducing processor upgrade method with DPU that requires upgrading.}
Claim 10
With respect to claim 10, Arrive and Raisch, teach the invention as claimed including:
wherein before upgrading the pre-upgrade data, the at least one chip is further configured to: receive an upgrade request from a host, wherein the upgrade request indicates to upgrade the first application program; and suspend the service and store the pre-upgrade data in the shared storage area in response to the upgrade request. {An application, such as a Code Load, running on a processing core, may be instructed by a separate orchestrating component processor to save its state to its portion of a shared memory, upgrade its application to a new version, and then retrieve the saved state to resume operation, where the data saved and retrieved includes data for processing, memory, and TCP states, and for hardware status including PCI/PCIe and memory communication status. Raisch at Abstract; id. at ¶ 0019 (OC 112 is a separate standalone computer from the cores [DPU] being upgraded); id. at ¶¶ 0024 – 0027 & 0030 – 0033; id. at ¶¶ 0020, 0021, 0029 (PCI and PCIe root complex quiesce and load the shared memory).}
Claim 11
With respect to claim 11, Arrive and Raisch, teach the invention as claimed including:
wherein the pre-upgrade data comprises service data of the first application program and a hardware status during running of the first application program before upgrading the first application program. {An application, such as a Code Load, running on a processing core, may be instructed by a separate orchestrating component processor to save its state to its portion of a shared memory, upgrade its application to a new version, and then retrieve the saved state to resume operation, where the data saved and retrieved includes data for processing, memory, and TCP states, and for hardware status including PCI/PCIe and memory communication status. Raisch at Abstract; id. at ¶ 0019 (OC 112 is a separate standalone computer from the cores [DPU] being upgraded); id. at ¶¶ 0024 – 0027 & 0030 – 0033; id. at ¶¶ 0020, 0021, 0029 (PCI and PCIe root complex quiesce and load the shared memory).}
Claim 12
With respect to claim 12, Arrive and Raisch, teach the invention as claimed including:
wherein the shared storage area further comprises sub-areas, and wherein each of the sub-areas is configured to store service data and a hardware status of one of the application programs. {Applications, such as Code Load applications, running on a processing core, may be instructed by a separate orchestrating component processor to save state to its portion of a shared memory, upgrade to new versions, and then retrieve the saved state to resume operation, where the data saved and retrieved includes data for processing, memory, and TCP states, and for hardware status including PCI/PCIe and memory communication status. Raisch at Abstract; id. at ¶ 0019 (OC 112 is a separate standalone computer from the cores [DPU] being upgraded); id. at ¶¶ 0024 – 0027 & 0030 – 0033; id. at ¶¶ 0020, 0021, 0029 (PCI and PCIe root complex quiesce and load the shared memory); id. at ¶¶ 0015 & 0026 (plurality of portions of memory in the shared memory).}
Claim 13
With respect to claim 13, Arrive and Raisch, teach the invention as claimed including:
wherein the upgrade request comprises an identifier of the first application program, and wherein the at least one chip is further configured to identify the first application program based on the identifier. {An application, such as a Code Load, running on a processing core, may be instructed by a separate orchestrating component processor to save its state to its portion of a shared memory, upgrade its application to a new version, and then retrieve the saved state to resume operation, where the data saved and retrieved includes data for processing, memory, and TCP states, and for hardware status including PCI/PCIe and memory communication status. Raisch at Abstract; id. at ¶ 0019 (OC 112 is a separate standalone computer from the cores [DPU] being upgraded); id. at ¶¶ 0024 – 0027 & 0030 – 0033; id. at ¶¶ 0020, 0021, 0029 (PCI and PCIe root complex quiesce and load the shared memory).}
Claim 14
With respect to claim 14, Arrive and Raisch, teach the invention as claimed including:
wherein the hardware status comprises a status of a Peripheral Component Interconnect Express (PCIe) bus for connecting the DPU to a host, a status of a hardware channel between the PCIe bus and the internal memory, and a status of a channel between the internal memory and an external device. {An application, such as a Code Load, running on a processing core, may be instructed by a separate orchestrating component processor to save its state to its portion of a shared memory, upgrade its application to a new version, and then retrieve the saved state to resume operation, where the data saved and retrieved includes data for processing, memory, and TCP states, and for hardware status including PCI/PCIe and memory communication status. Raisch at Abstract; id. at ¶ 0019 (OC 112 is a separate standalone computer from the cores [DPU] being upgraded); id. at ¶¶ 0024 – 0027 & 0030 – 0033; id. at ¶¶ 0020, 0021, 0029 (PCI and PCIe root complex quiesce and load the shared memory).}
Claim 15
With respect to claim 15, Arrive and Raisch, teach the invention as claimed including:
wherein after upgrading the first application program, the at least one chip is further configured to send an upgrade completion response to a host to inform that the first application program has been successfully upgraded. {An application, such as a Code Load, running on a processing core, may be instructed by a separate orchestrating component processor to save its state to its portion of a shared memory, upgrade its application to a new version, and then retrieve the saved state to resume operation, where the data saved and retrieved includes data for processing, memory, and TCP states, and for hardware status including PCI/PCIe and memory communication status. Raisch at Abstract; id. at ¶ 0019 (OC 112 is a separate standalone computer from the cores [DPU] being upgraded); id. at ¶¶ 0024 – 0027 & 0030 – 0033; id. at ¶¶ 0020, 0021, 0029 (PCI and PCIe root complex quiesce and load the shared memory).}
Claim 16
With respect to claim 16, Arrive and Raisch, teach the invention as claimed including:
wherein after upgrading the first application program, the method further comprises sending an upgrade completion response to a host to inform that the first application program has been successfully upgraded. {An application, such as a Code Load, running on a processing core, may be instructed by a separate orchestrating component processor to save its state to its portion of a shared memory, upgrade its application to a new version, and then retrieve the saved state to resume operation, where the data saved and retrieved includes data for processing, memory, and TCP states, and for hardware status including PCI/PCIe and memory communication status. Raisch at Abstract; id. at ¶ 0019 (OC 112 is a separate standalone computer from the cores [DPU] being upgraded); id. at ¶¶ 0024 – 0027 & 0030 – 0033; id. at ¶¶ 0020, 0021, 0029 (PCI and PCIe root complex quiesce and load the shared memory).}
Claim 17
With respect to claim 17, Arrive and Raisch, teach the invention as claimed including:
wherein the upgrade request comprises an identifier of the first application program, and wherein the method further comprises identifying the first application program based on the identifier. {An application, such as a Code Load, running on a processing core, may be instructed by a separate orchestrating component processor to save its state to its portion of a shared memory, upgrade its application to a new version, and then retrieve the saved state to resume operation, where the data saved and retrieved includes data for processing, memory, and TCP states, and for hardware status including PCI/PCIe and memory communication status. Raisch at Abstract; id. at ¶ 0019 (OC 112 is a separate standalone computer from the cores [DPU] being upgraded); id. at ¶¶ 0024 – 0027 & 0030 – 0033; id. at ¶¶ 0020, 0021, 0029 (PCI and PCIe root complex quiesce and load the shared memory).}
Claim 18
With respect to claim 18, Arrive and Raisch, teach the invention as claimed including:
wherein the hardware status comprises a status of a Peripheral Component Interconnect Express (PCIe) bus for connecting the DPU to a host, a status of a hardware channel between the PCIe bus and the internal memory, and a status of a channel between the internal memory and an external device. {An application, such as a Code Load, running on a processing core, may be instructed by a separate orchestrating component processor to save its state to its portion of a shared memory, upgrade its application to a new version, and then retrieve the saved state to resume operation, where the data saved and retrieved includes data for processing, memory, and TCP states, and for hardware status including PCI/PCIe and memory communication status. Raisch at Abstract; id. at ¶ 0019 (OC 112 is a separate standalone computer from the cores [DPU] being upgraded); id. at ¶¶ 0024 – 0027 & 0030 – 0033; id. at ¶¶ 0020, 0021, 0029 (PCI and PCIe root complex quiesce and load the shared memory).}
Claim 19
With respect to claim 19, Arrive and Raisch, teach the invention as claimed including:
wherein the upgrade request comprises an identifier of the first application program, and wherein the integrated circuit is further configured to identify the first application program based on the identifier. {An application, such as a Code Load, running on a processing core, may be instructed by a separate orchestrating component processor to save its state to its portion of a shared memory, upgrade its application to a new version, and then retrieve the saved state to resume operation, where the data saved and retrieved includes data for processing, memory, and TCP states, and for hardware status including PCI/PCIe and memory communication status. Raisch at Abstract; id. at ¶ 0019 (OC 112 is a separate standalone computer from the cores [DPU] being upgraded); id. at ¶¶ 0024 – 0027 & 0030 – 0033; id. at ¶¶ 0020, 0021, 0029 (PCI and PCIe root complex quiesce and load the shared memory).}
Claim 20
With respect to claim 20, Arrive and Raisch, teach the invention as claimed including:
wherein the hardware status comprises a status of a Peripheral Component Interconnect Express (PCIe) bus for connecting the DPU to a host, a status of a hardware channel between the PCIe bus and the internal memory, and a status of a channel between the internal memory and an external device. {An application, such as a Code Load, running on a processing core, may be instructed by a separate orchestrating component processor to save its state to its portion of a shared memory, upgrade its application to a new version, and then retrieve the saved state to resume operation, where the data saved and retrieved includes data for processing, memory, and TCP states, and for hardware status including PCI/PCIe and memory communication status. Raisch at Abstract; id. at ¶ 0019 (OC 112 is a separate standalone computer from the cores [DPU] being upgraded); id. at ¶¶ 0024 – 0027 & 0030 – 0033; id. at ¶¶ 0020, 0021, 0029 (PCI and PCIe root complex quiesce and load the shared memory).}
Claim 21
With respect to claim 21, Arrive and Raisch, teach the invention as claimed including:
wherein after upgrading the first application program, the integrated circuit is further configured to send an upgrade completion response to a host to inform that the first application program has been successfully upgraded. {An application, such as a Code Load, running on a processing core, may be instructed by a separate orchestrating component processor to save its state to its portion of a shared memory, upgrade its application to a new version, and then retrieve the saved state to resume operation, where the data saved and retrieved includes data for processing, memory, and TCP states, and for hardware status including PCI/PCIe and memory communication status. Raisch at Abstract; id. at ¶ 0019 (OC 112 is a separate standalone computer from the cores [DPU] being upgraded); id. at ¶¶ 0024 – 0027 & 0030 – 0033; id. at ¶¶ 0020, 0021, 0029 (PCI and PCIe root complex quiesce and load the shared memory).}
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THEODORE E HEBERT whose telephone number is (571)270-1409. The examiner can normally be reached on Monday to Friday 9:00 a.m. to 6:00 p.m..
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//T.H./ February 21, 2026
Examiner, Art Unit 2199
/LEWIS A BULLOCK JR/Supervisory Patent Examiner, Art Unit 2199