DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 10-15, and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kuroki (4,489,279).
Regarding Claim 1 and equivalent method Claim 11, Kuroki teaches in Figure 2 a divide by 3 prescaler for an integrated circuit, the divide by 3 prescaler comprising:
a first logic block configured to generate a first input pulse at a rising edge of a clock signal (13; see also Col. 2, lines 60-63);
a second logic block configured to generate a second input pulse after the first input pulse that ends at a falling edge of the clock signal, the falling edge being for a clock cycle subsequent to the rising edge (14 and 15; see also Col. 2, line 63 through Col. 3, line 3); and
a third logic block coupled to the first input pulse and the second input pulse and configured to generate a divide by 3 clock output (16).
Regarding Claims 2 and 12, Kuroki further teaches the divide by 3 prescaler, wherein the third logic block comprises an OR gate that is configured to generate the divide by 3 clock output in response to either or both of the first input pulse and the second input pulse (where 16 receives the outputs from 13 and from 15).
Regarding Claims 3 and 13, Kuroki further teaches the divide by 3 prescaler, wherein the first logic block is configured to generate the first input pulse as going high at the rising edge and then low on a rising edge of a next clock cycle (using 31-33 within 13).
Regarding Claims 4 and 14, Kuroki further teaches the divide by 3 prescaler, wherein the second logic block is configured to generate the second input pulse as going high at the falling edge and then low on a falling edge of a next clock cycle (using the elements within the configuration of 14 and 15, where 41 is connected to B).
Regarding Claims 5 and 15, Kuroki further teaches the divide by 3 prescaler, wherein the third logic block comprises an OR gate that is configured to generate a high when either or both of the first input pulse and the second input pulse are high (using OR gate 16).
Regarding Claim 10, Kuroki further teaches the divide by 3 prescaler, wherein the second input pulse is delayed by a half cycle of the clock signal with respect to the first input pulse (using at least 31).
Regarding Claim 18, Kuroki teaches in Figure 2 a divide by 3 prescaler for an integrated circuit, the divide by 3 prescaler comprising:
a first logic block configured to generate a first input pulse in response to a clock signal (13; see also Col. 2, lines 60-63);
a second logic block configured to generate a second input pulse delayed after the first input pulse by a half cycle of the clock signal (14 and 15; see also Col. 2, line 63 through Col. 3, line 3); and
a third logic block coupled to the first input pulse and the second input pulse and configured to odd divide the clock signal in response to the first input pulse and the second input pulse to generate a divide by 3 clock output (16).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6, 7, 16, 17, 19, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuroki (4,489,279), as applied to claims 1, 11, and 18 above, and further in view of Chen (US 7,012,455 B2).
Regarding Claims 6 and 16, Kuroki further teaches the divide by 3 prescaler, wherein the first logic block comprises a first flip-flop configured to generate the first input pulse in response to the clock signal (using 31 of 13),
but does not explicitly teach a second flip-flop configured to generate a feedback signal to a D input of the first flip-flop in response to the clock signal.
Chen teaches a frequency divider, wherein the first logic block (34) comprising a first flip-flop configured to generate the first input pulse (62) and a second flip-flop configured to generate a feedback signal to a D input of the first flip-flop in response to the clock signal (66).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the configuration of 34 of Chen in place of the configuration of 13 of Kuroki for the purpose of utilizing “means of different combinations of the three edge-triggered clock generators within the dividing circuits”. Chen: Col. 5, lines 8-10.
Regarding Claims 7 and 17, Kuroki and Chen, as a whole, teach all the limitations of the present invention, wherein Chen further teaches the divide by 3 prescaler, wherein the first input pulse of the first flip-flop is coupled to a D input of the second-flip-flop through a NOR gate (62 is connected to 66 though NOR gate 64),
the NOR gate (64) configured to receive the first input pulse (from Q of 62) and the feedback signal and to generate a high to a D input of the second flip-flop in response thereto (from Q of 66).
Regarding Claim 19, Kuroki teaches all the limitations of the present invention, but does not explicitly teach the divide by 3 prescaler, wherein the second logic block uses an inverse clock signal that is generated from the clock signal.
Chen teaches in Figure 3 a first logic block (34) and a second logic block (36), wherein the second logic block uses an inverse clock signal that is generated from the clock signal (where the clock input of 72, 76, and 78 are inverted from those of 62, 66, and 68).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use clock input teachings of flip-flops in Chen with the flip-flops of Kuroki for the purpose of utilizing “means of different combinations of the three edge-triggered clock generators within the dividing circuits”. Chen: Col. 5, lines 8-10.
Regarding Claim 20, Kuroki and Chen, as a whole, teach all the limitations of the present invention, and further teaches the divide by 3 prescaler, wherein the second logic block operates with a delay of the half cycle of the clock signal with respect to the first logic block (see inverted clock inputs of Chen’s flip-flops).
Allowable Subject Matter
Claims 8 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 8, the prior art does not disclose, teach or suggest the divide by 3 prescaler, wherein the second logic block comprises a third flip-flop configured to generate the second input pulse in response to an inverse clock signal and a fourth flip-flop configured to generate a feedback signal to a D input of the third flip-flop in response to the inverse clock signal;
in combination with all the other claimed limitations.
Claim 9 is objected to for depending from Claim 8.
Contact
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Diana J Cheng whose telephone number is (571)270-1197. The examiner can normally be reached Monday - Friday 9 am - 5:30 pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at (571)270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DIANA J. CHENG/Primary Examiner, Art Unit 2849