DETAILED ACTION
This office action is responsive to communication filed on January 2, 2026.
Response to Arguments
Applicant's arguments filed January 2, 2026 have been fully considered but they are not persuasive.
Applicant argues, with respect to claims 1 and 18, that Takahashi does not teach the claimed binning circuit operation that includes a first mode electrically connecting each photodetector to a single readout circuit (of multiple readout circuits) such that each photodetector operates as an independent intensity pixel and a second mode electrically connecting multiple photodetectors to a single readout circuit (of multiple readout circuits) to in combination perform event detection as a single contrast change pixel.
The Examiner respectfully disagrees. Takahashi teaches that the binning circuit (32) operation includes a first mode electrically connecting each photodetector (61) to a single readout circuit (53) such that each photodetector (61) operates as an independent intensity pixel (The first mode electrically connects a single photodetector (61) to the pixel signal generation section (53) via a transfer transistor (63), paragraphs 0074, 0083, 0129 and 0132, see figures 4 and 8. For instance, at T3 of figure 8, TRG1 is pulsed, which connects a single photodetector (61) to a single readout circuit (53), such that the single photodetector (61) operates as an independent intensity pixel. After that, at T4 of figure 8, TRG2 is pulsed, which connects a single photodetector (61) to a single readout circuit (53), such that the single photodetector (61) operates as an independent intensity pixel.), and a second mode electrically connecting multiple photodetectors (61) to a single readout circuit (52) to in combination perform event detection as a single contrast change pixel (The second mode electrically connects more than one photodetector (61) to the event detecting section (52) via transfer transistors (62), paragraphs 0073, 0075, 0082 and 0126, see figures 4 and 8. For instance, at T0 of figure 8, both OFG1 and OFG2 are pulsed high, electrically connecting two photodetectors (61) to a single readout circuit (52) to in combination perform event detection as a single contrast change pixel.).
Therefore, the rejection is maintained by the Examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 6-10, 15-19 and 21-23 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Takahashi (US 2022/0038645).
Consider claim 1, Takahashi teaches:
An event image sensor (see figures 2-4) comprising:
a matrix arrangement (pixel array section, 31, paragraph 0055) of a plurality of pixels (pixel, 51, figure 3, paragraph 0064), comprising:
a plurality of photodetectors (photoelectric conversion element, 61, figure 4) configured to receive light from a physical environment (see paragraph 0072), each photodetector (61) corresponding to one of the pixels (51, see figure 4);
a plurality of readout circuits (The pixel array section (31) includes a plurality of pixel blocks (41, see figure 3), paragraph 0064. Each pixel block (41) includes an event detecting section (52, i.e. a readout circuit) and a pixel signal generating section (53, i.e. a readout circuit), paragraph 0064, see figure 3. The pixel array section (31) is part of a sensor section (21) which is embodied in a “circuit”, paragraph 0048.), each of the readout circuits (52, 53) configured to receive pixel data to detect a change in light intensity exceeding a threshold detected by a photodetector (“The event detecting section 52 detects, as an event, a change larger than the predetermined threshold in photocurrent from each of the pixels 51, under the control of the driving section 32.” paragraphs 0066 and 0075); and
a binning circuit (The sensor section (21) includes a driving section (32) which supplies control signals to the pixel array section (31), paragraph 0056, figure 2. The sensor section (21) is embodied in a “circuit”, paragraph 0048.) configured to operate in a first mode and a second mode (see below), wherein the binning circuit (32) in the first mode is configured to electrically connect each photodetector (61) of the plurality of photodetectors to a single readout circuit (53) of the plurality of readout circuits (52, 53) such that each said photodetector (61) operates as an independent intensity pixel (The first mode electrically connects a single photodetector (61) to the pixel signal generation section (53) via a transfer transistor (63), paragraphs 0074, 0083, 0129 and 0132, see figures 4 and 8. For instance, at T3 of figure 8, TRG1 is pulsed, which connects a single photodetector (61) to a single readout circuit (53), such that the single photodetector (61) operates as an independent intensity pixel. After that, at T4 of figure 8, TRG2 is pulsed, which connects a single photodetector (61) to a single readout circuit (53), such that the single photodetector (61) operates as an independent intensity pixel.), and wherein the binning circuit (32) in the second mode is configured to electrically connect more than one photodetector (61) of the plurality of photodetectors to a single readout circuit (52) of the plurality of readout circuits (52, 53) to, in combination, perform event detection as a single contrast change pixel (The second mode electrically connects more than one photodetector (61) to the event detecting section (52) via transfer transistors (62), paragraphs 0073, 0075, 0082 and 0126, see figures 4 and 8. For instance, at T0 of figure 8, both OFG1 and OFG2 are pulsed high, electrically connecting two photodetectors (61) to a single readout circuit (52) to in combination perform event detection as a single contrast change pixel.).
Consider claim 2, and as applied to claim 1 above, Takahashi further teaches that the binning circuit (32) is configured to electrically connect the plurality of photodetectors (61) to the single readout circuit (52, 53) in the second mode (i.e. to electrically connect more than one photodetector (61) to the event detecting section (52) via transfer transistors (62), paragraphs 0073, 0075, 0082 and 0126, see figures 4 and 8).
Consider claim 3, and as applied to claim 1 above, Takahashi further teaches that each said photodetector (61) is respectively read out by sequentially enabling first readout transistors (63) of the plurality of readout circuits (i.e. to electrically connect a single photodetector (61) to the pixel signal generation section (53) via a transfer transistor (63), paragraphs 0074, 0083, 0129 and 0132, see figures 4 and 8).
Consider claim 4, and as applied to claim 3 above, Takahashi further teaches that each said photodetector (61) is respectively read out by sequentially enabling the first readout transistors (63) subsequent to an integration period (i.e. to electrically connect a single photodetector (61) to the pixel signal generation section (53) via a transfer transistor (63) subsequent to an integration period ending at T3 in figure 8, paragraphs 0074, 0083, 0129 and 0132, see figures 4 and 8), wherein a charge accumulated by the plurality of photodetectors (61) during the integration period is buffered by a source follower transistor (amplification transistor, 72) prior to being transferred to a column bus (VSL) (“The amplification transistor 72 is a source follower and outputs a voltage (electrical signal) corresponding to the voltage of the FD 74 supplied to the gate to the VSL through the selection transistor 73.” paragraphs 0079 and 0083).
Consider claim 6, and as applied to claim 1 above, Takahashi further teaches that the plurality of pixels are configured to utilize a plurality of time-sequenced output paths in the first mode (i.e. to electrically connect single photodetectors (61) to the pixel signal generation section (53) via output paths of transfer transistors (63), paragraphs 0074, 0083, 0129 and 0132, see figures 4 and 8).
Consider claim 7, and as applied to claim 1 above, Takahashi further teaches that the plurality of photodetectors (61) are configured to operate multiple independent intensity pixels (51, see figure 4).
Consider claim 8, and as applied to claim 1 above, Takahashi further teaches that the plurality of photodetectors (61) are respectively connected through a conductive readout path to a DVS back-end (event detecting section, 52, figure 4) in the second mode (i.e. to electrically connect more than one photodetector (61) to the event detecting section (52) via transfer transistors (62), paragraphs 0073, 0075, 0082 and 0126, see figures 4 and 8).
Consider claim 9, and as applied to claim 8 above, Takahashi further teaches that a photocurrent from the plurality of photodetectors (61) is continuously output to the DVS back-end (52) in the second mode (i.e. to electrically connect more than one photodetector (61) to the event detecting section (52) via transfer transistors (62) continuously until an event is detected, paragraphs 0073, 0075, 0082, 0126 and 0127, see figures 4 and 8).
Consider claim 10, and as applied to claim 9 above, Takahashi further teaches that the photocurrent from the photodetectors (61) is continuously output to the DVS back-end (52) in the second mode by concurrently enabling a plurality of second readout transistors of the plurality of readout circuits (i.e. to electrically concurrently connect more than one photodetector (61) to the event detecting section (52) via transfer transistors (62) continuously until an event is detected, paragraphs 0073, 0075, 0082, 0126 and 0127, see figures 4 and 8).
Consider claim 15, and as applied to claim 1 above, Takahashi further teaches that the event image sensor uses a first resolution in the first mode (i.e. by reading out each photodiode (61) separately, paragraphs 0074, 0083, 0129 and 0132, see figures 4 and 8), and a second resolution in the second mode (i.e. by binning the charges from multiple photodiodes (61) through concurrent readout, paragraphs 0073, 0075, 0082 and 0126, see figures 4 and 8), wherein the first resolution is greater than the second resolution (i.e. due to signals from all photodiodes being individually read in the first mode, and signals from multiple photodiodes being binned into a single output in the second mode).
Consider claim 16, and as applied to claim 1 above, Takahashi further teaches that a first terminal of each said photodetector (61) is coupled to a ground voltage (see figure 4).
Consider claim 17, and as applied to claim 1 above, Takahashi further teaches that each said photodetector (61) is connected to a differing set of readout transistors of the plurality of readout circuits (See figure 4. Each photodiode (61) is connected to its own set of readout transistors (62, 63).).
Consider claim 21, and as applied to claim 1 above, Takahashi further teaches that the binning circuit (32) is operated in the second mode during low contrast conditions where photocurrent generated by a single photodetector (61) of the plurality of photodetectors is insufficient to generate events at a dynamic vision sensor (DVS) back-end but photocurrent from the plurality of photodetectors is sufficient to generate events at the DVS back-end (When performing event detection, the binning circuit (32) is always operated in the second mode by changing all of the control signals (OFGn) from low to high, paragraph 0126, see figure 8. This would include times during low contrast conditions where photocurrent generated by a single photodetector (61) of the plurality of photodetectors is insufficient to generate events at a dynamic vision sensor (DVS) back-end but photocurrent from the plurality of photodetectors is sufficient to generate events at the DVS back-end.).
Consider claim 22, and as applied to claim 1 above, Takahashi further teaches that the binning circuit (32) operated in the second mode is configured to sum photocurrent of the plurality of photodetectors (61) into a single amplifier (As detailed in paragraph 0126, “the sum of photocurrents from all the pixels 51 in the pixel block 41 is supplied to the event detecting section 52”. The event detection section (52) includes a single amplifier (operational amplifier, 102, figure 7), paragraphs 0105 and 0091.).
Consider claim 23, and as applied to claim 1 above, Takahashi further teaches that the binning circuit (32) operated in the first mode is configured to enable correlated double sampling (CDS) to reduce fixed pattern noise (See “CDS”, paragraphs 0130 and 0131).
Consider claim 18, Takahashi teaches:
A method comprising:
at an event image sensor (see figures 2-4) having a matrix arrangement (pixel array section, 31, paragraph 0055) of a plurality of pixels (pixel, 51, figure 3, paragraph 0064) comprising a plurality of photodetectors (photoelectric conversion element, 61, figure 4), a plurality of readout circuits (The pixel array section (31) includes a plurality of pixel blocks (41, see figure 3), paragraph 0064. Each pixel block (41) includes an event detecting section (52, i.e. a readout circuit) and a pixel signal generating section (53, i.e. a readout circuit), paragraph 0064, see figure 3. The pixel array section (31) is part of a sensor section (21) which is embodied in a “circuit”, paragraph 0048.), and a binning circuit (The sensor section (21) includes a driving section (32) which supplies control signals to the pixel array section (31), paragraph 0056, figure 2. The sensor section (21) is embodied in a “circuit”, paragraph 0048.):
receiving, via the plurality of photodetectors (61), light from a physical environment (see paragraph 0072), each photodetector (61) corresponding to one of the pixels (see figure 4);
receiving, via each readout circuit of the plurality of readout circuits (52, 53), pixel data to detect a change in light intensity exceeding a threshold detected by a photodetector (“The event detecting section 52 detects, as an event, a change larger than the predetermined threshold in photocurrent from each of the pixels 51, under the control of the driving section 32.” paragraphs 0066 and 0075);
operating the binning circuit (32) in a first mode to electrically connect each photodetector (61) of the plurality of photodetectors to a single readout circuit (53) of the plurality of readout circuits (52, 53) such that each said photodetector (61) operates as an independent intensity pixel (The first mode electrically connects a single photodetector (61) to the pixel signal generation section (53) via a transfer transistor (63), paragraphs 0074, 0083, 0129 and 0132, see figures 4 and 8. For instance, at T3 of figure 8, TRG1 is pulsed, which connects a single photodetector (61) to a single readout circuit (53), such that the single photodetector (61) operates as an independent intensity pixel. After that, at T4 of figure 8, TRG2 is pulsed, which connects a single photodetector (61) to a single readout circuit (53), such that the single photodetector (61) operates as an independent intensity pixel.); and
operating the binning circuit (32) in a second mode to electrically connect more than one photodetector (61) of the plurality of photodetectors to a single readout circuit (52) of the plurality of readout circuits (52, 53) to, in combination, perform event detection as a single contrast change pixel (The second mode electrically connects more than one photodetector (61) to the event detecting section (52) via transfer transistors (62), paragraphs 0073, 0075, 0082 and 0126, see figures 4 and 8. For instance, at T0 of figure 8, both OFG1 and OFG2 are pulsed high, electrically connecting two photodetectors (61) to a single readout circuit (52) to in combination perform event detection as a single contrast change pixel.).
Consider claim 19, and as applied to claim 18 above, Takahashi further teaches electrically connecting the plurality of photodetectors (61) to the single readout circuit (52, 53) in the second mode (i.e. to electrically connect more than one photodetector (61) to the event detecting section (52) via transfer transistors (62), paragraphs 0073, 0075, 0082 and 0126, see figures 4 and 8).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 5 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Takahashi (US 2022/0038645) in view of Tsuchimoto et al. (US 2024/0015412).
Consider claims 5 and 20, and as applied to claims 1 and 18 above, Takahashi teaches that said plurality of photodetectors may be covered by color filters (“Note that, the pixel 51 can receive any light as incident light with an optical filter through which predetermined light passes, such as a color filter.” paragraph 0124).
However, Takahashi does not explicitly teach that the color filters for a repeating Bayer pattern.
Tsuchimoto et al. similarly teaches an event image sensor (figures 3 and 4) having pixels (51) including photodetectors (61).
However, Tsuchimoto et al. additionally teaches that said plurality of photodetectors (61) form a repeating Bayer pattern of pixels (see figure 19, paragraphs 0256-0260).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the plurality of photodetectors taught by Takahashi form a repeating Bayer pattern of pixels as taught by Tsuchimoto et al. for the benefit of enabling reproduction of the coloring of the subject from which the pixels with the occurrence of events have received the light (Tsuchimoto et al., paragraph 0269).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Takahashi (US 2022/0038645) in view of Bencuya et al. (US 2005/0128327).
Consider claim 14, and as applied to claim 1 above, Takahashi does not explicitly teach that the event image sensor is used in low light conditions.
Bencuya et al. similarly teaches an image sensor (figure 1) including a plurality of photodetectors (122, 124, 126, 128, paragraph 0023) coupled to a single readout circuit (shared readout circuit, 102, paragraph 0023).
However, Bencuya et al. additionally teaches that this image sensor is used in low light conditions (“may provide increased low light level sensitivity” paragraph 0041).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the event image sensor taught by Takahashi be used in low light conditions as taught by Bencuya et al. for the benefit of enabling capture of low light images with increased sensitivity (Bencuya et al., paragraph 0041).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALBERT H CUTLER whose telephone number is (571)270-1460. The examiner can normally be reached approximately Mon - Fri 8:00-4:30.
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/ALBERT H CUTLER/Primary Examiner, Art Unit 2637