Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
1. This Office Action is responsive to the communication filed 2/3/2026.
Claim Status
2. Claims 1-2, 4-8, 10-11, 13-14, 16-17, and 20 have been amended.
Allowable Subject Matter
3. Claims 8-9, 17, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Objections
4. Claims 1-2, 10-11, and 20 are objected to for the following minor informalities:
Line 11 of claim 1, line 10 of claim 10, and line 11 of claim 20 should be amended to --a plurality of encoding operations--.
Line 1 of claims 1-2 should be amended to include a colon after “wherein”.
Response to Arguments
5. The applicant’s arguments filed on 2/3/2026 have been take into consideration, but are moot in view of new grounds of rejection.
A. The previous rejection under 35 USC 101 has been withdrawn in light of the amended claim language.
B. In response to the applicant’s argument (disclosed on pg. 2-3 of the remarks segment) that the previously cited prior art fails to teach or suggest a security circuit configured to generate permutation data by performing a permutation operation including a mixcolumn multiplication operation on the shift data based on a plurality of encoding operation under control of the encryption controller circuit:
In light of the amended claim language, previously cited prior art reference Ghosh (US 2024/0259182) has been cited, which discloses (in fig. 4, ‘400/‘412/’426, par [0030], lines 5-10, and par [0034], lines 5-20 of Ghosh) encryption circuitry (e.g., encryption controller circuit) including a multiplexer and a mix-column unit that processes data input from a shift row, via first and second state register over a plurality of cryptographic rounds (e.g., a security circuit configured to generate permutation data by performing a permutation operation including a mixcolumn multiplication operation on the shift data based on a plurality of encoding operation under control of the encryption controller circuit).
Claim Rejections – 35 USC 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office Action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claims 1-3, 5-6, 10-12, 14-15, and 20-21 are rejected under 35 USC 103 as being unpatentable over Park (KR 20180021473 A) in view of Komano et al (US 2007/0140478), further in view of Ghosh (US 2024/0259182).
Regarding claim 1, Park teaches an encryption device (Abstract), comprising:
an encryption core circuit configured to generate output data by performing an encryption operation on input data (Abstract, “encryption core…outputting an encrypted result”); and
an encryption controller circuit configured to control an operation of the encryption core circuit (pg. 4, lines 36-37 and pg. 5, lines 1-15, which disclose input and output control logic to distribute data to and from encryption cores),
wherein the encryption core circuit comprises:
a shiftrow circuit configured to generate shift data by performing a shiftrow operation on the input data (pg. 3, lines 16-20, “shift-row operation” & pg. 4, lines 1-15, “shiftrow logic”);
a security circuit configured to generate permutation data by performing a permutation operation including a mixcolumn multiplication operation on the shift data (pg. 3, lines 16-25, which discloses performing a Mixcolumns operation on a shift-row operation); and
a round key addition operation circuit (pg. 4, lines 15-25, “round key addition logic”) configured to generate the output data by performing a round key addition operation on the first mid data (pg. 3, lines 10-20, “round key addition operation”).
Park does not explicitly teach a mixcolumn addition circuit configured to generate first mid data by performing a mixcolumn addition operation on the permutation data.
However, Komano et al teaches a mixcolumn addition circuit configured to generate first mid data by performing a mixcolumn addition operation on the permutation data (par [0110], which discloses adding circuits being implemented to execute MixColumn operations).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Komano et al within the disclosure of Park in order to provide the predictive result of improving security by using a different mask in each cryptographic round to prevent leakage of masked value data (as disclosed in par [0038], par [0054] & par [0077] of Komano et al) because this feature eliminated the possibility of fraudulently exposing fixed values by way of reverse engineering.
Park and Komano et al do not explicitly teach performing a permutation operation including a mixcolumn multiplication operation on the shift data based on a plurality of encoding operations under control of the encryption controller circuit.
However, Ghosh teaches performing the permutation operation including a mixcolumn multiplication operation on the shift data based on a plurality of encoding operations under control of the encryption controller circuit (fig. 4, ‘400/‘412/’426, par [0030], lines 5-10, and par [0034], lines 5-20, which disclose encryption circuitry including a multiplexer and a mix-column unit that processes data input from a shift row, via first and second state register over a plurality of cryptographic rounds).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Ghosh within the teachings of Park and Komano et al in order to provide the predictive result of improving prevention of potential attacks by upgrading from an AES-126 to an AES-256 implemented environment (as disclosed in par [0001], lines 7-15 of Ghosh) because this feature allows for more in depth security in environments where high volume, data driven artificial intelligence (AI) applications require increasingly high bandwidth.
Regarding claim 2, Park does not explicitly teach wherein the security circuit comprises a plurality of sub security circuits configured to receive any one of a plurality of pieces of sub shift data generated by dividing the shift data, and generate any one of a plurality of pieces of multiplication data included in sub permutation data by performing the permutation operation on the sub shift data, wherein the permutation operation includes the mixcolumn multiplication operation on any one of a plurality of mixcolumn multiplication values, and the permutation data includes a plurality of pieces of the sub permutation data.
However, Komano et al teaches wherein the security circuit comprises a plurality of sub security circuits configured to receive any one of a plurality of pieces of sub shift data generated by dividing the shift data (par [0100], “Shift-Row…divided 8-bit data block”), and generate any one of a plurality of pieces of multiplication data included in sub permutation data by performing the permutation operation on the sub shift data (par [0053], lines 10-20, “initial permutation…expansion permutation…final permutation” & par [0070], “Shift-Row executed cyclic permutation”),
wherein the permutation operation includes the mixcolumn multiplication operation on any one of a plurality of mixcolumn multiplication values (par [0072], “multiplying circuit…MixColumn”), and
the permutation data includes a plurality of pieces of the sub permutation data (fig. 7, ‘807/’809).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Komano et al within the disclosure of Park according to the motivation disclosed regarding claim 1.
Regarding claim 3, Park does not explicitly teach wherein the sub shift data received by each of the plurality of sub security circuits is different from each other, or each of the plurality of sub security circuits performs the permutation operation on the mixcolumn multiplication values different from each other, wherein the permutation operation includes the mixcolumn multiplication operation.
However, Komano et al teaches wherein the sub shift data received by each of the plurality of sub security circuits is different from each other, or each of the plurality of sub security circuits performs the permutation operation on the mixcolumn multiplication values different from each other (par [0031], lines 1-4 and par [0077], “different mask random numbers in rounds”),
wherein the permutation operation includes the mixcolumn multiplication operation (par [0070]).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Komano et al within the disclosure of Park according to the motivation disclosed regarding claim 1.
Regarding claim 5, Park does not explicitly teach wherein the security circuit comprises a plurality of sub security circuits configured to receive any one of a plurality of pieces of sub shift data generated by dividing the shift data, and generate sub permutation data including a plurality of pieces of multiplication data by performing the permutation operation including the mixcolumn multiplication operation on the sub shift data, the permutation data includes a plurality of pieces of the sub permutation data, each of the plurality of pieces of multiplication data is generated by performing the permutation operation on the sub shift data, and the permutation operation includes the mixcolumn multiplication operation on any one of a plurality of mixcolumn multiplication values.
However, Komano et al teaches wherein the security circuit comprises a plurality of sub security circuits configured to receive any one of a plurality of pieces of sub shift data generated by dividing the shift data (par [0025-0027]), and generate sub permutation data including a plurality of pieces of multiplication data by performing the permutation operation including the mixcolumn multiplication operation on the sub shift data (par [0069-0070] & par [0072]),
the permutation data includes a plurality of pieces of the sub permutation data (par [0034], lines 10-15, “subjected to initial permutation and divided into 32-bit data”),
each of the plurality of pieces of multiplication data is generated by performing the permutation operation on the sub shift data (par [0034], lines 10-20, “initial permutation”), and
the permutation operation includes the mixcolumn multiplication operation on any one of a plurality of mixcolumn multiplication values (par [0070], “MixColumn executes”).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Komano et al within the disclosure of Park in order to provide the predictive result of improving security by using a different mask in each cryptographic round to prevent leakage of masked value data (as disclosed in par [0038], par [0054] & par [0077] of Komano et al) because this feature eliminated the possibility of fraudulently exposing fixed values by way of reverse engineering.
Regarding claim 6, Park does not explicitly teach wherein the sub shift data received by each of the plurality of sub security circuits is different from each other.
However, Komano et al teaches wherein the sub shift data received by each of the plurality of sub security circuits is different from each other (par [0085], lines 1-6, processing is changed…”).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Komano et al within the disclosure of Park according to the motivation disclosed regarding claim 5.
Regarding claim 10, Park teaches an encryption device (Abstract), comprising:
an encryption core circuit configured to generate output data (Abstract, “encryption core…outputting an encrypted result”) by performing a plurality of round operations on input data (pg. 3, lines 10-20, “repeating several rounds”); and
an encryption controller circuit configured to control the encryption core circuit (pg. 4, lines 36-37 and pg. 5, lines 1-15, which disclose input and output control logic to distribute data to and from encryption cores) to sequentially perform the plurality of round operations including an initial round operation (pg. 3, lines 5-15, “repeating several rounds”), an iterative round operation of a preset reference number of times (pg. 3, lines 10-20, “N-1 rounds”), and a final round operation (pg. 3, lines 27-31, “processing of the Nth round is completed”),
wherein the encryption core circuit comprises a shiftrow circuit configured to generate shift data by performing a shiftrow operation on the input data (pg. 3, lines 16-20, “shift-row operation” & pg. 4, lines 1-15, “shiftrow logic”), a security circuit configured to generate permutation data by performing a permutation operation including a mixcolumn multiplication operation on the shift data (pg. 3, lines 16-25, “Mixcolumns operation”), and a round key addition operation circuit (pg. 4, lines 15-25, “round key addition logic”) configured to generate the output data by performing a round key addition operation on the first mid data (pg. 3, lines 10-20, “round key addition operation”), and
the iterative round operation includes the shiftrow operation (pg. 4, lines 1-10,), the mixcolumn addition operation (pg. 4, lines 1-10,), and the round key addition operation (pg. 3, lines 27-31, “AddRoundKey operation”).
Park does not explicitly teach a mixcolumn addition circuit configured to generate first mid data by performing a mixcolumn addition operation on the permutation data and the iterative round operation including the permutation operation.
However, Komano et al teaches a mixcolumn addition circuit configured to generate first mid data by performing a mixcolumn addition operation on the permutation data (par [0110], which discloses adding circuits being implemented to execute MixColumn operations) and the iterative round operation including the permutation operation (fig. 7, “initial permutation…final permutation”).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Komano et al within the disclosure of Park in order to provide the predictive result of improving security by using a different mask in each cryptographic round to prevent leakage of masked value data (as disclosed in par [0038], par [0054] & par [0077] of Komano et al) because this feature eliminated the possibility of fraudulently exposing fixed values by way of reverse engineering.
Park and Komano et al do not explicitly teach performing a permutation operation including a mixcolumn multiplication operation on the shift data based on a plurality of encoding operations under control of the encryption controller circuit.
However, Ghosh teaches performing the permutation operation including a mixcolumn multiplication operation on the shift data based on a plurality of encoding operations under control of the encryption controller circuit (fig. 4, ‘400/‘412/’426, par [0030], lines 5-10, and par [0034], lines 5-20, which disclose encryption circuitry including a multiplexer and a mix-column unit that processes data input from a shift row, via first and second state register over a plurality of cryptographic rounds).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Ghosh within the teachings of Park and Komano et al in order to provide the predictive result of improving prevention of potential attacks by upgrading from an AES-126 to an AES-256 implemented environment (as disclosed in par [0001], lines 7-15 of Ghosh) because this feature allows for more in depth security in environments where high volume, data driven artificial intelligence (AI) applications require increasingly high bandwidth.
Regarding claim 11, Park does not explicitly teach wherein the security circuit comprises a plurality of sub security circuits configured to receive any one of a plurality of pieces of sub shift data generated by dividing the shift data, and generate any one of a plurality of pieces of multiplication data included in sub permutation data by performing the permutation operation on the sub shift data, wherein the permutation operation includes the mixcolumn multiplication operation on any one of a plurality of mixcolumn multiplication values, and the permutation data includes a plurality of pieces of the sub permutation data.
However, Komano et al teaches wherein the security circuit comprises a plurality of sub security circuits configured to receive any one of a plurality of pieces of sub shift data generated by dividing the shift data (par [0100], “Shift-Row…divided 8-bit data block”), and generate any one of a plurality of pieces of multiplication data included in sub permutation data by performing the permutation operation on the sub shift data (par [0053], lines 10-20, “initial permutation…expansion permutation…final permutation” & par [0070], “Shift-Row executed cyclic permutation”),
wherein the permutation operation includes the mixcolumn multiplication operation on any one of a plurality of mixcolumn multiplication values (par [0072], “multiplying circuit…MixColumn”), and
the permutation data includes a plurality of pieces of the sub permutation data (fig. 7, ‘807/’809).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Komano et al within the disclosure of Park according to the motivation disclosed regarding claim 10.
Regarding claim 12, Park does not explicitly teach wherein the sub shift data received by each of the plurality of sub security circuits is different from each other, or each of the plurality of sub security circuits performs the permutation operation on the mixcolumn multiplication values different from each other, wherein the permutation operation includes the mixcolumn multiplication operation.
However, Komano et al teaches wherein the sub shift data received by each of the plurality of sub security circuits is different from each other, or each of the plurality of sub security circuits performs the permutation operation on the mixcolumn multiplication values different from each other (par [0031], lines 1-4 and par [0077], “different mask random numbers in rounds”),
wherein the permutation operation includes the mixcolumn multiplication operation (par [0070]).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Komano et al within the disclosure of Park according to the motivation disclosed regarding claim 10.
Regarding claim 14, Park does not explicitly teach wherein the security circuit comprises a plurality of sub security circuits configured to receive any one of a plurality of pieces of sub shift data generated by dividing the shift data, and generate sub permutation data including a plurality of pieces of multiplication data by performing the permutation operation including the mixcolumn multiplication operation on the sub shift data, the permutation data includes a plurality of pieces of the sub permutation data, each of the plurality of pieces of multiplication data is generated by performing the permutation operation on the sub shift data, and the permutation operation includes the mixcolumn multiplication operation on any one of a plurality of mixcolumn multiplication values.
However, Komano et al teaches wherein the security circuit comprises a plurality of sub security circuits configured to receive any one of a plurality of pieces of sub shift data generated by dividing the shift data (par [0025-0027]), and generate sub permutation data including a plurality of pieces of multiplication data by performing the permutation operation including the mixcolumn multiplication operation on the sub shift data (par [0069-0070] & par [0072]),
the permutation data includes a plurality of pieces of the sub permutation data (par [0034], lines 10-15, “subjected to initial permutation and divided into 32-bit data”),
each of the plurality of pieces of multiplication data is generated by performing the permutation operation on the sub shift data (par [0034], lines 10-20, “initial permutation”), and
the permutation operation includes the mixcolumn multiplication operation on any one of a plurality of mixcolumn multiplication values (par [0070], “MixColumn executes”).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Komano et al within the disclosure of Park in order to provide the predictive result of improving security by using a different mask in each cryptographic round to prevent leakage of masked value data (as disclosed in par [0038], par [0054] & par [0077] of Komano et al) because this feature eliminated the possibility of fraudulently exposing fixed values by way of reverse engineering.
Regarding claim 15, Park does not explicitly teach wherein the sub shift data received by each of the plurality of sub security circuits is different from each other.
However, Komano et al teaches wherein the sub shift data received by each of the plurality of sub security circuits is different from each other (par [0085], lines 1-6, processing is changed…”).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Komano et al within the disclosure of Park according to the motivation disclosed regarding claim 14.
Regarding claim 20, Park teaches an operating method being executed by an encryption device (Abstract), the operating method comprising:
controlling, by an encryption controller circuit of the encryption device, an encryption core circuit of the encryption device (Abstract, “encryption core…outputting an encrypted result” & pg. 4, lines 36-37 and pg. 5, lines 1-15, which disclose input and output control logic to distribute data to and from encryption cores) to generate shift data by performing a shiftrow operation on input data (pg. 3, lines 16-20, “shift-row operation” & pg. 4, lines 1-15, “shiftrow logic”),
generating, by the encryption core circuit, permutation data by performing a permutation operation including a mixcolumn multiplication operation on the shift data (pg. 3, lines 16-25, “Mixcolumns operation”); and
generating , by the encryption core circuit, the output data by performing a round key addition operation on the first mid data (pg. 3, lines 10-20, “round key addition operation).
Park does not explicitly teach generating, by the encryption core circuit, first mid data by performing a mixcolumn addition operation on the permutation data.
However, Komano et al teaches generating, by the encryption core circuit, first mid data by performing a mixcolumn addition operation on the permutation data (par [0110], which discloses adding circuits being implemented to execute MixColumn operations).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Komano et al within the disclosure of Park in order to provide the predictive result of improving security by using a different mask in each cryptographic round to prevent leakage of masked value data (as disclosed in par [0038], par [0054] & par [0077] of Komano et al) because this feature eliminated the possibility of fraudulently exposing fixed values by way of reverse engineering.
Park and Komano et al do not explicitly teach performing a permutation operation including a mixcolumn multiplication operation on the shift data based on a plurality of encoding operations under control of the encryption controller circuit.
However, Ghosh teaches performing the permutation operation including a mixcolumn multiplication operation on the shift data based on a plurality of encoding operations under control of the encryption controller circuit (fig. 4, ‘400/‘412/’426, par [0030], lines 5-10, and par [0034], lines 5-20, which disclose encryption circuitry including a multiplexer and a mix-column unit that processes data input from a shift row, via first and second state register over a plurality of cryptographic rounds).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Ghosh within the teachings of Park and Komano et al in order to provide the predictive result of improving prevention of potential attacks by upgrading from an AES-126 to an AES-256 implemented environment (as disclosed in par [0001], lines 7-15 of Ghosh) because this feature allows for more in depth security in environments where high volume, data driven artificial intelligence (AI) applications require increasingly high bandwidth.
Regarding claim 21, Park does not explicitly teach wherein generating the permutation data comprises: receiving a plurality of pieces of sub shift data generated by dividing the shift data; and generating sub permutation data including a plurality of pieces of multiplication data by performing the permutation operation on the plurality of pieces of sub shift data, wherein the permutation operation includes the mixcolumn multiplication operation on each of a plurality of mixcolumn multiplication values.
However, Komano et al teaches wherein generating the permutation data comprises:
receiving a plurality of pieces of sub shift data generated by dividing the shift data (par [0100], “Shift-Row…divided 8-bit data block”), and generating sub permutation data including a plurality of pieces of multiplication data by performing the permutation operation on the plurality of pieces of sub shift data (par [0053], lines 10-20, “initial permutation…expansion permutation…final permutation” & par [0070], “Shift-Row executed cyclic permutation”), and
wherein the permutation operation includes the mixcolumn multiplication operation on each of a plurality of mixcolumn multiplication values (par [0072], “multiplying circuit…MixColumn”).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Komano et al within the disclosure of Park according to the motivation disclosed regarding claim 20.
8. Claims 4, 7, 13, and 16 are rejected under 35 USC 103 as being unpatentable over Park (KR 20180021473 A) in view of Komano et al (US 2007/0140478) in view of Ghosh (US 2024/0259182), further in view of Sano (JP 2008209499 A).
Regarding claim 4, Park, Komano et al, and Ghosh do not explicitly teach wherein each of the plurality of sub security circuits comprises a decoder configured to decode the sub shift data and output a decoded value; a permutation circuit configured to output a selected permutation value based on the decoded value; and an encoder configured to generate the multiplication data by encoding the seleted permutation value to represent a result of the mixcolumn multiplication operation on any one of the plurality of mixcolumn multiplication values.
However, Sano teaches wherein each of the plurality of sub security circuits comprises:
a decoder configured to decode the sub shift data and output a decoded value (pg. 10, lines 1-10, “AES decoder”);
a permutation circuit configured to output a selected permutation value based on the decoded value (pg. 10, lines 11-13, “decrypted plaintext”); and
an encoder configured to generate the multiplication data by encoding the seleted permutation value to represent a result of the mixcolumn multiplication operation on any one of the plurality of mixcolumn multiplication values (pg. 5, lines 6-10, AES encryption method…reverse process of mix MixColumn conversion).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Sano within the disclosure of Park, Komano et al, and Ghosh in order to provide the predictive result of improving processing efficiency by reducing the number of computations in a cryptographic environment (as disclosed in pg. 6, lines 1-30 of Sano) because this implementation increases processing efficiency during processing of data permutations.
Regarding claim 7, Park, Komano et al, and Ghosh do not explicitly teach wherein each of the plurality of sub security circuits comprises: a decoder configured to decode the sub shift data and output a decoded value; a permutation circuit configured to output a selected permutation value based on the decoded value; and a plurality of encoders configured to generate the multiplication data by encoding the seleted permutation value to represent a result of the mixcolumn multiplication operation on any one of the plurality of mixcolumn multiplication values.
However, Sano teaches wherein each of the plurality of sub security circuits comprises:
a decoder configured to decode the sub shift data and output a decoded value (pg. 10, 5-15, “decrypted plaintext”);
a permutation circuit configured to output a selected permutation value based on the decoded value (pg. 7, lines 10-15, “permutation P by the matrix”); and
a plurality of encoders configured to generate the multiplication data by encoding the seleted permutation value to represent a result of the mixcolumn multiplication operation on any one of the plurality of mixcolumn multiplication values (pg. 3, lines 12-20, “MixColumns operation”).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Sano within the disclosure of Park, Komano et al, and Ghosh according to the motivation disclosed regarding claim 4.
Regarding claim 13, Park, Komano et al, and Ghosh do not explicitly teach wherein each of the plurality of sub security circuits comprises a decoder configured to decode the sub shift data and output a decoded value; a permutation circuit configured to output a selected permutation value based on the decoded value; and an encoder configured to generate the multiplication data by encoding the seleted permutation value to represent a result of the mixcolumn multiplication operation on any one of the plurality of mixcolumn multiplication values.
However, Sano teaches wherein each of the plurality of sub security circuits comprises:
a decoder configured to decode the sub shift data and output a decoded value (pg. 10, lines 1-10, “AES decoder”);
a permutation circuit configured to output a selected permutation value based on the decoded value (pg. 10, lines 11-13, “decrypted plaintext”); and
an encoder configured to generate the multiplication data by encoding the seleted permutation value to represent a result of the mixcolumn multiplication operation on any one of the plurality of mixcolumn multiplication values (pg. 5, lines 6-10, AES encryption method…reverse process of mix MixColumn conversion).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Sano within the disclosure of Park, Komano et al, and Ghosh in order to provide the predictive result of improving processing efficiency by reducing the number of computations in a cryptographic environment (as disclosed in pg. 6, lines 1-30 of Sano) because this implementation increases processing efficiency during processing of data permutations.
Regarding claim 16, Park, Komano et al, and Ghosh do not explicitly teach wherein each of the plurality of sub security circuits comprises: a decoder configured to decode the sub shift data and output a decoded value; a permutation circuit configured to output a selected permutation value based on the decoded value; and a plurality of encoders configured to generate the multiplication data by encoding the seleted permutation value to represent a result of the mixcolumn multiplication operation on any one of the plurality of mixcolumn multiplication values.
However, Sano teaches wherein each of the plurality of sub security circuits comprises:
a decoder configured to decode the sub shift data and output a decoded value (pg. 10, 5-15, “decrypted plaintext”);
a permutation circuit configured to output a selected permutation value based on the decoded value (pg. 7, lines 10-15, “permutation P by the matrix”); and
a plurality of encoders configured to generate the multiplication data by encoding the seleted permutation value to represent a result of the mixcolumn multiplication operation on any one of the plurality of mixcolumn multiplication values (pg. 3, lines 12-20, “MixColumns operation”).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Sano within the disclosure of Park, Komano et al, and Ghosh according to the motivation disclosed regarding claim 13.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Randy A. Scott whose telephone number is (571) 272-3797. The examiner can normally be reached on Monday-Thursday 7:30 am-5:00 pm, second Fridays 7:30 am-4pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Luu Pham can be reached on (571) 270-5002. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/RANDY A SCOTT/Primary Examiner, Art Unit 2439 20260303