SEMICONDUCTOR DEVICE

DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 3-9, 11-15, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Min et al. (2022/0223526, hereafter Min) in view of Liao et al. (2023/0063786, hereafter Liao). Regarding claim 1, Min discloses semiconductor device comprising: a back interlayer insulating film (190, Fig. 32, 0087); a back wiring line (205, Fig. 32, 0034) in the back interlayer insulating film, the back wiring line comprising a first surface and a second surface opposite the first surface in a first direction; a fin-type pattern (AP1, Fig. 31-32, 0045) on the first surface of the back wiring line and extending in a second direction; a gate electrode (120, Fig. 32, 0036) on the fin-type pattern and extending in a third direction; a first source/drain pattern (150, Fig. 32, 0082) on a first side of the gate electrode, the first source/drain pattern comprising a bottom surface contacting the fin-type pattern; a back source/drain contact (206, Fig. 32, 0035) connected to the first surface of the back wiring line; a contact insulating liner (206a, Fig. 19, 0188) between the fin-type pattern and the back source/drain contact, the contact insulating liner extending along at least a portion of side walls of the back source/drain contact; a first front source/drain contact (170, Fig. 32, 0036) directly connected to the back source/drain contact; and a first contact silicide film (155, Fig. 32, 0098) between the first front source/drain contact and the first source/drain pattern, wherein an upper surface of the fin-type pattern is lower than an upper surface of the gate electrode in the first direction (Fig. 32). Min fails to disclose a back source/drain contact in the fin-type pattern. However, Liao teaches a back source/drain contact (92, Fig. 19A) in the fin-type pattern (16a in 20a/20b; Fig. 3, 19A; par. 0016). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Min with Liao by providing the source/drain contact in the fin-type pattern in order to increase the effective contact surface area to reduce electrical resistance and maximize thermal dissipation. Regarding claim 3, Min discloses a semiconductor device wherein the first contact silicide film (155, Fig. 32, par. 0098) does not extend along a bottom surface of the first front source/drain contact (170, Fig. 32, par. 0036). Regarding claim 4, Min discloses a semiconductor device further comprising: a second source/drain pattern (150 middle, Fig. 32) on the fin-type pattern (AP1, Figs. 31-32, par. 0045) on a second side of the gate electrode (120, Fig. 32, par. 0036); a second front source/drain contact (170 middle, Fig. 32) connected to the second source/drain pattern; and a second contact silicide film (155 center, Fig. 32) extending along side walls of the second front source/drain contact, and wherein the second contact silicide film does not extend along a bottom surface of the second front source/drain contact. Regarding claim 5, Min discloses a semiconductor device further comprising: a defective semiconductor region (196, Fig. 27, par. 0116) contacting the second front source/drain contact (170 middle, Fig. 27, par. 0036), and extending along the bottom surface of the second front source/drain contact. Regarding claim 6, Min discloses a semiconductor device further comprising: a defective semiconductor region (196, Fig. 27, par. 0116) contacting a bottom surface of the first front source/drain contact (172b, Fig. 25, par. 0036). Regarding claim 7, Min discloses a semiconductor device wherein the defective semiconductor region (196, Fig. 19) contacts the contact insulating liner (206a, Fig. 19). Regarding claim 8, Min discloses a semiconductor device wherein the first front source/drain contact comprises a front contact barrier film (170a, Fig. 19, par. 0108) and a front contact plug film (170b, Fig. 19, par. 0108). Regarding claim 9, Min discloses a semiconductor device wherein the front contact plug film (170b, Fig. 32) is directly connected to the back source/drain contact (206, Fig. 32). Regarding claim 11, Min discloses a semiconductor device further comprising a plurality of sheet patterns (UP1, Fig. 32, par. 0218) on the fin-type pattern (AP1, Figs. 31-32, par. 0045) and spaced apart from the fin-type pattern in the first direction, wherein the first source/drain pattern (150, Fig. 32, par. 0082) contacts the plurality of sheet patterns. Regarding claim 12, Min discloses a semiconductor device further comprising a substrate (191, Fig. 32, par. 0115) between the back wiring line (205, Fig. 32) and the fin-type pattern (AP1, Figs. 31-32), wherein the fin-type pattern protrudes from the substrate in the first direction, and wherein the back source/drain contact (206, Fig. 32) penetrates the substrate. Regarding claim 13, Min discloses a semiconductor device comprising: a back interlayer insulating film (190, Fig. 32, par. 0087); a back wiring line (205, Fig. 32, par. 0034) in the back interlayer insulating film, and the back wiring line comprising a first surface and a second surface opposite the first surface in a first direction; a fin-type pattern (AP1, Figs. 31-32, par. 0043) on the first surface of the back wiring line, and extending in a second direction; a first source/drain pattern (150 right, Fig. 32, par. 0080) and a second source/drain pattern (150 middle, Fig. 32, par. 0080) on the fin-type pattern and spaced apart in the second direction; a gate electrode (120 middle right, Fig. 32, par. 0036) between the first source/drain pattern and the second source/drain pattern; a back source/drain contact (206, Fig. 32, par. 0035) connected to the first surface of the back wiring line; a first front source/drain contact (170 right, Fig. 32, par. 0036) directly connected to the back source/drain contact, the first front source/drain contact comprising at least a portion in the first source/drain pattern; a second front source/drain contact (170 middle, Fig. 32, par. 0036) connected to the second source/drain pattern, the second front source/drain contact comprising at least a portion in the second source/drain pattern; a first contact silicide film (155 right, Fig. 32, par. 0098) between the first front source/drain contact and the first source/drain pattern; and a second contact silicide film (155 middle, Fig. 32, par. 0098) extending along side walls of the second front source/drain contact, wherein the second contact silicide film does not extend along a bottom surface of the second front source/drain contact. Min fails to disclose a back source/drain contact in the fin-type pattern. However, Liao teaches a back source/drain contact (92, Fig. 19A) in the fin-type pattern (16a in 20a/20b; Fig. 3, 19A; par. 0016). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Min with Liao by providing the source/drain contact in the fin-type pattern in order to increase the effective contact surface area to reduce electrical resistance and maximize thermal dissipation. Regarding claim 14, Min discloses a semiconductor device further comprising: a defective semiconductor region (196, Fig. 27, par. 0116) contacting the second front source/drain contact (170 middle, Fig. 27), and extending along the bottom surface of the second front source/drain contact. Regarding claim 15, Min discloses a semiconductor device further comprising: a defective semiconductor region (196, Fig. 27) contacting a bottom surface of the first front source/drain contact (170 right, Fig. 27). Regarding claim 18, Min discloses a semiconductor device further comprising a plurality of sheet patterns (UP1, Fig. 32, par. 0218) on the fin-type pattern (AP1, Figs. 31-32), and spaced apart from the fin-type pattern in the first direction, wherein the plurality of sheet patterns are disposed the first source/drain pattern (150 right, Fig. 32) and the second source/drain pattern (150 middle, Fig. 32). Regarding claim 19, Min discloses a semiconductor device comprising: a back interlayer insulating film (190, Fig. 32, par. 0086); a back wiring line (205, Fig. 32, par. 0034) in the back interlayer insulating film, the back wiring line comprising a first surface and a second surface opposite the first surface in a first direction; a fin-type pattern (AP1, Figs. 31-32, par. 0045) on the first surface of the back wiring line, and extending in a second direction; a plurality of sheet patterns (UP1, Figs. 32, 34; par. 0036) on the fin-type pattern, and spaced apart from the fin-type pattern in the first direction; a gate electrode (120, Figs. 32, 34; par. 0036) on the fin-type pattern, extending in a third direction, and at least partially surrounding the plurality of sheet patterns (Fig. 34); a source/drain pattern (150, Fig. 32, par. 0080) on a side surface of the gate electrode, the source/drain pattern comprising a bottom surface contacting the fin-type pattern; a back source/drain contact (206, Fig. 32, par. 0034) connected to the first surface of the back wiring line; a contact insulating liner (206a, Fig. 19, par. 0186) between the fin-type pattern and the back source/drain contact, the contact insulating liner extending along at least a portion of a side wall of the back source/drain contact; a front source/drain contact (170, Fig. 32, par. 0036) directly connected to the back source/drain contact, the front source/drain contact comprising a least a portion in the source/drain pattern; and a contact silicide film (155, Fig. 32, par. 0098) extending along a side wall of the front source/drain contact, wherein the contact silicide film does not extend along a bottom surface of the front source/drain contact. Min fails to disclose a back source/drain contact in the fin-type pattern. However, Liao teaches a back source/drain contact (92, Fig. 19A) in the fin-type pattern (16a in 20a/20b; Fig. 3, 19A; par. 0016). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Min with Liao by providing the source/drain contact in the fin-type pattern in order to increase the effective contact surface area to reduce electrical resistance and maximize thermal dissipation. Claims 2, 10, 16, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Min in view of Liao as applied to claims 1, 13, and 19 above, and further in view of Kim et al. (2021/0375722, hereafter Kim). Regarding claim 2, Min discloses a semiconductor device wherein the back source/drain contact (206, Fig. 32) comprises: a first surface (206_US, Fig. 32) connected to the back wiring line (205, Fig. 32); and a second surface opposite to the first surface of the back source/drain contact in the first direction (Fig. 32). Min and Liao fail to disclose that the contact insulating liner does not extend to the second surface of the back source/drain contact. However, Kim teaches that the contact insulating liner (131, Fig. 3, par. 0034) does not extend to the second surface (120B, Fig. 3, par. 0034) of the back source/drain contact (120, Fig. 3, par. 0034). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Min and Liao with Kim by implementing a liner that does not extend to the second surface of the contact in order to provide contact area between the back source/drain contact and first front source/drain contact. Regarding claim 10, Min and Liao fail to disclose a semiconductor device further comprising a front wiring line on the gate electrode and connected to the first front source/drain contact, wherein the first front source/drain contact is between the front wiring line and the back source/drain contact. However, Kim teaches a semiconductor device further comprising a front wiring line (ML1, Fig. 2) on the gate electrode (145, Fig. 2, par. 0028) and connected to the first front source/drain contact (180, Fig. 2), wherein the first front source/drain contact is between the front wiring line and the back source/drain contact (120, Fig. 2). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Min and Liao with Kim by implementing a front wiring line on the other side of the first front source/drain contact from the back source/drain contact in order to maximize surface area to reduce parasitic resistance, and provide signals for a plurality of devices. Regarding claim 16, Min discloses a semiconductor device further comprising a contact insulating liner (206a, Fig. 19, par. 0186) between the fin-type pattern (AP1, Figs. 1, 19) and the back source/drain contact (206b, Fig. 19, par. 0186), the contact insulating liner extending along side walls of the back source/drain contact. Min and Liao fail to disclose that the contact insulating liner does not contact the first front source/drain contact. However, Kim teaches that the contact insulating liner (251) does not contact the first front source/drain contact (180, par. 0047) (Fig. 2-3). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Min and Liao with Kim by providing an insulating liner that does not contact the first front source/drain contact in order to provide contact area between the back source/drain contact and first front source/drain contact and prevent inhibiting connection between contacts. Regarding claim 17, Min discloses a semiconductor device wherein the first contact silicide film (155, Fig. 32) does not extend along a bottom surface of the first front source/drain contact (170 right, Fig. 32). Regarding claim 20, Min and Liao fail to disclose a semiconductor device wherein the contact insulating liner does not contact the front source/drain contact. However, Kim teaches a semiconductor device wherein the contact insulating liner (251) does not contact the front source/drain contact (180, par. 0047) (Fig. 2-3). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Min and Liao with Kim by providing an insulating liner that does not contact the first front source/drain contact in order to provide contact area between the back source/drain contact and first front source/drain contact and prevent inhibiting connection between contacts. Response to Arguments Applicant’s arguments with respect to claims 1, 13, and 19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES M BRECHT whose telephone number is (571)272-9634. The examiner can normally be reached Mon-Fri: 7:30am - 5pm. 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Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /C.M.B./Examiner, Art Unit 2817 /ALI NARAGHI/Primary Examiner, Art Unit 2817