DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1 and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 20 of U.S. Publication No. 2025/0323583 A1. Although the claims at issue are not identical, they are not patentably distinct from each other because they can be interpreted to describe substantially identical or very similar a gate drive system with essentially the same relationship. Regarding claims 1 and 20 of instant application, see comparison with claims 11 and 20 of US Publication No. 2025/0323583 A1, respectively. Differences between the respective claims are underlined.
Instant application 18/634538
U.S. Publication No. 2025/0323583 A1
Claim 1. A gate drive system for a multi-phase power inverter, comprising:
a gate controller, a gate drive circuit, and a hybrid switch power module;
wherein the hybrid switch power module is integrated into a phase leg of the multi-phase power inverter;
wherein the hybrid switch power module includes a first semiconductor switch connected in parallel with a second semiconductor switch between one of a positive power rail or a negative power rail and an AC power link of the phase leg of the multi-phase power inverter, the first semiconductor switch having a first set of performance characteristics and the second semiconductor switch having a second set of performance characteristics differing at least partially from the first set of performance characteristics;
wherein the gate drive circuit includes a gate driver, a first variable resistance circuit that connects to the first semiconductor switch, and a second variable resistance circuit that connects to the second semiconductor switch;
wherein the gate controller generates a plurality of control signals that are communicated to the gate drive circuit to control the hybrid switch power module;
wherein the gate controller is connected to the gate drive circuit via a plurality of links; and
wherein the gate controller communicates the plurality of control signals to the gate drive circuit via the plurality of links.
Claim 20. An electrified vehicle system, comprising:
a gate drive system, a multi-phase power inverter, and an electric machine;
the multi-phase power inverter being operatively connected to the electric machine via a plurality of phase legs;
the gate drive system including a gate controller, a gate drive circuit, and a plurality of hybrid switch power modules;
wherein the plurality of hybrid switch power modules are electrically coupled to the plurality of phase legs of the multi-phase power inverter;
wherein each of the plurality of hybrid switch power modules includes a first semiconductor switch connected in parallel with a second semiconductor switch between one of a positive high-voltage DC power rail or a negative HV DC power rail and one of the plurality of phase legs of the multi-phase power inverter, the first semiconductor switch having a first set of performance characteristics and the second semiconductor switch having a second set of performance characteristics differing at least partially from the first set of performance characteristics;
wherein the gate drive circuit includes a gate driver, a first variable resistance circuit that connects to the first semiconductor switch, and a second variable resistance circuit that connects to the second semiconductor switch;
wherein the gate controller generates a plurality of control signals that are communicated to the gate drive circuit to control the hybrid switch power module;
wherein the gate controller is connected to the gate drive circuit via a plurality of links; and
wherein the gate controller communicates the plurality of control signals to the gate drive circuit via the plurality of links.
Claim 1. Control system for a multi-phase inverter, comprising:
a gate controller, a gate drive circuit, and a hybrid switch power module;
wherein the hybrid switch power module is integrated into a phase leg of the multi-phase inverter;
wherein the hybrid switch power module includes a first semiconductor switch connected in parallel with a second semiconductor switch between one power rail and an AC power link of the phase leg of the multi-phase inverter, the first semiconductor switch having a first set of performance characteristics and the second semiconductor switch having a second set of performance characteristics differing at least partially from the first set of performance characteristics;
wherein the gate drive circuit includes a gate driver, a first variable resistance circuit that operatively connects to the first semiconductor switch, and a second variable resistance circuit that operatively connects to the second semiconductor switch;
wherein the gate controller generates a first control signal for controlling the first semiconductor switch via the gate driver and the first variable resistance circuit, the first control signal selected to achieve a first switching transient in the first semiconductor switch;
wherein the gate controller generates a second control signal for controlling the second semiconductor switch via the gate driver and the second variable resistance circuit, the second control signal selected to achieve a second switching transient in the second semiconductor switch; and
wherein the gate controller generates the first control signal and the second control signal to synchronize the first switching transient in the first semiconductor switch with the second switching transient in the second semiconductor switch.
Claim 20. A vehicle system, comprising:
a gate drive system, a multi-phase power inverter, and an electric machine;
the multi-phase power inverter being operatively connected to the electric machine via a plurality of phase legs;
the gate drive system including a gate controller, a gate drive circuit, and a plurality of hybrid switch power modules;
wherein the hybrid switch power modules are integrated into the plurality of phase legs of the multi-phase inverter;
wherein each of the hybrid switch power modules includes a first semiconductor switch connected in parallel with a second semiconductor switch between a power rail and an AC power link of the phase leg of the multi-phase inverter,
the first semiconductor switch having a first set of performance characteristics and the second semiconductor switch having a second set of performance characteristics differing at least partially from the first set of performance characteristics;
wherein the gate drive circuit includes a gate driver, a first variable resistance circuit that is operatively connected to the first semiconductor switch, and a second variable resistance circuit that is operatively connected to the second semiconductor switch;
wherein the gate controller generates a first control signal for controlling the first semiconductor switch via the gate driver and the first variable resistance circuit, the first control signal selected to achieve a first switching transient in the first semiconductor switch;
wherein the gate controller generates a second control signal for controlling the second semiconductor switch via the gate driver and the second variable resistance circuit, the second control signal selected to achieve a second switching transient in the second semiconductor switch;
wherein the gate controller generates the first control signal and the second control signal to synchronize the first switching transient in the first semiconductor switch with the second switching transient in the second semiconductor switch.
Note: some claims of instant application are not exactly limitations as U.S. Publication No. 2025/0323583 A1. However, they are the same functions. Therefore, these limitations are obvious by system of U.S. Publication No. 2025/0323583 A1.
Allowable Subject Matter
Claims 10-19 are allowed.
The following is an examiner’s statement of reasons for allowance:
For claim 10, the prior art of record fails to disclose, reasonably suggest, or render obvious, in combination with all the given limitations, a multi-phase power inverter comprising a gate drive system including a gate controller, gate drive circuits and a plurality of hybrid switch power modules;
wherein each hybrid switch power module includes a first semiconductor switch connected in parallel with a second semiconductor switch between one of the positive DC power rail or the negative DC power rail and one of the plurality of AC power links of the respective phase leg of the multi-phase power inverter, the first semiconductor switch having a first set of performance characteristics and the second semiconductor switch having a second set of performance characteristics differing at least partially from the first set of performance characteristics; and
wherein the gate drive circuit includes a gate driver, a first variable resistance circuit that connects to the first semiconductor switch, and a second variable resistance circuit that is connects the second semiconductor switch.
Claims 11-19 are allowed because they depend on claim 10.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THAI T DINH whose telephone number is (571)270-3852. The examiner can normally be reached (571)270-3852.
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/THAI T DINH/Primary Examiner, Art Unit 2846