DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Information Disclosure Statement
The Information Disclosure Statement filed on April 12, 2024 and February 20, 2025 have been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 11 similarly recite “determine a first number of channels required to store first data of a first tenant in each way of the plurality of ways based on commands received from each of the plurality of tenants”. The specification appears to show that only the commands of a particular tenant are used to determine how many channels are required. This is different from what is claimed. The present claim limitation recites that commands from each of the tenants are used to determine the number of channels for the first tenant.
[0093] For example, when 192 write requests are received from the first tenant Tenant 1 and 192 write requests are received from the second tenant Tenant 1, the channel allocator 142 may determine whether the number of write requests included in commands received from the first tenant Tenant 1 and the second tenant Tenant 2 is greater than or equal to “384,” which is the predetermined threshold value. When 192 kB of data can be stored in each memory die, the channel allocator 142 may determine that four channels are required to store the first data. In addition, the channel allocator 142 may determine that four channels are required to store the second data.
[0094] For example, when 96 write requests are received from the first tenant Tenant 1 and 288 write requests are received from the second tenant Tenant 2, the channel allocator 142 may determine whether the number of write requests included in commands received from the first tenant Tenant 1 and the second tenant Tenant 2 is greater than or equal to “384,” which is the predetermined threshold value. When 192 kB of data can be stored in each memory die, the channel allocator 142 may determine that two channels are required to store the first data. In addition, the channel allocator 142 may determine that six channels are required to store the second data.
Claim 1 recites the limitation "the first number of memory dies" in line 11. There is insufficient antecedent basis for this limitation in the claim.
Claim 2 recites the limitation "the first number of memory dies" in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim 2 recites the limitation "the first number of memory dies" in line 5. There is insufficient antecedent basis for this limitation in the claim.
Claim 5 recites the limitation "the first number " in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim 6 recites the limitation "the first number " in lines 1-2. There is insufficient antecedent basis for this limitation in the claim.
Claim 6 recites the limitation "the first number of memory dies" in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim 8 recites the limitation "the first number of memory dies" in lines 4-5. There is insufficient antecedent basis for this limitation in the claim.
Claim 9 recites the limitation "the first number of memory dies" in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim 9 recites the limitation "the first number of memory dies" in line 6. There is insufficient antecedent basis for this limitation in the claim.
Claim 11 recites the limitation "the first number of memory dies" in line 8. There is insufficient antecedent basis for this limitation in the claim.
Claim 12 recites the limitation "the first number of memory dies" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 12 recites the limitation "the first number of memory dies" in line 4. There is insufficient antecedent basis for this limitation in the claim.
Claim 15 recites the limitation "the first number " in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 16 recites the limitation "the first number " in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 16 recites the limitation "the first number of memory dies" in lines 2-3. There is insufficient antecedent basis for this limitation in the claim.
Claim 18 recites the limitation "the first number of memory dies" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 18 recites the limitation "the first number of memory dies" in line 5. There is insufficient antecedent basis for this limitation in the claim.
Claim 19 recites the limitation "the first number of memory dies" in line 13. There is insufficient antecedent basis for this limitation in the claim.
Claim 20 recites the limitation "the first number of memory dies" in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim 20 recites the limitation "the first number of memory dies" in line 5. There is insufficient antecedent basis for this limitation in the claim.
Claim 3 recites the limitation "the second number of memory dies" in line 6. There is insufficient antecedent basis for this limitation in the claim.
Claim 4 recites the limitation "the second number of memory dies" in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim 5 recites the limitation "the second number " in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim 6 recites the limitation "the second number" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 6 recites the limitation "the second number of memory dies" in line 4. There is insufficient antecedent basis for this limitation in the claim.
Claim 13 recites the limitation "the second number of memory dies" in line 4. There is insufficient antecedent basis for this limitation in the claim.
Claim 14 recites the limitation "the second number of memory dies" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 15 recites the limitation "the second number " in lines 2-3. There is insufficient antecedent basis for this limitation in the claim.
Claim 16 recites the limitation "the second number" in lines 1-2. There is insufficient antecedent basis for this limitation in the claim.
Claim 16 recites the limitation "the second number of memory dies" in line 3-4. There is insufficient antecedent basis for this limitation in the claim.
Claims not referred to specifically above are rejected as depending upon a rejected claim
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 11, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Byun (Pub. No. US 2019/0303293) in view of Nanduri et al. (Pub. No. US 2016/0179404).
Claim 1:
Byun discloses a storage device comprising:
a plurality of memory dies corresponding to a plurality of channels and a plurality of ways [fig. 7; pars. 0098-0100 – “The memory device 150 may include the plurality of memory dies which are coupled to a plurality of channels and a plurality of ways, and index information on the channels and ways coupled to the respective memory dies may be included in metadata and may then be stored in the memory 144 of the controller 130 and the memory device 150.”]; and
a storage controller connected to the plurality of memory dies [figs. 1, 7; pars. 0048-0049 – “The memory system 110 may include a memory device 150 and a controller 130. The memory device 150 may store data for the host 120, and the controller 130 may control data storage into the memory device 150.”],
wherein the storage controller is configured to:
receive commands from a tenant [figs. 1, 7; pars. 0048-0054 – “The host interface 132 may be configured to process a command and data of the host 102, and may communicate with the host 102 through one or more of various interface protocols such as universal serial bus (USB), multi-media card (MMC), peripheral component interconnect-express (PCI-e or PCIe), small computer system interface (SCSI), serial-attached SCSI (SAS), serial advanced technology attachment (SATA), parallel advanced technology attachment (PATA), enhanced small disk interface (ESDI) and integrated drive electronics (IDE).”];
However, Byun does not specifically disclose,
receiving commands from a plurality of tenants
in response to a number of the received commands being equal to or greater than a predetermined threshold value, determine a first number of channels required to store first data of a first tenant in each way of the plurality of ways based on commands received from each of the plurality of tenants; and
store the first data in the first number of memory dies in each way of the plurality of ways, and
wherein the first data is stored in memory dies that correspond to the plurality of channels in at least a portion or an entire portion of the plurality of ways.
In the same field of endeavor, Nanduri et al. disclose,
receiving commands from a plurality of tenants [par. 0054 – “At any point in time, many types of applications may be accessing the storage device, sending read and write request of different request sizes.”],
in response to a number of the received commands being equal to or greater than a predetermined threshold value, determine a first number of channels required to store first data of a first tenant in each way of the plurality of ways based on commands received from each of the plurality of tenants [pars. 0040-0044 – The threshold is 0 (e.g. as long as any commands are received). The maximum number of channels and ways are used to maximize throughput. (“To maximize the write throughput beyond this 4 MB/sec, SSDs typically stripe the write request among all the possible flash planes. For example SSDs first stripe the data across channels (N) (channel parallelism), then SSDs stripe across flash packages (M) (way parallelism), then SSDs stripe across flash dies (L), and then SSDs stripe across flash planes(K). By doing this, SSDs can get a write throughput of (N*M*L*K*40 MB/sec). The striping granularity across flash planes is about the flash page size. Some of the SSDs might choose to limit the write striping to some upper limit, though the actual flash parallelism is high.” … “In another scenario, assuming a write chunklet size of 64 KB, and there are two write requests of 32 KB each, then it is better to submit these two write requests together to maximize the write throughput.”)]; and
store the first data in the first number of memory dies in each way of the plurality of ways [pars. 0040-0044 – The maximum number of dies are used to maximize throughput. (“To maximize the write throughput beyond this 4 MB/sec, SSDs typically stripe the write request among all the possible flash planes. For example SSDs first stripe the data across channels (N) (channel parallelism), then SSDs stripe across flash packages (M) (way parallelism), then SSDs stripe across flash dies (L), and then SSDs stripe across flash planes(K). By doing this, SSDs can get a write throughput of (N*M*L*K*40 MB/sec). The striping granularity across flash planes is about the flash page size. Some of the SSDs might choose to limit the write striping to some upper limit, though the actual flash parallelism is high.” … “In another scenario, assuming a write chunklet size of 64 KB, and there are two write requests of 32 KB each, then it is better to submit these two write requests together to maximize the write throughput.”)], and
wherein the first data is stored in memory dies that correspond to the plurality of channels in at least a portion or an entire portion of the plurality of ways [pars. 0040-0044 – The maximum number of channels and dies are used to maximize throughput. (“To maximize the write throughput beyond this 4 MB/sec, SSDs typically stripe the write request among all the possible flash planes. For example SSDs first stripe the data across channels (N) (channel parallelism), then SSDs stripe across flash packages (M) (way parallelism), then SSDs stripe across flash dies (L), and then SSDs stripe across flash planes(K). By doing this, SSDs can get a write throughput of (N*M*L*K*40 MB/sec). The striping granularity across flash planes is about the flash page size. Some of the SSDs might choose to limit the write striping to some upper limit, though the actual flash parallelism is high.” … “In another scenario, assuming a write chunklet size of 64 KB, and there are two write requests of 32 KB each, then it is better to submit these two write requests together to maximize the write throughput.”)].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Byun to include the teachings of Nanduri et al., in order to improve performance by maximizing parallelism.
Claim 11:
Claim 11, directed to a method, is rejected for the same reasons set forth in the rejection of claim 1 above, mutatis mutandis.
Claim 19:
Byun discloses a storage device comprising:
a nonvolatile memory device comprising a plurality of channels, each channel of the plurality of channels comprising a plurality of memory dies corresponding to a plurality of ways [fig. 7; pars. 0098-0100 – “The memory device 150 may include the plurality of memory dies which are coupled to a plurality of channels and a plurality of ways, and index information on the channels and ways coupled to the respective memory dies may be included in metadata and may then be stored in the memory 144 of the controller 130 and the memory device 150.”]; and
a storage controller [figs. 1, 7; pars. 0048-0049 – “The memory system 110 may include a memory device 150 and a controller 130. The memory device 150 may store data for the host 120, and the controller 130 may control data storage into the memory device 150.”],
However, Byun does not specifically disclose,
wherein the storage controller comprises:
a command queue configured to store commands transmitted from a plurality of tenants,
an input command handler configured to fetch the commands from the command queue;
a channel allocator configured to determine a first number of channels required to store first data of a first tenant based on information included in the commands; and
a placement unit configured to store the first data in the first number of memory dies in each way of the plurality of ways, and
wherein the first data is stored in memory dies that evenly correspond to the plurality of channels in at least a portion or an entire portion of the plurality of ways.
In the same field of endeavor, Nanduri et al. disclose,
a command queue configured to store commands transmitted from a plurality of tenants [pars. 0054, 0057 – “At any point in time, many types of applications may be accessing the storage device, sending read and write request of different request sizes.” … “In one embodiment, the request processor includes read requests queue 204 and write requests queue 206. In another embodiment, a single queue is used for holding incoming read and write requests.”],
an input command handler configured to fetch the commands from the command queue [par. 0058 – “The scheduler 210 selects read requests and write requests from their respective queues and schedules them for processing, which includes transferring the scheduled requests, or chunklets of the I/O requests, to the SSD. Scheduler 210 may utilize algorithms for fair scheduling of the incoming requests based on system parameters, such as priority of the request, fairness, use of SSD, quality of service (QOS), etc.”];
a channel allocator configured to determine a first number of channels required to store first data of a first tenant based on information included in the commands [pars. 0040-0044 – The maximum number of channels and ways are used to maximize throughput. (“To maximize the write throughput beyond this 4 MB/sec, SSDs typically stripe the write request among all the possible flash planes. For example SSDs first stripe the data across channels (N) (channel parallelism), then SSDs stripe across flash packages (M) (way parallelism), then SSDs stripe across flash dies (L), and then SSDs stripe across flash planes(K). By doing this, SSDs can get a write throughput of (N*M*L*K*40 MB/sec). The striping granularity across flash planes is about the flash page size. Some of the SSDs might choose to limit the write striping to some upper limit, though the actual flash parallelism is high.” … “In another scenario, assuming a write chunklet size of 64 KB, and there are two write requests of 32 KB each, then it is better to submit these two write requests together to maximize the write throughput.”)]; and
a placement unit configured to store the first data in the first number of memory dies in each way of the plurality of ways [pars. 0040-0044 – The maximum number of dies are used to maximize throughput. (“To maximize the write throughput beyond this 4 MB/sec, SSDs typically stripe the write request among all the possible flash planes. For example SSDs first stripe the data across channels (N) (channel parallelism), then SSDs stripe across flash packages (M) (way parallelism), then SSDs stripe across flash dies (L), and then SSDs stripe across flash planes(K). By doing this, SSDs can get a write throughput of (N*M*L*K*40 MB/sec). The striping granularity across flash planes is about the flash page size. Some of the SSDs might choose to limit the write striping to some upper limit, though the actual flash parallelism is high.” … “In another scenario, assuming a write chunklet size of 64 KB, and there are two write requests of 32 KB each, then it is better to submit these two write requests together to maximize the write throughput.”)], and
wherein the first data is stored in memory dies that evenly correspond to the plurality of channels in at least a portion or an entire portion of the plurality of ways [pars. 0040-0044 – The maximum number of channels and ways are used to maximize throughput. (“To maximize the write throughput beyond this 4 MB/sec, SSDs typically stripe the write request among all the possible flash planes. For example SSDs first stripe the data across channels (N) (channel parallelism), then SSDs stripe across flash packages (M) (way parallelism), then SSDs stripe across flash dies (L), and then SSDs stripe across flash planes(K). By doing this, SSDs can get a write throughput of (N*M*L*K*40 MB/sec). The striping granularity across flash planes is about the flash page size. Some of the SSDs might choose to limit the write striping to some upper limit, though the actual flash parallelism is high.” … “In another scenario, assuming a write chunklet size of 64 KB, and there are two write requests of 32 KB each, then it is better to submit these two write requests together to maximize the write throughput.”)].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Byun to include the teachings of Nanduri et al., in order to improve performance by maximizing parallelism.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Oikarinen et al. (Pub. No. US 2015/0277802) disclose, “In at least some embodiments it may be possible to improve overall performance achieved for the sequential reads by assigning higher priorities (or, equivalently, lower costs) to those clients that have made more progress. FIG. 34 illustrates an example timeline of the progress made by multiple concurrent read requests directed to a logical block of a storage service object in a scheduling environment in which an offset-based congestion control policy is used, according to at least some embodiments. Logical block 3302 once again comprises two pages PP1 and PP2 at an extent E3334 with a capacity of 25 page I/Os per second. In the depicted embodiment, LB 3302 has an offset-based I/O prioritization policy 3401 to implement congestion control. In accordance with the policy, read requests that are directed to higher offsets within LB 3302 are given higher priority than read requests directed to lower offsets.” [par. 0204]
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LARRY T MACKALL whose telephone number is (571)270-1172. The examiner can normally be reached Monday - Friday, 9am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald G Bragdon can be reached at (571) 272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
LARRY T. MACKALL
Primary Examiner
Art Unit 2131
10 January 2026
/LARRY T MACKALL/Primary Examiner, Art Unit 2139