DETAILED ACTION
This Office action is in response to the application filed on 12 April 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-7 and 12-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Pieszala et al. (US Patent 12,362,742; hereinafter “Pieszala”).
The applied reference has a common applicant and common joint inventors with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
In re claims 1, 19 and 20, Pieszala discloses a vehicle system, a control system for a multi-phase inverter, and the operational method of its control (Figs. 1, 2), comprising:
a gate controller (Figs. 1, 2: 38), a gate drive circuit (Figs. 1, 2: 40), and a hybrid switch power module (e.g., M1);
wherein the hybrid switch power module is integrated into a phase leg of the multi-phase inverter (see Fig. 1);
wherein the hybrid switch power module includes a first semiconductor switch (Fig. 2: e.g., 56) connected in parallel with a second semiconductor switch (Fig. 2: e.g., 54) between a power rail (positive or negative DC bus rail in Fig. 1)and an AC power link of the phase leg of the multi-phase inverter (Fig. 1: output phases 46, 48, 50), the first semiconductor switch having a first set of performance characteristics and the second semiconductor switch having a second set of performance characteristics differing at least partially from the first set of performance characteristics (col. 2: 1-5);
wherein the gate drive circuit (40) includes a gate driver (Fig. 2: 118), a first variable resistance circuit (Fig. 2: 82) that is operatively connected to the first semiconductor switch (54), and a second variable resistance circuit (84) that is operatively connected to the second semiconductor switch (56);
wherein the gate controller generates a first control signal for controlling the first semiconductor switch via the gate driver and the first variable resistance circuit (Fig. 2: signal comprising 108, 112), the first control signal selected to achieve a first switching transient in the first semiconductor switch (that is, selected to turn on/off the switch, for example);
wherein the gate controller generates a second control signal for controlling the second semiconductor switch via the gate driver and the second variable resistance circuit (Fig. 2: 110, 114), the second control signal selected to achieve a second switching transient in the second semiconductor switch (turn on/off as above); and
wherein the gate controller generates the first control signal and the second control signal to synchronize the first switching transient in the first semiconductor switch with the second switching transient in the second semiconductor switch (col. 11: 8-16).
In re claim 2, Pieszala discloses wherein the first control signal for controlling the first semiconductor switch to achieve the first switching transient in the first semiconductor switch comprises a first slew rate command (Fig. 2: 112; see col. 8: 20-27);
wherein the second control signal for controlling the second semiconductor switch to achieve the second switching transient in the second semiconductor switch comprises a second slew rate command (Fig. 2: 114; see id.); and
wherein the gate controller controls the first slew rate command and the second slew rate command to synchronize the first switching transient in the first semiconductor switch with the second switching transient in the second semiconductor switch (col. 11: 8-16).
In re claim 3, Pieszala discloses wherein the gate controller generates the first control signal to control the first variable resistance circuit to control the first slew rate to achieve the first switching transient in the first semiconductor switch (col. 8: 20-35); and
wherein the gate controller generates the second control signal to control the second variable resistance circuit to control the second slew rate to achieve the second switching transient in the second semiconductor switch (id.).
In re claim 4, Pieszala discloses wherein the first switching transient comprises a first time-rate change in voltage (dV/dt) across the first semiconductor switch (col. 9:1-9), and wherein the second switching transient comprises a second time-rate change in voltage (dV/dt) across the second semiconductor switch (id.).
In re claim 5, Pieszala discloses wherein the first switching transient comprises a first time-rate change in current (dI/dt) across the first semiconductor switch (id.), and wherein the second switching transient comprises a second time-rate change in current (dI/dt) across the second semiconductor switch (id.).
In re claim 6, Pieszala discloses wherein the first control signal for controlling the first semiconductor switch to achieve the first switching transient in the first semiconductor switch comprises a first pulse width-modulated (PWM) signal (id.);
wherein the second control signal for controlling the second semiconductor switch to achieve the second switching transient in the second semiconductor switch comprises a second PWM signal (id.); and
wherein the gate controller controls the first PWM signal and the second PWM signal to synchronize the first switching transient in the first semiconductor switch with the second switching transient in the second semiconductor switch (col. 11: 8-16).
In re claim 7, Pieszala discloses wherein the gate controller generates the first control signal to control the first PWM signal to achieve the first switching transient in the first semiconductor switch (col. 8:20-27 and 42-47); and
wherein the gate controller generates the second control signal to control the second PWM signal to achieve the second switching transient in the second semiconductor switch (id.).
In re claim 12, Pieszala discloses wherein the first PWM signal includes a first frequency and a first duty cycle (it is known that a PWM signal, by definition, includes a frequency and duty cycle; see also col. 8:42-47 and col. 9:1-9), wherein the second PWM signal is OFF (that is, when the second switch is OFF, its PWM control signal is considered to be OFF; see also col. 8:20-27).
In re claim 13, Pieszala discloses wherein the first semiconductor switch (56) of the hybrid switch power module comprises an Insulated Gate Bipolar Transistor (IGBT) (see Fig. 2), and second semiconductor switch (54) comprises a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) (see Fig. 2).
In re claim 14, Pieszala discloses wherein the first semiconductor switch of the hybrid switch power module comprises a silicon-based device, and wherein the second semiconductor switch comprises a wide bandgap (WBG) device (col. 7:27-36).
In re claim 15, Pieszala discloses wherein the power rail comprises a positive high-voltage power link, and wherein the hybrid switch power module is connected between the positive high-voltage power link and the AC power link of the phase leg of the multi-phase inverter (that is, when the specific hybrid switch module is, e.g., M1 as shown in Fig. 1).
In re claim 16, Pieszala discloses wherein the power rail comprises a negative high-voltage power link, and wherein the hybrid switch power module is connected between the negative high-voltage power link and the AC power link of the phase leg of the multi-phase inverter (that is, when the specific hybrid switch module is, e.g., M2 as shown in Fig. 1; see col. 6:60-65).
In re claim 17, Pieszala discloses, wherein the first switching transient in the first semiconductor switch comprises an ON/OFF transition, and wherein the second switching transient in the second semiconductor switch comprises an ON/OFF transition (see explanation with respect to claim 1, above, and see col. 11: 8-16).
In re claim 17, Pieszala discloses wherein the first switching transient in the first semiconductor switch comprises an OFF/ON transition, and wherein the second switching transient in the second semiconductor switch comprises an OFF/ON transition (see explanation with respect to claim 1, above, and see col. 11: 8-16).
Allowable Subject Matter
Claims 8-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
It is also noted that if Applicant is able to properly invoke one of the prior art exceptions under 35 U.S.C. 102(b)(2) in order to disqualify the applied Pieszala reference, then all claims 1-20 would be allowable.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 8, the closest prior art in Pieszala discloses the invention according to claims 1, 6 and 7 as explained above, but does not further disclose the particular case in which the first PWM signal includes a first frequency and a first duty cycle, wherein the second PWM signal includes a second frequency and a second duty cycle; wherein the first frequency is equal to the second frequency, wherein the first duty cycle is equal to the second duty cycle, and wherein the first duty cycle lags the second duty cycle.
With respect to claim 9, the closest prior art in Pieszala discloses the invention according to claims 1, 6 and 7 as explained above, but does not further disclose the particular case in which the first PWM signal includes a first frequency and a first duty cycle, wherein the second PWM signal includes a second frequency and a second duty cycle; wherein the first frequency is equal to the second frequency, wherein the first duty cycle is equal to the second duty cycle, and wherein the first duty cycle leads the second duty cycle.
With respect to claim 10, the closest prior art in Pieszala discloses the invention according to claims 1, 6 and 7 as explained above, but does not further disclose the particular case in which the first PWM signal includes a first frequency and a first duty cycle, wherein the second PWM signal includes a second frequency and a second duty cycle; wherein the first frequency is equal to the second frequency, and wherein the first duty cycle is greater than the second duty cycle.
With respect to claim 11, the closest prior art in Pieszala discloses the invention according to claims 1, 6 and 7 as explained above, but does not further disclose the particular case in which the first PWM signal includes a first frequency and a first duty cycle, wherein the second PWM signal includes a second frequency and a second duty cycle; wherein the first frequency is equal to the second frequency, and wherein the first duty cycle is less than the second duty cycle.
With respect to claims 1-20, aside from Pieszala as applied above in this Office action, the next closest prior art to the claimed inventions is Tsurumaru (US 2018/0159521), which discloses control circuitry for a hybrid switching module in a multi-phase inverter (Figs. 3, 4). The control circuitry includes a gate driver with first and second resistance circuits (Fig. 4: Rg1, Rg2, respectively) corresponding to first and second semiconductor switches (Fig. 4: 12_1, 12_2) having differing performance characteristics ([0073]), and specifically includes operational control for synchronizing the operation of the first and second semiconductor switches ([0079]). Tsurumaru does not disclose that the resistance circuits are variable resistance circuits.
Although variable gate resistance circuits used in this particular application environment are known as in, e.g., Suh et al. (US Patent 10,931,276; see Fig. 10C and corresponding description at col. 2: 44-47) for tuning the gate drive characteristics of the hybrid switch module, it still would not have been obvious to modify the system of Tsurumaru to include variable gate resistance circuits because Tsurumaru specifically teaches away from such modification. That is, Tsurumaru at [0082] discloses that, “Work of correcting the gate resistance for each IGBT becomes unnecessary by performing the characteristic inspection of each IGBT using the semiconductor device for control and thus it is possible to reduce a time taken for the adjustment work.”. Thus, Tsurumaru’s disclosed invention specifically obviates the need for variable resistance gate circuits because it inspects each switching device and automatically corrects for resistance variations in each gate drive path.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2004/0196678 is cited as being the US and English language equivalent of DE 10356468, which was cited by Applicant in an IDS.
US 2014/0001839 is cited as being the US and English language equivalent of DE 102013212262, which was cited by Applicant in an IDS.
US 2018/0375508 discloses a power switching apparatus for synchronizing turn ON/OFF of switches in a hybrid switch module using fixed balancing resistors.
US Patent 10,505,538 shares a common applicant with the instant application and discloses a dynamic gate drive system and control method having similar features.
US 2020/0076292 is cited as being the US and English language equivalent of DE 112018002634, which was cited by Applicant in an IDS.
US 2020/0186140 is cited as being the US and English language equivalent of DE 112018004716, which was cited by Applicant in an IDS.
US 2020/0350907 discloses a drive circuit for driven switches with synchronized switching obtained by synchronizing logic signals for controlling the switches.
US 2024/0259015 is cited as being the US and English language equivalent of WO 2023/079820, which was cited by Applicant in an IDS.
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/FRED E FINCH III/Primary Examiner, Art Unit 2838