Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 5-7 and 16 of U.S. Patent No. 11,984,860 (thereafter referred to as Patent ‘860). Although the claims at issue are not identical, they are not patentably distinct from each other.
As for claim 1, Patent ‘860 discloses a circuit (see claim 1 of Patent’860), comprising:
an amplifier (amplifier, see claim 1, line 2 of Patent ‘860);
a bias voltage node (bias voltage node, see claim 1, line 8);
a first set of switches (first set of switches, see claim 1, lines 10-14) coupled to the amplifier and the bias voltage node;
a first feedback branch (first feedback branch, see claim 1, lines 15-18) coupled to the amplifier, the first feedback branch including a first RC network including a first and a second capacitance;
a second feedback branch (second feedback branch, see claim 1, lines 19-22) to the amplifier, the second feedback branch including a second RC network including a third and a fourth capacitance;
the first and second feedback branches further including:
a second set of switches (second set of switches, see lines 24-26); and
a third set of switches (third set of switches, see lines 27-29);
wherein the switches in the second set of switches are configured to selectively
couple one of the first and second capacitances in the first feedback branch and one of the third
and fourth capacitances in the second feedback branch to the amplifier in response to a first reset
signal (second reset, see claim 1, lines 31-37 of Patent ‘860); and
the switches in the third set of switches are configured to selectively couple the one of the
first and second capacitances in the first feedback branch and the one of the third and fourth
capacitances in the second feedback branch to the amplifier in response to a second reset signal (second reset, see claim 1, lines 38- 44 of Patent ‘860).
As for claim 2, Patent ‘860 discloses the circuit of claim 1, wherein the amplifier has a first input node, a second input node, a first output node, and a second output node (see claim 1, lines 2-7 of Patent ‘860).
As for claim 3, Patent ‘860 discloses circuit of claim 2, wherein the first feedback branch is coupled between the first output node and the first input node of the amplifier and the second feedback
branch is coupled between the second output node and the second input node of the amplifier (see claim 1, lines 15-16 and 19-20 of Patent ‘860).
As for claim 4, Patent ‘860 discloses circuit of claim 2, wherein the second set of switches is coupled between the first and second input nodes of the amplifier and the first, second, third, and fourth capacitances (see claim 1, lines 24-26 of Patent ‘860).
As for claim 5, Patent ‘860 discloses circuit of claim 2, wherein the third set of switches is coupled between the first and second output nodes of the amplifier and the first, second, third, and fourth capacitances (see claim 1, lines 27-29 of Patent ‘860).
As for claim 6, Patent ‘860 discloses circuit of claim 2, wherein the first set of switches includes an output switch coupled between the first output node and the second output node (see claim 1, lines 13-14 of Patent ‘860).
As for claim 7, Patent ‘860 discloses a circuit, comprising:
an amplifier circuit (amplifier, see claim 1, line 2 of Patent ‘860);
a capacitive sensor circuit (see claim 1, lines 4-6 of Patent ‘860) coupled to a first and second input of the amplifier circuit, the capacitive sensor circuit including a plurality of sensing capacitances;
a first set of switches (first set of switches, see claim 1, lines 10-14) coupled to the capacitive sensor circuit;
a first feedback branch (first feedback branch, see claim 1, lines 15-18) coupled between the first input and a first output of the amplifier
circuit, the first feedback branch including a first capacitance and a second capacitance;
a second feedback branch (second feedback branch, see claim 1, lines 19-22) coupled between the second input and a second output of the amplifier circuit, the second feedback branch including a third capacitance and a fourth capacitance;
a second set of switches (second set of switches, see lines 24-26) that selectively couple one of the first and second capacitances in the first feedback branch and one of the third and fourth capacitances in the second feedback branch to the amplifier; and
a third set of switches (third set of switches, see lines 27-29).
As for claim 8, Patent’860 does not specifically disclose: a plurality of sensing capacitances are coupled in parallel. A person of ordinary skill in the art would recognize that using a plurality of sensing capacitances coupled in parallel does not make the current application patentably distinct from the cited Patent’860.
As for claim 9, Patent ‘860 discloses circuit of claim 7, wherein the first feedback branch includes a first resistor and the second feedback branch includes a second resistor (i.e., the first RC network and the second RC network in claim 1, lines 15-22 of Patent ‘860).
As for claim 10, Patent ‘860 discloses circuit of claim 7, wherein the first capacitance is coupled in parallel with the second capacitance and the third capacitance is coupled in parallel with the fourth
Capacitance (see claims 6 and 7 of Patent ‘860).
As for claim 11, Patent’860 discloses the circuit if claim 9, wherein the first resistor has a first resistance equal to a second resistance of the second resistor (see claims 5-7 of Patent ‘860).
As for claim 12, Patent ‘860 discloses circuit of claim 7, wherein the first set of switches is driven by a first reset signal and the second set of switches is driven by a second reset signal (see claim 1, lines 10-11 and lines 31-37 of Patent ‘860).
As for claim 13, Patent ‘860 discloses circuit of claim 12, wherein the first reset signal has a first value for a first time interval and switches to a second value after the first time interval (see claim 1, lines 45-48 of Patent ‘860).
As for claim 14, Patent ‘860 discloses circuit of claim 13, wherein, in response to the first reset signal switching to the second value, the second reset signal maintains the first value for a second time
interval that is longer than the first time interval (see claim 1, lines 48-53 of Patent ‘860).
As for claim 15, Patent ‘860 discloses circuit of claim 7, wherein the switches in the third set of switches are configured to selectively couple the one of the first and second capacitances in the first feedback branch and the one of the third and fourth capacitances in the second feedback branch to the
amplifier in response to a reset signal (see claim 1, lines 38-44 of Patent ‘860).
As for claim 16, Patent ‘860 discloses circuit of claim 7, wherein the first, second, third, and fourth capacitances are all equal (see claim 5 of Patent ‘860).
As for claim 17, Patent ‘860 discloses method (see method claim 16 of Patent ‘860) of operating a circuit, comprising:
forming a bias voltage level in a bias voltage node, the bias voltage node coupled to a
first set of switches and a capacitive sensor circuit, the capacitive sensor circuit coupled to a first
and second input of an amplifier circuit (see claim 16, lines 3-4);
driving the first set of switches, based on a first reset signal, to couple the first and second
inputs of the amplifier circuit to the bias voltage node (see claim 16, lines 5-9);
driving a second set of switches, based on a second reset signal, to selectively couple one
of a first and second capacitances in a first feedback branch to the first and second input nodes of
the amplifier, the first feedback branch being coupled between the first input and a first output of
the amplifier circuit (see claim 16, lines 10-15);
driving a third set of switches, based on the second reset signal, to couple one of the first
and second capacitances in the first feedback branch to the first output node and a second output
node of the amplifier (see claim 16, lines 16-32);
switching the first reset signal from a first value to a second value after a first time
interval (see claim 16, lines 23-24); and
maintaining, in response to the switching the first reset signal from the first value to the
second value, the second reset signal at the first value for a second time interval that is greater
than the first time interval (see claim 16, lines 25-29).
As for claim 18, Patent ‘860 discloses method of claim 17, wherein the driving the first set of switches includes driving the first set of switches to couple the first output node and the second output
node of the amplifier circuit (see claim 16, lines 5-9 of Patent ‘860).
As for claim 19, Patent ‘860 discloses method of claim 17, further comprising:
selectively coupling one of a third and fourth capacitances in a second feedback branch to
the first and second input nodes of the amplifier, the second feedback branch being coupled
between the second input and the second output node of the amplifier circuit by driving the
second set of switches, based on the second reset signal (see claim 16, lines 10-15 of Patent ‘860).
As for claim 20, Patent ‘860 discloses method of claim 17, further comprising:
coupling one of the third and fourth capacitances in the second feedback branch to the
first output node and the second output node of the amplifier circuit by driving the third set of
switches, based on the second reset signal (see claim 16, lines 16-22 of patent ‘860).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 7-17 and 19-20 are rejected under 35 U.S.C. 102(a)(1), 102(a)(2) as being anticipated by Nicollini et al. (U. S. Pub. 2017/0187335).
As for claim 7, Nicollini et al. discloses a circuit (1 in Fig. 1), comprising:
an amplifier circuit (2);
a capacitive sensor circuit (Ci1 and Ci2) coupled to a first and second input of the amplifier circuit (2), the capacitive sensor circuit including a plurality of sensing capacitances (Ci1 and Ci2)(also see [0025]);
a first set of switches (switches RESET1 and RESET2) coupled to the capacitive sensor circuit (Ci1 and Ci2);
a first feedback branch (see the feedback branch on the top) coupled between the first input (negative input) and a first output of the amplifier circuit (2), the first feedback branch including a first capacitance (Cr1) and a second capacitance (CRES1);
a second feedback branch (see the feedback branch on the bottom) coupled between the second input (positive input) and a second output of the amplifier circuit (2), the second feedback branch including a third capacitance (Cr2) and a fourth capacitance (CRES2);
a second set of switches (RD1 and RD3) that selectively couple one of the first and second capacitances (i.e., RD1 selectively couple the second capacitance CRES1) in the first feedback branch and one of the third and fourth capacitances (i.e., RD3 selectively couple the fourth capacitance CRES2) in the second feedback branch to the amplifier (2); and
a third set of switches (RD2 and RD4).
As for claim 8, Nicollini et al. discloses circuit of claim 7, wherein the plurality of sensing capacitances (Ci1 and Ci2) are coupled in parallel (see Fig. 1).
As for claim 9, Nicollini et al. discloses circuit of claim 7, wherein the first feedback branch (see the feedback branch on the top) includes a first resistor (Rr1) and the second feedback branch (see the feedback branch on the bottom) includes a second resistor (Rr2).
As for claim 10, Nicollini et al. discloses circuit of claim 7, wherein the first capacitance (Cr1) is coupled in parallel with the second capacitance (CRES1) and the third capacitance (Cr2) is coupled in parallel with the fourth capacitance (CRES2).
As for claim 11, Nicollini et al. discloses circuit of claim 9, wherein the first resistor (Rr1) has a first resistance equal to a second resistance of the second resistor (Rr2; see [0016]).
As for claim 12, Nicollini et al. discloses circuit of claim 7, wherein the first set of switches (RESET1, RSET2) is driven by a first reset signal (the first control signal sRESET) and the second set of switches (RD1, RD3) is driven by a second reset signal (the second control signal sRD; also see [0032]).
As for claim 13, Nicollini et al. discloses circuit of claim 12, wherein the first reset signal (sRESET) has a first value (1) for a first time interval (t2) and switches to a second value (0) after the first time interval (i.e., the switches RESET 1 and RESET 2 can be closed for a first time interval and then switch to open; also see Fig. 2).
As for claim 14, Nicollini et al. discloses circuit of claim 13, wherein, in response to the first reset signal (sRESET) switching to the second value (0), the second reset signal (sRD) maintains the first value (1) for a second time interval ( t3) that is longer than the first time interval (t2) (also see Fig. 2).
As for claim 15, Nicollini et al. discloses circuit of claim 7, wherein the switches in the third set of switches (RD2 and RD4) are configured to selectively couple the one of the first and second capacitances in the first feedback branch and the one of the third and fourth capacitances in the second feedback branch to the amplifier in response to a reset signal (i.e., RD2 selectively couple the second capacitance CRES1 in the first feedback and RD4 selectively couple the fourth capacitance CRES2 in the second feedback).
As for claim 16, Nicollini et al. discloses circuit of claim 7, wherein the first, second, third, and fourth capacitances are all equal (see [0016] and [0017] and [0021]).
As for claim 17, Nicollini et al. discloses a method of operating a circuit, comprising:
forming a bias voltage level (Vin)in a bias voltage node (N), the bias voltage node (N) coupled to a first set of switches (switches RESET1 and RESET2) and a capacitive sensor circuit (Ci1 and Ci2), the capacitive sensor circuit coupled to a first and second input of an amplifier circuit (2);
driving the first set of switches (switches RESET1 and RESET2), based on a first reset signal (the first control signal sRESET), to couple the first and second inputs of the amplifier circuit (2) to the bias voltage node;
driving a second set of switches (RD1 and RD3), based on a second reset signal (the second control signal sRD; also see [0032]), to selectively couple one of a first and second capacitances (CRES1) in a first feedback branch (the top feedback) to the first and second input nodes of the amplifier(2), the first feedback branch being coupled between the first input (- input)and a first output Vout) of
the amplifier circuit(2);
driving a third set of switches(RD2 and RD4), based on the second reset signal(the second control signal sRD), to couple one of the first and second capacitances(CRES1) in the first feedback branch to the first output node and a second output node (Vout) of the amplifier (2);
switching the first reset signal (sRESET) from a first value (1) to a second value (0) after a first time interval (t2); and maintaining, in response to the switching the first reset signal from the first value to the second value, the second reset signal (sRD) at the first value (1) for a second time interval (t3) that is greater than the first time interval (t2).
As for claim 19, Nicollini et al. discloses method of claim 17, further comprising:
selectively coupling one of a third and fourth capacitances (CRES2) in a second feedback branch (the bottom feedback branch) to the first and second input nodes of the amplifier (2), the second feedback branch being coupled between the second input (+ input) and the second output node (Vout) of the amplifier circuit (2) by driving the second set of switches (RD1, RD3), based on the second reset signal (sRD),
As for claim 20, Nicollini et al. discloses method of claim 17, further comprising:
coupling one of the third and fourth capacitances (CRES2) in the second feedback branch (the bottom feedback branch) to the first output node and the second output node(Vout)of the amplifier circuit (2)by driving the third set of switches (RD2, RD4), based on the second reset signal (sRD).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Nicollini et al. (U. S. Pub. 2017/0187335).
As for claim 18, Nicollini et al. discloses the method of claim 17 as discussed above.
Still referring to claim 18, Nicollini et al. does not specifically disclose wherein driving the first set of switches includes couple the first output node and the second output node.
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to further modify Nicollini et al. to disclose driving the first set of switches includes driving the first set of switches to couple the first output node and the second output node, for the purpose of resetting or precharging the two outputs when needed.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (U. S. Pub. 2011/0279148) in view of Nicollini et al. (U. S. Pub. 2017/0187335).
As for claim 1, Watanabe discloses a circuit (100 in Fig. 1), comprising:
an amplifier (110);
a bias voltage node (Vicm);
a first set of switches (S11p, S9p, S9n, S11n) coupled to the amplifier (110) and the bias voltage node (Vicm);
a first feedback branch (the top feedback branch) coupled to the amplifier (110), the first feedback branch including a first RC network including a first and a second capacitance (Chp and Cfp);
a second feedback branch (the bottom feedback branch) to the amplifier, the second feedback branch including a second RC network including a third and a fourth capacitance (Chn, Cfn);
the first and second feedback branches further including:
a second set of switches (S9p, S5p, S5n, S9n); and
a third set of switches (S10p, S6p, S6n, S10n);
wherein the switches in the second set of switches (S9p, S5p, S5n, S9n) are configured to selectively couple one of the first and second capacitances (Chp and Cfp) in the first feedback branch and one of the third and fourth capacitances (Chn, Cfn) in the second feedback branch to the amplifier in response to a first reset signal; and
the switches in the third set of switches (S10p, S6p, S6n, S10n) are configured to selectively couple the one of the first and second capacitances (Chp and Cfp) in the first feedback branch and the one of the third and fourth capacitances (Chn, Cfn) in the second feedback branch to the amplifier in response to a second reset signal.
Still referring to claim 1, Watanabe does not specifically disclose that the first feedback branch including a first RC network, and the second feedback branch including a second RC network.
Nicollini et al. discloses a first feedback branch including a first RC network and a second feedback branch including a second RC network (see the first and second RC network including resistors Rr1, Rr2 and the capacitors in Fig. 1).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to further modify Watanabe to incorporate the use of a first RC network in the first feedback branch and a second RC network in the second feedback branch, for the purpose of improving DC gain, and with better stability for the amplifier.
As for claim 2, Watanabe discloses the circuit of claim 1, wherein the amplifier (110) has a first input node (- input), a second input node(+ input), a first output node(Vop), and a second output node (Von)(see Fig. 1).
As for claim 3, Watanabe discloses circuit of claim 2, wherein the first feedback branch is coupled between the first output node (Vop) and the first input node (- input) of the amplifier (110) and the second feedback branch is coupled between the second output node (Von) and the second input node (+ input) of the amplifier (see Fig. 1).
As for claim 4, Watanabe discloses circuit of claim 2, wherein the second set of switches (S9p, S5p, S5n, S9n) is coupled between the first and second input nodes (-input and +input) of the amplifier (110) and the first, second, third, and fourth capacitances (see the connections to Chp, Cfp, Chn, Cfn in Fig. 1).
As for claim 5, Watanabe discloses circuit of claim 2, wherein the third set of switches (S10p, S6p, S6n, S10n) is coupled between the first and second output nodes (Vop and Von) of the amplifier (110) and the first, second, third, and fourth capacitances (see the connections to Chp, Cfp, Chn, Cfn in Fig. 1)
As for claim 6, Watanabe in view of Nicollini et al. discloses circuit of claim 2 as discussed above. Watanabe in view of Nicollini et al. does not specifically disclose wherein the first set of switches includes an output switch coupled between the first output node and the second output node.
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to further modify Watanabe in view of Nicollini et al. to incorporate the use of an output switch coupled between the first output node and the second output node, for the purpose of reset or precharge the two outputs when needed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMY HE whose telephone number is (571)272-2230. The examiner can normally be reached 9:00am--5:00pm.
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/AMY HE/Primary Examiner, Art Unit 2858
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