DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Inventorship
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim Objections
Claims 1-7, 9, 10 and 13-16 are objected to because of the following informalities:
Claim 1 recites the limitation "the switching signal" in line 6. There is insufficient antecedent basis for this limitation in the claim. Claim 1 line 3 recites a switching signal, claim 1 line 5 recites a switching signal (i.e. a processed switching signal). The applicant should label each switching separately and independently in order to avoid confusion when referring back to a specific switching signal.
Claims 2-7 inherit the same from claim 1.
Claim 2 recites the limitation "the switching signal" in line 8. There is insufficient antecedent basis for this limitation in the claim. Claim 1 line 3 recited a switching signal, claim 1 line 5 recited a switching signal (i.e. a processed switching signal), claim 1 line 6 recites a switching signal (i.e. another switching signal), etc. The applicant should label each switching separately and independently in order to avoid confusion when referring back to a specific switching signal.
Claim 3 inherits the same from claim 2.
Claim 4 recites the limitation "the switching signal" in line 10. There is insufficient antecedent basis for this limitation in the claim. Claim 1 line 6 recited a switching terminal signal (i.e. another switching terminal signal). Claim 4 line 8 also recites a switching terminal signal, etc. The applicant should label each switching terminal separately and independently in order to avoid confusion when referring back to a specific switching terminal signal.
Claim 5 inherits the same from claim 4.
Claim 9 recites the limitation "the switching signal" in line 8. There is insufficient antecedent basis for this limitation in the claim. Claim 8 line 4 recited a switching signal (i.e. a first switching signal), claim 8 line 4 recited another switching signal (i.e. a first switching terminal signal), claim 8 line 9 recites a switching signal (i.e. a second switching signal), claim 8 line 12 recited a switching signal (i.e. a processed switching signal) etc. The applicant should label each switching separately and independently in order to avoid confusion when referring back to a specific switching signal.
Claim 10 inherits the same from claim 9.
Claim 13; recites the limitation "the switching signal" in line 5. There is insufficient antecedent basis for this limitation in the claim. claim 13 line 3 recites a switching signal. Claim 13 line 5 recites a switching signal, (i.e. a processed switching signal). The applicant should label each switching separately and independently in order to avoid confusion when referring back to a specific switching signal.
Claims 14-16 inherit the same from claim 13.
Claim 14; recites the limitation "the step" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 16; recites the limitation "the step" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Please review all claims to ensure no other antecedent basis errors exist or repeat.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 7 and 13 is/are rejected under 35 U.S.C. 102a2 as being anticipated by Yamada (US 20240333132).
Claims 1 and 7; Yamada disclose a voltage conversion device (e.g. fig. 1), comprising: a first input terminal to obtain a first input voltage (Vrec); a feedback controller (43) to provide a switching signal based (e.g. Vq1/Vq2) on a feedback voltage (e.g. Vfb), wherein the feedback voltage is generated based on an output voltage (e.g. Vout) of the voltage conversion device; a masking circuit (e.g. 212) to generate a processed switching signal (e.g. mask) by masking a part of time period of the switching signal (e.g. Vq1) according to another switching signal (e.g. 202, CMP 210); and a driving circuit (220), coupled to the first input terminal (through Vzcd2) and the masking circuit (212) to provide the output voltage (Vout) according to the first input voltage and the processed switching signal (mask).
Claim 13; Yamada discloses a method for a voltage conversion device, comprises: providing a switching signal based on a feedback voltage (Vfb), wherein the feedback voltage is generated based on an output voltage (Vout) of the voltage conversion device; generating a processed switching signal (mask) by masking a part of time period of the switching signal (Vq1/Vq2) according another switching signal (202, 210); and providing the output voltage (vout) according to a first input voltage (Vrec) and the processed switching signal (mask).
Allowable Subject Matter
Claims 2-6, 9, 10 and 14-16 would be allowable if rewritten to overcome the objection(s) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 8, 11 and 12 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 2 and 3; prior art fails to disclose or fairly suggest, inter alia, the masking circuit comprises: an edge trigger detector to determine a triggering time point according to one of the another switching signal and the another switching terminal signal; a mask signal generator, coupled to the edge trigger detector to generate a mask signal, wherein the mask signal comprises a masking pulse corresponding to the triggering time point; and a control logic circuit, coupled to the mask signal generator to generate the processed switching signal by masking the part of time period of the switching signal based on the masking pulse.
Claims 4 and 5; prior art fails to disclose or fairly suggest, inter alia, a voltage comparator to generate a setting signal by comparing the output voltage and a reference voltage; an edge trigger detector to determine a triggering time point of one of the another switching signal and the another switching terminal signal; a sample hold circuit, coupled to the voltage comparator and the edge trigger detector to determine that the setting signal has a complete pulse after the triggering time point, and to determine whether a first state corresponding to a switching terminal signal in the voltage conversion device at the triggering time point is the same as a second state corresponding to the switching terminal signal at a time point when the setting signal has the complete pulse, wherein in a case where the first state is the same as the second state, the sample hold circuit records a time period between the triggering time point and the time point when the setting signal has the complete pulse as a masking time period; and a control logic circuit, coupled to the sample hold circuit to receive and record the masking time period, generate an average masking time period by averaging the masking time period with a plurality of historical masking time periods, and generate the processed switching signal by masking the part of time period of the switching signal based on the average masking time period.
Claim 6; prior art fails to disclose or fairly suggest, inter alia, a driver to generate a first switching control signal and a second switching control signal based on the processed switching signal; a control terminal of the first switch receives the first switching control signal; a second switch, wherein a first terminal of the second switch is coupled to a second terminal of the first switch, and a control terminal of the second switch receives the second switching control signal; and an inductor-capacitor circuit, wherein an input terminal of the inductor-capacitor circuit is coupled to the second terminal of the first switch, and the inductor-capacitor circuit is coupled to an output terminal of the voltage conversion device, wherein the driver controls the first switch and the second switch through the first switching control signal and the second switching control signal to provide the output voltage at the output terminal of the voltage conversion device.
Claims 8-12; prior art fails to disclose or fairly suggest, inter alia, a power supply system, comprising: a first voltage conversion device, coupled to a first ground terminal and a second ground terminal, wherein the first voltage conversion device converts a first input voltage into a first output voltage according to a first switching signal and a first switching terminal signal; and a second voltage conversion device, wherein the second voltage conversion device comprises: a first input terminal to obtain the first input voltage; a feedback controller, coupled to the second ground terminal to provide a second switching signal based on a feedback voltage, wherein the feedback voltage is generated based on a second output voltage of the second voltage conversion device; a masking circuit, coupled to the feedback controller to generate a processed switching signal by masking a part of time period of the second switching signal according to one of the first switching signal and the first switching terminal signal; and a driving circuit, coupled to the first input terminal and the masking circuit to provide the second output voltage according to a second input voltage and the processed switching signal.
Claims 14 and 15; prior art fails to disclose or fairly suggest, inter alia, generating the processed switching signal by masking the part of time period of the switching signal according to the one of the another switching signal and the another switching terminal signal of the another voltage conversion device comprises: determining a triggering time point of the one of the another switching signal and the another switching terminal signal; generating a mask signal according to the triggering time point, wherein the mask signal comprises a masking pulse corresponding to the triggering time point; and generating the processed switching signal by masking the part of time period of the switching signal based on the masking pulse in the mask signal.
Claim 16; prior art fails to disclose or fairly suggest, inter alia, generating the processed switching signal by masking the part of time period of the switching signal according to the one of the another switching signal and the another switching terminal signal of the another voltage conversion device comprises: generating a setting signal by comparing the output voltage and a reference voltage; determining a triggering time point of the one of the another switching signal and the another switching terminal signal; determining that the setting signal has a complete pulse after the triggering time point; when the setting signal after the triggering time point has the complete pulse, determining whether a first state corresponding to a switching terminal signal in the voltage conversion device at the triggering time point is the same as a second state corresponding to the switching terminal signal at a time point when the setting signal has the complete pulse; in a case where the first state is the same as the second state, recording a time period between the triggering time point and the time point when the setting signal has the complete pulse as a masking time period; recording the masking time period; generating an average masking time period by averaging the masking time period with a plurality of historical masking time periods; and generating the processed switching signal by masking the part of time period of the switching signal based on the average masking time period.
Conclusion
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/GARY L LAXTON/Primary Examiner, Art Unit 2838 1/07/2026