Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 4/23/26 have been fully considered but they are not persuasive.
Regarding claim 1, Applicant argues “Applicant respectfully disagrees at least because, the Office Action did not explain, and it is unclear to Applicant, why an OR gate would be needed in Lamb, and thus it is unclear one of ordinary skill in the art would incorporate the OR gate used to combine the comparison results of different corresponding transistor driving signals from two systems into Lamb where multiple copies of the same data are compared...Therefore, claim 1 is patentable over the references cited in the Office Action”.
Examiner respectfully disagrees. In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, the reference of Schwesig teaches an output signal from an XOR gate which is input to an OR gate to provide a fault signal if driving signals do not coincide with each other. An OR gate added to the Lamb reference can provide uses such as using the error signal provided by the XOR gate 32 into another or separate circuit which may activate other circuits based on the OR gate output. For example, in Fig. 4B of Lamb, an error signal is supplied to another OR gate to activate a clock. Therefore, Lamb also teaches the use of an OR gate to activate additional circuits. Therefore, Examiner maintains the rejection of claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1, 3, 6, 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lamb, US 20090249174 in view of Schwesig, US 20020063548
Regarding claim 1, Lamb discloses a fault-detection circuit comprising:
a first NOR gate having first, second and third NOR gate inputs and a first NOR gate output, wherein the first, second and third NOR gate inputs are adaptable to be coupled to respective outputs of three identical circuits (Fig. 1 & 2b; NOR gate 29 with inputs a, b, c being copies of input 10);
an AND gate having first, second and third AND gate inputs and an AND gate output, wherein the first, second and third respective AND gate inputs are coupled to the first, second and third NOR gate inputs, respectively (Fig. 2B; AND gate 31 inputs coupled to a,b,c); and
a second NOR gate having fourth and fifth NOR gate inputs and a second NOR gate output, wherein the fourth NOR gate input is coupled to the AND gate output, and the fifth NOR gate input is coupled to the first NOR gate output (Fig. 2B; NOR gate 32 Having inputs coupled to NOR gate 29 output and AND gate output 31).
Lamb does not explicitly disclose an OR gate having first and second OR gate inputs and an OR gate output, wherein the first OR gate input is coupled to the second NOR gate output. Schwesig teaches an OR gate having first and second OR gate inputs and an OR gate output wherein the first OR gate input is coupled to a second XOR gate output (Fig. 4; OR gate O1 coupled to XOR gates XOR1). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Schwesig into Lamb for the benefit of providing a cumulative fault result.
Regarding claim 3, Lamb is silent in further comprising a low pass filter having a filter input and a filter output, wherein the filter input is coupled to the OR gate output. Schwesig teaches a low pass filter having a filter input and a filter output, wherein the filter input is coupled to the OR gate output (Fig. 4; gate O1 to resistor RS10 and capacitor C1 considered the low lass filter). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Schwesig into Lamb for the benefit of using a filter to remove glitches and noise in the signal.
Regarding claim 6, Lamb is silent in wherein the AND gate is a first AND gate, and the fault-detection circuit is further comprising: a third NOR gate having sixth, seventh and eighth NOR gate inputs and a third NOR gate output, wherein the sixth, seventh and eighth respective NOR gate inputs are adaptable to be coupled to respective outputs of three additional identical circuits; a second AND gate having fourth, fifth and sixth AND gate inputs and a second AND gate output, wherein the fourth, fifth and sixth respective AND gate inputs are coupled to the sixth, seventh and eighth NOR gate inputs, respectively; and a fourth NOR gate having ninth and tenth NOR gate inputs and a fourth NOR gate output, wherein the ninth NOR gate input is coupled to the second AND gate output, the tenth NOR gate input is coupled to the third NOR gate output, and the fourth NOR gate output is coupled to the second OR gate input. However, Lamb discloses a NOR gate having three inputs and one output, an AND gate having three inputs and an output, wherein the inputs of the NOR gate are coupled to the inputs of the AND gate and wherein an additional NOR gate having two inputs which are coupled to the NOR gate output and the AND gate output (See fig, 2b; same elements as that of claim 1). It would have been obvious to one having ordinary skill in the art at the time the invention was made to provide a an additional circuit (Fig. 2b of Lamb), since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. It would be within the level of ordinary skill in the art to provide additional circuits so that multiple devices can be monitored for errors.
Lamb is silent in wherein the fourth NOR gate output is coupled to the second OR gate input. Schwesig teaches an OR gate, wherein an OR gate input is coupled to a second XOR gate output (Fig. 4; OR gate O1 coupled to XOR gates XOR1). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Schwesig into Lamb for the benefit of providing a cumulative fault result.
Regarding claim 13, Lamb teaches the first NOR gate input and the first AND gate input are coupled to an output of a first circuit; the second NOR gate input and the second AND gate input are coupled to an output of a second circuit; and the third NOR gate input and the third AND gate input are coupled to an output of a third circuit, wherein the first, second, and third circuits have the same design and receive the same input (Fig. 1; input d_in received by circuits 11, 12, and 13 then output to the NOR gate 29 and AND gate 31).
Claim(s) 4, 5, 7, 9, 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lamb, US 20090249174 in view of Schwesig, US 20020063548 in view of Bond et al., US 5349654
Regarding claim 4, Lamb as modified is silent in further comprising a driver circuit having a driver input and a driver output, wherein the driver input is coupled to the filter output. Schwesig teaches a driver circuit having a driver input and a driver output, wherein the driver input is coupled to a gate output of a voter circuit (Fig. 3; buffer 144 connected to the voter error logging output). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Schwesig into Lamb for the benefit of using a buffer so that signal degradation can be reduced.
Regarding claim 5, Lamb is silent in further comprising a latch having a latch input and a latch output, wherein the latch input is coupled to the driver output. Schleswig teaches a latch having a latch input and a latch output, wherein the latch input is coupled to the filter output (Fig. 4; latch FF1). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Schleswig into Lamb for the benefit of providing a cumulative fault result.
Regarding claim 7, Lamb as modified discloses all the limitations of the fault-detection circuit of claim 3. Schwesig teaches wherein the low pass filter includes a resistor- capacitor filter (Fig. 4; RS10 -C1). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Schwesig into Lamb for the benefit of using a filter to remove glitches and noise in the signal.
Regarding claim 9, Lamb discloses the fault-detection circuit of claim 5 and further comprising a majority voter circuit having first, second, and third voter inputs and a voter output (Fig. 1-2a; majority voting circuit 17), wherein the first voter input is coupled to the first AND gate input and receives a first signal (Fig. 1-2a; “a” input coupled to AND gate 31), the second voter input is coupled to the second AND gate input and receives a second signal (Fig. 1-2a; “b” input coupled to AND gate 31), the third voter input is coupled to the third AND gate input and receives a third signal (Fig. 1-2a; “c” input coupled to AND gate 31 ), and the majority voter circuit is configured to provide at the voter output a voter output signal equal to at least two of the first signal, the second signal and the third signal (¶[0029]; majority vote two-out-of-three).
Regarding claim 11, Lamb teaches wherein the voter output will be equal to a first signal responsive to the first, second and third signals having equal values, and the voter output will be equal to the second signal responsive to the second and third signals having equal values but having an unequal value to the first signal (¶[0029]-[0030]; 0 or 1 if two or more of the inputs are zero or 1).
Claim(s) 8, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lamb, US 20090249174 in view of Schwesig, US 20020063548 in view of Bond et al., US 5349654 in view of Liu et al., US 20210409016
Regarding claim 8, Lamb is silent in wherein a high signal on the latch output indicates a presence of a fault in at least one of the identical circuits. Liu teaches wherein a high signal on a latch output indicates a presence of a fault in a circuit (¶[0028], [0032]; fig. 2; latch 229 outputs fault trigger signal being high value when a fault is present). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Liu into Lamb as modified for the benefit of detecting faults in the circuits and providing a signal to other circuit elements for remedial action.
Regarding claim 12, Lamb is silent in wherein a high signal on the latch output indicates a presence of a fault in a circuit providing at least one of the first, second or third signals. Liu teaches wherein a high signal on a latch output indicates a presence of a fault in a circuit (¶[0028], [0032]; fig. 2; latch 229 outputs fault trigger signal being high value when a fault is present). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Liu into Lamb as modified for the benefit of detecting faults in the circuits and providing a signal to other circuit elements for remedial action.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lamb, US 20090249174 in view of Schwesig, US 20020063548 in view of Tobin, US 3524073
Regarding claim 10, Lamb teaches wherein the majority voter includes AND logic gates (Fig.2a; 25-28). Lamb is silent in wherein the majority voter circuit includes OR logic gates. Tobin discloses wherein the majority voter circuit includes OR logic gates and AND gates (Fig. 2; OR gate 20, 22; AND gate 24, 26). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Tobin into Lamb for the benefit of providing redundant circuit paths if there is a failure of logic elements.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/FEBA POTHEN/ Examiner, Art Unit 2858
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