DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/15/24 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 6, the claim recites “the fourth NOR gate output is coupled to the second OR gate input”. There is a lack of antecedent basis for “the second OR gate input”. It appears that claim 6 should depend from claim 2 since claim 2 recites the second OR gate input.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lamb, US 20090249174
Regarding claim 1, Lamb discloses a fault-detection circuit comprising:
a first NOR gate having first, second and third NOR gate inputs and a first NOR gate output, wherein the first, second and third NOR gate inputs are adaptable to be coupled to respective outputs of three identical circuits (Fig. 1 & 2b; NOR gate 29 with inputs a, b, c being copies of input 10);
an AND gate having first, second and third AND gate inputs and an AND gate output, wherein the first, second and third respective AND gate inputs are coupled to the first, second and third NOR gate inputs, respectively (Fig. 2B; AND gate 31 inputs coupled to a,b,c); and
a second NOR gate having fourth and fifth NOR gate inputs and a second NOR gate output, wherein the fourth NOR gate input is coupled to the AND gate output, and the fifth NOR gate input is coupled to the first NOR gate output (Fig. 2B; NOR gate 32 Having inputs coupled to NOR gate 29 output and AND gate output 31).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2, 3, 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lamb, US 20090249174 in view of Schwesig, US 20020063548
Regarding claim 2, Lamb is silent in further comprising an OR gate having first and second OR gate inputs and an OR gate output, wherein the first OR gate input is coupled to the second NOR gate output. Schwesig teaches an OR gate having first and second OR gate inputs and an OR gate output wherein the first OR gate input is coupled to a second XOR gate output (Fig. 4; OR gate O1 coupled to XOR gates XOR1). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Schwesig into Lamb for the benefit of providing a cumulative fault result.
Regarding claim 3, Lamb is silent in further comprising a low pass filter having a filter input and a filter output, wherein the filter input is coupled to the OR gate output. Schwesig teaches a low pass filter having a filter input and a filter output, wherein the filter input is coupled to the OR gate output (Fig. 4; gate O1 to resistor RS10 and capacitor C1 considered the low lass filter). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Schwesig into Lamb for the benefit of using a filter to remove glitches and noise in the signal.
Regarding claim 6, Lamb is silent in wherein the AND gate is a first AND gate, and the fault-detection circuit is further comprising: a third NOR gate having sixth, seventh and eighth NOR gate inputs and a third NOR gate output, wherein the sixth, seventh and eighth respective NOR gate inputs are adaptable to be coupled to respective outputs of three additional identical circuits; a second AND gate having fourth, fifth and sixth AND gate inputs and a second AND gate output, wherein the fourth, fifth and sixth respective AND gate inputs are coupled to the sixth, seventh and eighth NOR gate inputs, respectively; and a fourth NOR gate having ninth and tenth NOR gate inputs and a fourth NOR gate output, wherein the ninth NOR gate input is coupled to the second AND gate output, the tenth NOR gate input is coupled to the third NOR gate output, and the fourth NOR gate output is coupled to the second OR gate input. However, Lamb discloses a NOR gate having three inputs and one output, an AND gate having three inputs and an output, wherein the inputs of the NOR gate are coupled to the inputs of the AND gate and wherein an additional NOR gate having two inputs which are coupled to the NOR gate output and the AND gate output (See fig, 2b; same elements as that of claim 1). It would have been obvious to one having ordinary skill in the art at the time the invention was made to provide a an additional circuit (Fig. 2b of Lamb), since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. It would be within the level of ordinary skill in the art to provide additional circuits so that multiple devices can be monitored for errors.
Lamb is silent in wherein the fourth NOR gate output is coupled to the second OR gate input. Schwesig teaches an OR gate, wherein an OR gate input is coupled to a second XOR gate output (Fig. 4; OR gate O1 coupled to XOR gates XOR1). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Schwesig into Lamb for the benefit of providing a cumulative fault result.
Claim(s) 4, 5, 7, 9, 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lamb, US 20090249174 in view of Schwesig, US 20020063548 in view of Bond et al., US 5349654
Regarding claim 4, Lamb as modified is silent in further comprising a driver circuit having a driver input and a driver output, wherein the driver input is coupled to the filter output. Schwesig teaches a driver circuit having a driver input and a driver output, wherein the driver input is coupled to a gate output of a voter circuit (Fig. 3; buffer 144 connected to the voter error logging output). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Schwesig into Lamb for the benefit of using a buffer so that signal degradation can be reduced.
Regarding claim 5, Lamb is silent in further comprising a latch having a latch input and a latch output, wherein the latch input is coupled to the driver output. Schleswig teaches a latch having a latch input and a latch output, wherein the latch input is coupled to the filter output (Fig. 4; latch FF1). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Schleswig into Lamb for the benefit of providing a cumulative fault result.
Regarding claim 7, Lamb as modified discloses all the limitations of the fault-detection circuit of claim 3. Schwesig teaches wherein the low pass filter includes a resistor- capacitor filter (Fig. 4; RS10 -C1). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Schwesig into Lamb for the benefit of using a filter to remove glitches and noise in the signal.
Regarding claim 9, Lamb discloses the fault-detection circuit of claim 5 and further comprising a majority voter circuit having first, second, and third voter inputs and a voter output (Fig. 1-2a; majority voting circuit 17), wherein the first voter input is coupled to the first AND gate input and receives a first signal (Fig. 1-2a; “a” input coupled to AND gate 31), the second voter input is coupled to the second AND gate input and receives a second signal (Fig. 1-2a; “b” input coupled to AND gate 31), the third voter input is coupled to the third AND gate input and receives a third signal (Fig. 1-2a; “c” input coupled to AND gate 31 ), and the majority voter circuit is configured to provide at the voter output a voter output signal equal to at least two of the first signal, the second signal and the third signal (¶[0029]; majority vote two-out-of-three).
Regarding claim 11, Lamb teaches wherein the voter output will be equal to a first signal responsive to the first, second and third signals having equal values, and the voter output will be equal to the second signal responsive to the second and third signals having equal values but having an unequal value to the first signal (¶[0029]-[0030]; 0 or 1 if two or more of the inputs are zero or 1).
Claim(s) 8, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lamb, US 20090249174 in view of Schwesig, US 20020063548 in view of Bond et al., US 5349654 in view of Liu et al., US 20210409016
Regarding claim 8, Lamb is silent in wherein a high signal on the latch output indicates a presence of a fault in at least one of the identical circuits. Liu teaches wherein a high signal on a latch output indicates a presence of a fault in a circuit (¶[0028], [0032]; fig. 2; latch 229 outputs fault trigger signal being high value when a fault is present). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Liu into Lamb as modified for the benefit of detecting faults in the circuits and providing a signal to other circuit elements for remedial action.
Regarding claim 12, Lamb is silent in wherein a high signal on the latch output indicates a presence of a fault in a circuit providing at least one of the first, second or third signals. Liu teaches wherein a high signal on a latch output indicates a presence of a fault in a circuit (¶[0028], [0032]; fig. 2; latch 229 outputs fault trigger signal being high value when a fault is present). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Liu into Lamb as modified for the benefit of detecting faults in the circuits and providing a signal to other circuit elements for remedial action.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lamb, US 20090249174 in view of Tobin, US 3524073
Regarding claim 10, Lamb teaches wherein the majority voter includes AND logic gates (Fig.2a; 25-28). Lamb is silent in wherein the majority voter circuit includes OR logic gates. Tobin discloses wherein the majority voter circuit includes OR logic gates and AND gates (Fig. 2; OR gate 20, 22; AND gate 24, 26). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Tobin into Lamb for the benefit of providing redundant circuit paths if there is a failure of logic elements.
Conclusion
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/FEBA POTHEN/Examiner, Art Unit 2858
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