DETAILED ACTION
This action is responsive to the Application filed on 04/15/2024. Claims 1-3, 6-9, 11-15, 18-20 are pending in the case. Claims 1, 9, and 18 are independent claims. Claims 1, 6, 9, 11, 15, 18, 19, 20 are amended.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “a confinement apparatus configured to confine”, “one or more manipulation sources configured to generate”, “a controller configured to control” in claim 11.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Examiner notes the structure for the claimed “confinement apparatus” and how the structure performs the claimed function is described for example in specification para 0062-0066
Further, the structure for the claimed “manipulation sources” and how the structure performs the claimed function is described for example in specification para 0061-0065.
Further, the structure for the claimed “controller” and how the structure performs the claimed function is described for example in specification para 0103-0106.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3-8, 11, 13-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Google Quantum AI and Collaborators “Observation of non-Abelian exchange statistics on a superconducting processor” hereinafter Google.
Claim 1/11
Google teaches, A method for creating, braiding, and fusing non-Abelian anyons, the method comprising [from claim 11] A system configured for creating, braiding, and fusing non-Abelian anyons, the system comprising (abstract pg 1 “By implementing a unitary protocol23 to move the anyons, we experimentally verify the fusion rules of non-Abelian Ising anyons and braid them to realize their statistics. Building on our technique, we study the prospect of employing the anyons for quantum computation and utilize braiding to create an entangled state of anyons encoding three logical qubits”) [from claim 11] a confinement apparatus configured to confine a plurality of physical qubits; (pg 1 “While the physical layout of qubits is typically used to determine the structure of the stabilizers, the qubits can be considered to be degree-j vertices (DjV; j ∈ {2,3,4}) on more general planar graphs(see Fig.1a)” here the planar graph is a confinement apparatus containing degree-j vertices or qubits) [from claim 11] one or more manipulation sources configured to generate respective manipulation signals for interaction with respective physical qubits of the plurality of physical qubits; (pg 2 “In panel V, single-qubit Z-gates are applied to two qubits near the lower left corner of the grid to create adjacent plaquette violations, which together form a fermion. Through the sequential application of X- and Z-gates” here the application of gates to manipulate the plaquette amounts to generation of manipulation signals interacting with the respective qubits. The gates are applied via a manipulation source. ) controlling operation of a confinement apparatus to cause a plurality of physical qubits to be confined by the confinement apparatus, [from claim 11] and a controller configured to control operation of the confinement apparatus and the one or more manipulation sources, the controller configured to perform: (pg 2 “In the first experiment we demonstrate the creation of anyons and the fundamental fusion rules of σ and ε (Fig.2a). In a 5×5 grid of superconducting qubits, we first use a protocol consisting of four layers of CZ-gates to prepare the surface code ground state…” the grid of superconducting qubits confines the qubits via a confinement apparatus) wherein at least some of the plurality of physical qubits are logically organized onto a lattice and have been prepared to provide a non-Abelian topological order ground state, (pg 1 abstract “Using a superconducting quantum processor, we prepare the ground state of the surface code and manipulate it via unitary operations to form wavefunctions that are described by non-Abelian anyons” pg 1 “Therefore, R2 is a fundamental characteristic of anyon braiding. The topological approach to quantum computation aims to leverage these non-Abelian anyons and their topological nature… In solid-state systems, primary candidates of non-Abelian quasiparticles are low-energy excitations… We recently demonstrated the Abelian statistics of such quasi particles in the surface code. To realize non-Abelian statistics, one needs to go beyond such plaquette violations and instead deform the stabilizer graph” pg 3 “This doubling is exactly what is expected when a pair of Ising anyons is introduced; hence, D3Vs appear as a candidate of non-Abelian anyons, and we will denote them as σ” the stabilizer graph provides a non-abelian ground state when ising anyons are introduced to the lattice as described in the art. The graph is a logical arrangement of qubits.) wherein the lattice comprises a plurality of vertices connected by edges, wherein the lattice is formed of a plurality of sublattices, wherein each sublattice comprises a respective plurality of vertices of the plurality of vertices, the respective plurality of vertices of a sublattice of the plurality of sublattices are connected by edges to form the sublattice; (figure 2 pg 3
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each 5x5 grid is a lattice of vertices and edges, the lattice contains several sublattices which are simply the smaller lattices which are contained within the greater lattice.) causing performance of an anyon creation gate to cause creation of a first pair of non-Abelian anyons on a first sublattice of the plurality of sublattices; ( pg 2 “To shift a D3V from vertex u to v, an edge must be disconnected from v and reconnected to u…. This can be achieved via the gate unitary”, “We then remove a stabilizer edge to create a pair of D3Vs (σ) and separate them through the application of two-qubit gates” pg 3 Figure 2 caption “We first prepare the ground state of the surface code (step I; average stabilizer value: 0.94±0.04). A D3V(σ) pair is then created(II)” as shown in stage II and III of the figure a pair of D3V anyon are created by removing a stabilizer edge, i.e applying a gate unitary of anyon creation gate. Interacting with the quantum lattice is performed via gate operations as described in the art) causing a path traversal gate sequence to be performed to cause at least a first anyon of the first pair of non-Abelian anyons to traverse a first braiding path to form a closed loop on the first sublattice; (pg 3 and figure 2 “Having demonstrated the above fusion rules involving σ, we next braid them with each other to directly show their non-Abelian statistics. We consider two spatially separated σ-pairs, A and B, by removing two stabilizer… Next, we apply two-qubit gates along a horizontal path to separate the σ in pair A(panel III), followed by a similar procedure in the vertical direction on pair B… Moving the plaquette violation along with the σ requires a string of single-qubit gates” the string of gates applied to the pairs separates and moves the pairs along the depicted path, the path is a braiding path because the anyons are non-abelian, thus forming a braiding path as described. The closed loop path is shown by the braiding worldlines in the figure 2) and determining a first fusion channel of fusing the first pair of non-Abelian anyons. (Figure 2 pg 2 caption “The pathV→VIII demonstrates the fusion rule, σ×ε=σ. The different fermion parities at the end of the paths VIII→XI and IV→I show the other fusion rule, σ×σ=1+ε” the determined fusion rules and their accompany coefficients defines the subspace basis of the fusion channel)
Claim 3/13
Google teaches claim 1/11
Google teaches, wherein the path traversal gate sequence comprises a plurality of Pauli-X gates performed on vertices of the first sublattice along the braiding path and a plurality of controlled Z-gates each performed on a respective pair of physical qubits that includes a second vertex qubit and a third vertex qubit, (pg 1 “An instance where sp = −1 on a plaquette is called a plaquette violation. These can be thought of as quasi-particles, which are created and moved through single-qubit Pauli operators (Fig.1a).” pg 2 “In panel V, single-qubit Z-gates are applied to two qubits near the lower left corner of the grid to create adjacent plaquette violations, which together form a fermion. Through the sequential application of X- and Z-gates” further, pg 4 “The diagonal σ move in step IV requires two SWAP-gates (3CZ-gates each) and a total of 10 CZ-gates.” the pair of qubits including a second and third vertex in a pair are operated on via a sequence of x and z gates which define the traversal path. As shown in Figure 3, The diagonal movements along the braiding path of anyon pairs, σ, involve a plurality of CZ gates as well.) wherein the second vertex qubit is a physical qubit of the plurality of physical qubits that is assigned to a vertex of the second sublattice and the third vertex qubit is a physical qubit of the plurality of physical qubits that is assigned to a vertex of the third sublattice. (
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figure 3, as shown a plurality of pairs including first, second, third, and forth anyon qubits depicted with triangles are disposed on sublattice regions on the graph.)
Claim 4/14
Google teaches claim 3/13
Google teaches, wherein the plurality of controlled Z-gates comprises controlled Z-gates performed on each third vertex qubit along the first braiding path with each preceding second vertex qubit along the first braiding path.(Figure 3 caption pg 4 “The diagonal σ move in step IV requires two SWAP-gates (3CZ-gates each) and a total of 10 CZ-gates. The three-qubit unitary in step VIII requires 4 SWAP-gates and a total of 15 CZ-gates. In the full circuit, a total of 40 layers of CZ-gates are applied… The yellow triangles represent the locations of the σ; the brown and green lines represent the paths of σ from pair A and B” the CZ gates, i.e controlled z gates are performed on the third vertex qubit and second qubit along the braiding path.)
Claim 5/15
Google teaches claim 1/11
Google teaches, causing generation of a second pair of non-Abelian anyons on a second lattice of the plurality of sublattices, wherein performance of the path traversal gate sequence further causes at least a first anyon of the second pair of non-Abelian anyons to traverse a second braiding path to form a closed loop on the second sublattice so as to form a second fusion channel. (Figure 3 caption pg 4
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,”Experimental demonstration of braiding, …Two σ-pairs, A and B, are created from the vacuum, and one of the σ in pair A is brought to the right side of the grid. Next, a σ from pair B is moved to the top, thus crossing the path of pair A, before bringing σ-pairs A and B back together to complete the braid… a total of 15 CZ-gates” as shown in the left side of the figure the braid path over time forms a complete loop which defines the fusion channel, the generation of two pairs from a vacuum and subsequently moving them via gate sequences corresponds to the claimed performance of the path traversal gate)
Claim 6/16
Google teaches claim 5/15
Google teaches, wherein the first fusion channel is one of a plurality of possible fusion channels for the first pair of non-Abelian anyons and any crossings of the first braiding path and the second braiding path affects which fusion channel of the plurality of possible fusion channels is formed as the first fusion channel. (Figure 3 pg 4 caption
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“Wordline schematic of the braiding process… As a control experiment, we perform the same braid…” here the resulting braids which define the crossing of the first and second braiding paths affect the possible configurations of the channel. The resulting worldlines define the first fusion channel of a set of possible fusion channels.)
Claim 7/17
Google teaches claim 1/11
Google teaches, wherein determining the first fusion channel comprises determining one or more expectation values for one or more operators defined on the lattice. (pg 3 caption Figure 2 “Expectation values of stabilizers at each step of the unitary operation after readout correction (see Fig. S3 for details and individual stabilizer values).” For each gate operation and subsequent movement the color gradient on the lattice indicates the expectation values defined on the lattice.)
Claim 8/18
Google teaches claim 1/11
Google teaches, determining a creation location first vertex qubit and the first braiding path; (Figure 3 pg 4 caption “Two σ-pairs, A and B, are created from the vacuum” the location of each qubit in the pair is depicted in the figure) and generating a set of machine level executable instructions for causing performance of the anyon creation gate and the path traversal gate sequence. (pg 10 Circuit Details
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“In our experiment, the two-qubit unitaries U±(ˆτ1ˆτ2) are converted to single-qubit rotations and CZ-gates, as shown in Fig. S4a.” the depicted quantum circuits which define the gate operations refine the creation gates and path traversal sequence. The circuits are graphical descriptions of machine level executable instructions.)
Claim Rejections - 35 U.S.C. § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. §§ 102 and 103 (or as subject to pre-AIA 35 U.S.C. §§ 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2/12 are rejected under 35 U.S.C. § 103 as being unpatentable over Google further in view of Satzinger et al. “Realizing topologically ordered states on a quantum processor”
Claim 2/12
Google teaches claim 1/11
Google teaches, wherein the anyon creation gate… causing generation of the first pair of non-Abelian anyons on the first sublattice comprises performing an…gate on a creation location first vertex qubit of the first sublattice… the creation location first vertex qubit being a physical qubit of the plurality of physical qubits assigned to a vertex of the first sublattice that links a creation location of the first anyon of the first pair of non-Abelian anyons and a creation location of a second anyon of the first pair of non-Abelian anyons. ( pg 2 “To shift a D3V from vertex u to v, an edge must be disconnected from v and reconnected to u…. This can be achieved via the gate unitary”, “We then remove a stabilizer edge to create a pair of D3Vs (σ) and separate them through the application of two-qubit gates” pg 3 Figure 2 caption “We first prepare the ground state of the surface code (step I; average stabilizer value: 0.94±0.04). A D3V(σ) pair is then created(II)” as shown in stage II and III of the figure a pair of D3V anyon are created by removing a stabilizer edge via a gate unitary. Interacting with the quantum lattice is performed via gate operations as described in the art, to dispose the two anyonic qubits on locations of the lattice which are linked by the braid established by the unitary operations.)
Google does not explicitly teach, the anyon creation gate is an X-gate… performing an X-gate on a creation location
Satzinger however when addressing ground state initialization of anyonic qubits teaches, the anyon creation gate is an X-gate… performing an X-gate on a creation location (pg 2 Preparation of ground state “We realized the toric code ground state (Fig. 1A)by implementing a shallow quantum circuit on a Sycamore quantum processor…The toric code Hamiltonian is defined in terms of qubits living on the edges of a square lattice…The “plaquette” operators
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are pro-ducts of Pauli X operators on each plaquette (Fig. 1A, square shape, purple)” Fig. 2. Topological entanglement entropy, as shown in the figure the x gate plaquette operations are performed at the qubit creation location.)
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the qubit ground state preparation described by Google to utilize a product of pauli x operators to establish a ground state on a lattice of qubits as described by Satzinger. One would have been motivated to make such a combination because both references describe the construction of a lattice of ground state qubits. Further, Satzinger notes “Our shallow quantum circuits for realizing toric code eigenstates and simulating braiding statistics can be extended to other topologically ordered states, including string-nets with non-Abelian anyons (40, 41). The quasi-static protocol that uses controlled Pauli strings to simulate braiding can be generalized to dynamical adiabatic braiding” (pg 5 Satzinger)
Claim(s) 9/19 are rejected under 35 U.S.C. § 103 as being unpatentable over Google further in view of Liu et al. “Methods for simulating string-net states and anyons on a digital quantum computer”
Claim 9/19
Google teaches claim 1/11
Google does not explicitly teach, wherein a gate used to create the first pair of non-Abelian anyons and each gate of the path traversal gate sequence performed on the first sublattice is controlled by one or more ancilla qubits of the plurality of physical qubits.
Liu however when addressing the performance of non-abelian anionic braiding gates teaches, wherein a gate used to create the first pair of non-Abelian anyons and each gate of the path traversal gate sequence performed on the first sublattice is controlled by one or more ancilla qubits of the plurality of physical qubits. (pg 6 Caption Figure 5 “A simple circuit for measuring the expectation ψ| ˆA|ψ, where ˆA is a unitary operator acting on |ψ and the ancilla qubit is initially prepared in |0 . At the end of the circuit, the ancillary qubit is measured” pg 9 “When simulating the non-abelian strings, the additional ancillary qudits should always be placed at the endpoints of the current string operators” ancillary qudits are used to control the qudits or qubits when simulating, initializing, and measuring, non-abelian anyons.)
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the topological gate sequence described by Google to comprise quantum gates controlled or mediated by ancillary bits as described by Lie. One would have been motivated to make such a combination because describe the construction of quantum gate circuits for simulation of anionic braiding paths in the non-abelian state. Further, Google describes measuring the expectation values within a lattice while Liu clarifies that such a measurement is performed with an ancilla qubit “the expectation value can be efficiently measured by a simple Hadamard test quantum circuit with one ancilla qubit” (Liu pg 6), further “When simulating the non-abelian strings, the additional ancillary qudits should always be placed at the endpoints of the current string operators” (Liu pg 9)
Claim(s) 10/20 are rejected under 35 U.S.C. § 103 as being unpatentable over Google further in view of Hutter et al. “Parafermions in a Kagome Lattice of Qubits for Topological Quantum Computation”
Claim 10/20
Google does not explicitly teach, wherein the lattice is a Kagome lattice having periodic boundary conditions.
Hutter however when addressing confinement of non-abelian parafermions in a lattice teaches,
wherein the lattice is a Kagome lattice, (pg 2 Section 3 “We consider a two-dimensional Kagome (trihexagonal) lattice as in Fig. 1. Each vertex of the lattice hosts one four-dimensional qudit (one pair of Z4 parafermions) or, in other words, two qubits”)
having periodic boundary conditions. (pg 2 Introduction “we discuss how Z4 parafermion modes appear at the ends of defect strings in our model” pg 10 Section C “For a code of linear size L in both dimensions, with periodic boundary conditions”, “The introduction of the defects essentially corresponds to a change in the boundary conditions.” As described the presence of defect lines results in boundary conditions which as shown are periodic.)
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the non-abelian surface codes described by Google to utilize a Kagome lattice of parafermions as described by Hutter. One would have been motivated to make such a combination because both references describe methods for topological manipulation of non-abelian anyons to achieve fault tolerant quantum computing. As noted by Hutter, the creation and transport of parafermion modes, i.e non-abelian anyons, by the use of a Kagome lattice “In order to use the parafermion modes as non-Abelian anyons, some must be allowed to become unpaired. The creation and transport of unpaired parafermion modes can be done by adapting the method of Ref [38] to the Kagome lattice” (Hutter pg 4)
Conclusion
Prior art not relied upon:
Freedman et al US Document ID US 20060091375 A1, describes a system for deposing and braiding non-abelian anyons on a Kagome lattice. The reference does not describe the anyon traversal according to gate operations.
Rowell et al. “MATHEMATICS OF TOPOLOGICAL QUANTUM COMPUTING” describes the mathematics involved in topological computing
Lahtinen et al “A short introduction to topological quantum computation” describes the anyon model for error free subspaces noting the fusion rules and coefficients define the fusion channels or possible topological charges. Further describes that for ising anyons the natural gate sequence includes x-, z-, and controlled phase gates.
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/J.R.G./
Examiner, Art Unit 2122
/KAKALI CHAKI/Supervisory Patent Examiner, Art Unit 2122
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