DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Stoopman et al. (“Co-Design of a CMOS Rectifier and Small Loop Antenna for Highly Sensitive RF Energy Harvesters”; reference of record; “Stoopman”).
Note: The Applicant distinguishes between the terms “coupled” and “directly coupled”. For example, see “coupled” in claim 1 and “directly coupled” in claim 3. For examination purposes, the term “coupled” will be interpreted more broadly (i.e., not necessarily “directly” coupled) than the term “directly coupled”.
Regarding claim 1, Stoopman teaches an apparatus for signal rectification (figure 7), comprising:
a multi-stage rectifier (Capacitor Bank and Rectifier comprising three rectifier circuits in figure 7) comprising a first rectifier stage (leftmost rectifier), a second rectifier stage (middle rectifier), and a third rectifier stage (rightmost rectifier) coupled to an output (at Cstore) of the multi-stage rectifier (Capacitor Bank and Rectifier), wherein the second rectifier stage (middle rectifier) is coupled between the first rectifier stage (leftmost rectifier) and the third rectifier stage (rightmost rectifier); and
a sample and tune circuit (Control Loop) comprising a sampling input (Sample & Comparator) coupled to an output of the second rectifier stage (middle rectifier) and an output (D1-Dn) coupled to at least one tuning input (of Capacitor Bank) of the multi-stage rectifier (Capacitor Bank and Rectifier).
As for claim 2, Stoopman teaches wherein the multi-stage rectifier further comprises at least one fourth rectifier stage coupled between the first rectifier stage and the second rectifier stage (The multi-stage rectifier of Stoopman comprises 5 stages. See last sentence under the heading “B. Multi-stage Rectifier”.).
As for claim 3, Stoopman teaches wherein the output of the second rectifier stage (middle rectifier) is directly coupled to a reference node of the third rectifier stage (rightmost rectifier).
Regarding claim 4, Stoopman teaches wherein each of the first rectifier stage, the second rectifier stage, and the third rectifier stage comprises a complementary metal-oxide-semiconductor (CMOS) rectifier (See CMOS structure in figure 7).
As for claim 5, Stoopman teaches wherein the multi-stage rectifier further comprises one or more capacitive elements (1C-nC) coupled between differential input nodes of the multi-stage rectifier, wherein the output of the sample and tune circuit (Control Loop) is coupled to one or more control inputs of the one or more capacitive elements (1C-nC).
Regarding claim 6, Stoopman teaches wherein the multi-stage rectifier further comprises an output capacitive element (Cstore) coupled to the output of the third rectifier stage (rightmost rectifier).
Regarding claim 7, Stoopman teaches wherein each of the first rectifier stage (leftmost rectifier), the second rectifier stage (middle rectifier), and the third rectifier stage (rightmost rectifier) is coupled between differential input nodes (at capacitors Cc) of the multi-stage rectifier (figure 7).
As for claim 8, Stoopman teaches wherein each of the first rectifier stage, the second rectifier stage, and the third rectifier stage comprises:
a first transistor; a second transistor having a drain coupled to a drain of the first transistor; a third transistor; a fourth transistor having a drain coupled to a drain of the third transistor and to gates of the first transistor and the second transistor, wherein gates of the third transistor and the fourth transistor are coupled to the drains of the first transistor and the second transistor (See four transistors in each of the rectifier stages in figure 7 of Stoopman.);
a first capacitive element (Cc) coupled between a first input of the multi-stage rectifier and the drains of the first transistor and the second transistor; and
a second capacitive element (Cc) coupled between a second input of the multi-stage rectifier and the drains of the third transistor and the fourth transistor.
As for claim 9, Stoopman teaches wherein the multi-stage rectifier is configured to rectify a signal received via an antenna (Antenna in figure 7) to generate a rectified output voltage (across Cstore) for powering one or more circuits (figure 1).
Regarding claims 10-18, the methods as recited in the claims are inherently present in the structure discussed above in the rejection of claims 1-9.
Regarding claim 19, Stoopman teaches a wireless device (figure 7), comprising:
an antenna (Antenna);
a multi-stage rectifier (Capacitor Bank and Rectifier comprising three rectifier circuits in figure 7) comprising a first rectifier stage (leftmost rectifier) coupled to the antenna (Antenna), a second rectifier stage (middle rectifier) coupled to the antenna (Antenna), and a third rectifier stage (rightmost rectifier) coupled to the antenna (Antenna) and to an output (at Cstore) of the multi-stage rectifier (Capacitor Bank and Rectifier), wherein the second rectifier stage (middle rectifier) is coupled between the first rectifier stage (leftmost rectifier) and the third rectifier stage (rightmost rectifier); and
a sample and tune circuit (Control Loop) comprising a sampling input (Sample & Comparator) coupled to an output of the second rectifier stage (middle rectifier) and an output (D1-Dn) coupled to at least one tuning input (of Capacitor Bank) of the multi-stage rectifier (Capacitor Bank and Rectifier).
As for claim 20, Stoopman teaches wherein the multi-stage rectifier further comprises at least one fourth rectifier stage coupled between the first rectifier stage and the second rectifier stage (The multi-stage rectifier of Stoopman comprises 5 stages. See last sentence under the heading “B. Multi-stage Rectifier”.).
Conclusion
The prior art references made of record and not relied upon teach cascaded multi-stage rectifiers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEVI GANNON whose telephone number is (571)272-7971. The examiner can normally be reached 7:00AM-4:30PM.
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/LEVI GANNON/Primary Examiner, Art Unit 2849 February 24, 2026
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