Prosecution Insights
Last updated: April 19, 2026
Application No. 18/636,158

HIGH-CURRENT, BIDIRECTIONAL PROTECTION CIRCUITS AND METHODS

Non-Final OA §102
Filed
Apr 15, 2024
Examiner
BAUER, SCOTT ALLEN
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Maxim Integrated Products Inc.
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
2y 7m
To Grant
96%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allow Rate
804 granted / 977 resolved
+14.3% vs TC avg
Moderate +13% lift
Without
With
+13.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
22 currently pending
Career history
999
Total Applications
across all art units

Statute-Specific Performance

§101
0.9%
-39.1% vs TC avg
§103
57.2%
+17.2% vs TC avg
§102
32.3%
-7.7% vs TC avg
§112
5.8%
-34.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 977 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 2, 8, 9 & 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Smith (US 5,534,788). With regard to claims 1 & 2, Smith, in Figures 1 & 6, discloses an overcurrent protection method (column 3, lines 5-12) comprising: using a sensing circuit (134) that, in response to an overcurrent condition being present at a current node, detects a current; using a current-mode comparator (column 7, lines 6-26 teaches that sense circuit may comprise a current mode comparator) to convert the current to a control signal (654); and using a control circuit (136) that, in response receiving the control signal, turns off a set of switching devices that are coupled to a to-be-protected current node to create a high-impedance electrical path between the current node and the to-be-protected current node (column 5, lines 5-23) (re claim 1), wherein the overcurrent condition is a current level outside of an operating current range of the to-be-protected current node (column 1, lines 12-16 teaches that the overcurrent condition can damage or compromise the safety of the device which would necessarily have an overcurrent limit that reacts within the operating range to prevent damage) (re claim 2). With regard to claims 8, 9 & 14, Smith, in Figure 1, discloses a dual-polarity high-current protection circuit (column 5, lines 5-23 teaches that over current protection is provided in both directions thus providing dual polarity protection) comprising: a protection circuit coupled to a to-be-protected current node and an output current node (node coupled to sense resistor 122); a current sensing circuit (134) that, in response to sensing an overcurrent condition present at the output current node , generates an output signal indicative of the overcurrent condition; and a control circuit (136) coupled to the current sensing circuit, the control circuit, in response to receiving the output signal, causes the protection circuit to assume a high impedance to isolate the to-be-protected current node from the overcurrent condition (column 5, lines 5-23) (re claim 8), wherein the overcurrent condition is a current level outside of an operating current range of the to-be-protected current node (column 1, lines 12-16 teaches that the overcurrent condition can damage or compromise the safety of the device which would necessarily have an overcurrent limit that reacts within the operating range to prevent damage) (re claim 9), wherein the current sensing circuit comprises a switch (604 of Fig. 6) coupled to the output current node, the switch generating the output signal in form of a current (re claim 14). Allowable Subject Matter Claims 3-7, 10-13 & 15-19 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 3 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record does not teach or fairly suggest an overcurrent protection method comprising all the features as recited in the claims and in combination with the sensing circuit being a current sensing circuit and the control signal is a state signal that controls a set of bias currents. Claims 4-7 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because they depend on claim 3 which would also be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 10 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record does not teach or fairly suggest an overcurrent protection method comprising all the features as recited in the claims and in combination with the protection circuit comprises two sets of switches, each set comprising opposing body diodes. Claims 11 & 19 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because they depend on claim 10 which would also be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 12 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record does not teach or fairly suggest an overcurrent protection method comprising all the features as recited in the claims and in combination with the operating current range being controlled by an output stage state of an operational amplifier that is coupled to the to-be-protected current node. Claim 13 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because it depends on claim 12 which would also be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 15 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record does not teach or fairly suggest a circuit comprising all the features as recited in the claims and in combination with an additional current sensing circuit coupled to the current sensing circuit, the additional current sensing circuit, in response to receiving the current, outputs a state signal that controls a set of bias currents. Claims 16-18 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because they depend on claim 15 which would also be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 20 is allowable. Claim 20 is allowable because the prior art of record does not teach or fairly suggest a switch network for bidirectional high-current protection of a current node comprising all the features as recited in the claims and in combination with generating a low-level signal to control bias currents to cause the two sets of switches to turn on, such that a current flowing between the to-be-protected current node and the output current node is determined by on-resistances of the two sets of switches and a load voltage present at the output current node; and in response to the current at the output current node falling outside the current range, a drain current exceeding a current value causing a corresponding comparator in the set of comparators generating a high-level signal that causes the bias currents and, thus, the two sets of switches to turn off, thereby, creating a high-impedance path between the to-be-protected current node and the output current node, the current at the to-be-protected current node being controlled by an output stage state of an operational amplifier to be within the current range, the current at the output current node assuming values between a lower current threshold and a higher current threshold. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hogari (US 2002/0017896), Hasegawa (US 5,789,900), Suzuki (US 9,172,261) and Kim (US 10,389,148) all teach circuits that provide overcurrent protection using dual polarity switches. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCOTT BAUER whose telephone number is (571)272-5986. The examiner can normally be reached M-F 12pm - 8pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, THIENVU TRAN can be reached at (571)270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Scott Bauer/ Primary Examiner, Art Unit 2838
Read full office action

Prosecution Timeline

Apr 15, 2024
Application Filed
Dec 13, 2025
Non-Final Rejection — §102
Mar 27, 2026
Interview Requested
Apr 06, 2026
Response Filed
Apr 06, 2026
Applicant Interview (Telephonic)
Apr 07, 2026
Examiner Interview Summary

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
96%
With Interview (+13.3%)
2y 7m
Median Time to Grant
Low
PTA Risk
Based on 977 resolved cases by this examiner. Grant probability derived from career allow rate.

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