Prosecution Insights
Last updated: October 25, 2026
Application No. 18/636,343

HIGH-POWER COMPONENT BASED ON III NITRIDE COMPOUND SEMICONDUCTORS, INTERMEDIATE PRODUCT AND PROCESS FOR PRODUCTION OF A HIGH-POWER COMPONENT

Non-Final OA §103
Filed
Apr 16, 2024
Priority
Apr 17, 2023 — DE 102023109595.1
Examiner
HOSSAIN, MOAZZAM
Art Unit
Tech Center
Assignee
Frauhofer-Gesellschaft Zur Förderung Der Angewandten Forschung E V
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
755 granted / 857 resolved
+28.1% vs TC avg
Moderate +11% lift
Without
With
+11.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
39 currently pending
Career history
890
Total Applications
across all art units

Statute-Specific Performance

§101
2.6%
-37.4% vs TC avg
§103
49.7%
+9.7% vs TC avg
§102
26.2%
-13.8% vs TC avg
§112
19.1%
-20.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 857 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election, without traverse, of Group I: claims 1-16 is acknowledged. This office action considers claims 1-22 are thus pending for prosecution, of which, non-elected claims 17-22 are withdrawn, and elected claims 1-16 are examined on their merits. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as SBD; Fig 1; [0064]) or C 1, L 13-14)= (element SBD; Figure No. 1; Paragraph No. [0064]) or Column No 1, Line Nos. 13-14. For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The primary reference, in this case Doring, citation may not be preceded by the inventor tag, wherein the other reference citation, for example Udrea, will carry inventor tag. These conventions are used throughout this document. Claims 1-16 are rejected under 35 U.S.C. 103 as being unpatentable over to DORING PHILIPP ET AL et al. ("Technology of GaN-Based Large Area CAVETs With Co-Integrated HEMTs", IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE, USA,Vol. 68, No. 11) hereinafter referenced as Doring, in view of Udrea; Florin; Florin et al. (US 20200357909 A1) hereinafter referenced as Udrea. Regarding Claim 1. Doring teaches a high-power component (GaN power ICs [abstract]; Fig 1(f); Section -I) based on III nitride compound semiconductors (GaN), comprising: (see the entire document, Fig 1(f), along with other figures referenced subject matter for details, Abstract, sections 1-III, specifically, as cited below): PNG media_image1.png 189 250 media_image1.png Greyscale Doring Figure 1(f) at least one first, vertical transistor component (Fig 1(f):: from Drain to AlGaN barrier/uid-GaN channel) and at least one second component (Fig. 1(e)) having a lateral heterostructure (AlGaN barrier/uid-GaN channel); the lateral heterostructure of the second component is formed monolithically by selective epitaxial overgrowth on a subregion (figs 1(a) to1(f), Section II: "Alignment markers were etched and protected by SiOx prior to regrowth to orientate the surface processing with respect to the aperture region". Since, therefore, no epitaxy takes place on the covered alignment marks, the lateral heterostructure is formed only on a portion of the surface, though the heterostructure appears to be formed over the entire area) of a surface of the first, vertical component ; and the second component comprises at least one transistor (HEMT see labels to Fig. 1(e); Section IV: Lateral HEMTs were co-integrated on chip, with the 2DEG in the vicinity of the Mg-implanted CBL. This combination of a large area CAVET and an on-chip integrated HEMT demonstrates a pathway to allow monolithically integrated GaN power converters with power switches based on the CAVET technology). Doring is silent on at least one further active and/or passive component. However, in the analogous art, Udrea discloses a power semiconductor devices. Particularly, but not exclusively, the disclosure relates to the use of a hetero-structure AlGaN/GaN high electron mobility transistor for an integrated start-up circuit of a switch mode power supply ([0001]) wherein (Figs 2/3; [0009]) a controller is powered when the de-coupling capacitor, C, is charged and is essential for the SMPS to operate as desired. This is shown in FIGS. 2 and 3. A DC/DC conversion to power the controller is used as the controller operates at a significantly reduced DC bias voltage compared to the rectified input DC rail voltage (V.sub.in). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Capacitor C of Udrea into the second component transistor (HEMT) of Doring, and there after the combination of (Doring and Udrea) comprises (active and/or) passive component (capacitor C) , since this inclusion, at least, this facilitates a controller operates at a significantly reduced DC bias voltage compared to the rectified input DC rail voltage (V.sub.in).) (Udrea [0009]). Regarding Claim 2. The combination of (Doring and Udrea) as applied to the high-power component as claimed in claim 1, Doring further teaches, wherein both the first transistor component (AlGaN barrier/uid-GaN channel) and the second component (GaN HEMT) are formed based on III nitride compound semiconductors. Regarding Claim 3. The combination of (Doring and Udrea) as applied to the high-power component as claimed in claim 1, Doring further teaches, (the component) further comprising a two-dimensional electron gas (Section IV: Lateral HEMTs were co-integrated onchip, with the 2DEG in the vicinity of the Mg-implanted CBL) formed within the lateral heterostructure of the second component. Regarding Claim 4. The combination of (Doring and Udrea) as applied to the high-power component as claimed in claim 1, Doring further teaches, wherein the lateral heterostructure is based on AlGaN (section I: AlGaN/GaN-HEMT.), AlN, ScAlGaN, InAlGaN and/or YAlGaN. Regarding Claim 5. The combination of (Doring and Udrea) as applied to the high-power component as claimed in claim 1, Doring further teaches, wherein, for formation of the subregion on the surface of the first transistor component , a protective layer (section II: a protective layer of SiOx. Moreover, silicon nitride is a known alternative material for masking in selective epitaxy) is formed outside of the subregion. Regarding Claim 6. The combination of (Doring and Udrea) as applied to the high-power component as claimed in claim 5, Doring further teaches, wherein the protective layer (section II: a protective layer of SiOx) is formed from a dielectric. Regarding Claim 7. The combination of (Doring and Udrea) as applied to the high-power component as claimed in claim 1, Doring further teaches, wherein the high-power component has a blocking strength of greater than 200 V (Fig 5: Section III: Breakdownis measured in the range of VBR = 206 − 222 V (at room temperature) independent of the aperture length and also for the transistor without an aperture). Regarding Claim 8. The combination of (Doring and Udrea) as applied to the high-power component as claimed in claim 1, Doring further teaches, wherein the first component is devoid of a polarization-induced electron channel (because CAVET combines the advantage of the vertical depletion and drift-region with the proven gate–source module of the lateral HEMT; Section I). Regarding Claim 9. The combination of (Doring and Udrea) as applied to the high-power component as claimed in claim 1, Doring further teaches, wherein the first component comprises (Figs 1(b) to 1(f))a plurality of layers ({Drain, p-GaN Substrate, Uid GaN Drft layer}'), with an uppermost layer, which forms the surface, of the first component being n-type or p-type doped. Regarding Claim 10. The combination of (Doring and Udrea) as applied to the high-power component as claimed in claim 1, Doring further teaches, further comprising a diffusion barrier (Section I: CAVETs were presented [17] with Mg-implanted CBL’s fabricated by molecular beam epitaxy (MBE) regrowth to prevent Mg-diffusion from the CBL) formed on the subregion between the first component and the lateral heterostructure (Lateral HEMT) of the second component . Regarding Claim 11. The combination of (Doring and Udrea) as applied to the high-power component as claimed in claim 1, Doring further teaches, wherein a source contact (Obvious from Section III: connecting the CBL to the source contact of the CAVET will be beneficial to avoid any impact of the drain potential on the static and dynamic behavior of the lateral HEMTs.) of the transistor of the second component (10) is formed extending into the first component (2). Regarding Claim 12. The combination of (Doring and Udrea) as applied to the high-power component as claimed in claim 1, Doring further teaches, wherein the first component comprises a MOSFET, trench MOSFET, DMOS, JFET, FinFET, OGFET or SIT (Section IV or abstract : Vertical FET/ CAVET). Regarding Claim 13. The combination of (Doring and Udrea) as applied to the high-power component as claimed in claim 1, Doring further teaches, wherein the second component comprises at least one of an HEMT (Fig 1(e) lateral GaN HEMT)(, a MOSHEMT or MISHEMT, a p gate, or a recess gate). Regarding Claim 14. The combination of (Doring and Udrea) as applied to the high-power component as claimed in claim 1, Doring further teaches, wherein the second component (lateral HEMT ) is used as a cascade circuit (Fig (1f)) for the first component (CAVET). Regarding Claim 15. The combination of (Doring and Udrea) as applied to the high-power component as claimed in claim 1, Doring further teaches, wherein the second component (lateral HEMT) is used as at least one of an integrated gate driver, (section I: This combined Power IC opens the possibility for monolithic integration of gate drivers) current sensor, or a temperature sensor. Regarding Claim 16. Doring teaches an intermediate product (fig 1(e)) for the production of a high-power component (GaN power ICs [abstract]; Fig 1(f); Section -I), the intermediate product comprises: a first, vertical transistor component (Fig 1(f): from Drain to AlGaN barrier/uid-GaN channel); a lateral heterostructure formed monolithically by epitaxy on a subregion of a surface of the first, vertical component (figs 1(a) to1(f), Section II: "Alignment markers were etched and protected by SiOx prior to regrowth to orientate the surface processing with respect to the aperture region". Since, therefore, no epitaxy takes place on the covered alignment marks, the lateral heterostructure is formed only on a portion of the surface, though the heterostructure appears to be formed over the entire area) ; and, outside of the subregion of the surface of the first, vertical component , a protective layer ((section II: a protective layer of SiOx. Moreover, silicon nitride is a known alternative material for masking in selectiveepitaxy)). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOAZZAM HOSSAIN whose telephone number is (571)270-7960. The examiner can normally be reached M-F: 8:30AM - 6:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOAZZAM HOSSAIN/Primary Examiner, Art Unit 2898 October 2, 2026
Read full office action

Prosecution Timeline

Apr 16, 2024
Application Filed
Oct 06, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12772827
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
2y 3m to grant Granted Oct 20, 2026
Patent 12764976
PHASE CHANGE MATERIAL MICROELECTROMECHANICAL SYSTEMS BASED ANALOG MEMORY AND COMPUTATIONAL DEVICE
3y 2m to grant Granted Oct 13, 2026
Patent 12759866
MEMS MICROPHONE
3y 1m to grant Granted Oct 13, 2026
Patent 12753068
ENGINEERED SUBSTRATES, FREE-STANDING SEMICONDUCTOR MICROSTRUCTURES, AND RELATED SYSTEMS AND METHODS
3y 9m to grant Granted Oct 06, 2026
Patent 12757543
DISPLAY DEVICE
2y 11m to grant Granted Oct 06, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
99%
With Interview (+11.1%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 857 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month