DETAILED ACTION
Claims 1 – 20 are currently pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/1/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 – 3, 5 – 8, 10 – 13, 15 – 18 and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Minnich (US 2025/0117205).
As per claims 1 and 11:
Taking claim 1 as exemplary: Minnich discloses a network device, comprising: packet processing circuitry, to communicate packets over a network (Minnich: Paragraph [0102]); one or more hardware peripherals (Minnich: Paragraph [0103] firmware memory 825 is being considered a hardware peripheral]; a Baseboard Management Controller (BMC), to control the hardware peripherals (Minnich: Paragraph [0103], BMC 805); and a Central Processing Unit (CPU), to perform control-plane operations for communicating the packets by the packet processing circuitry(Minnich: Paragraph [0103], CPU 835a), wherein each of the CPU and the BMC is to modify states of the hardware peripherals, and to synchronize the other of the BMC and the CPU with the modified state of the hardware peripherals (Minnich: Paragraph [0103], both CPU and BMC write changes to firmware on memory 825, and both read updated firmware from memory 825, the updating of the firmware on memory 825 being considered the claimed modified state of the hardware peripheral).
As per claims 2 and 12:
Taking claim 2 as exemplary: Minnich discloses an interface to communicate between the CPU and the BMC, wherein the CPU and the BMC are to synchronize one another with the modified states of the hardware peripherals by communicating over the interface (Minnich: Paragraph [0102] and figure 8, connection 820).
As per claims 3 and 13:
Taking claim 3 as exemplary: Minnich discloses the CPU is to communicate with a first management system, and wherein the BMC is to communicate with a second management system, different from the first management system (Minnich: Paragraph [0102] and figure 8, CPU communicates with 830, BMC communicates with 815).
As per claims 5 and 15:
Taking claim 5 as exemplary: Minnich discloses each of the CPU and the BMC is to read a status of the hardware peripherals, and to synchronize the other of the BMC and the CPU with the read status (Minnich: Paragraph [0103], both BMC and CPU read modifications to the firmware written on memory 825, reading the status of the modified firmware).
As per claims 6 and 16:
Taking claim 6 as exemplary: Minnich discloses a given hardware peripheral is to send a status indication to both the CPU and the BMC (Minnich: Paragraph [0103], memory 825 accessible by both CPU and BMC).
As per claims 7 and 17:
Taking claim 7 as exemplary: Minnich discloses a given hardware peripheral is to send a status indication to the CPU, and wherein the CPU is to relay the status indication to the BMC (Minnich: Paragraph [0103], CPU reads from memory 825, modifies memory 825, BMC reads modification from memory 825).
As per claims 8 and 18:
Taking claim 8 as exemplary: Minnich discloses the CPU is to modify a state of a hardware peripheral by communicating with the hardware peripheral directly, not via the BMC (Minnich: Paragraph [0103]).
As per claims 10 and 20:
Taking claim 10 as exemplary: Minnich discloses the hardware peripherals comprise at least one peripheral type selected from (i) a cooling device, (ii) an optical indicator, (iii) a power supply, (iv) a voltage regulator, (v) a cooling-liquid leakage sensor and (vi) a security device (Minnich: Paragraph [0103], firmware memory 825, and paragraph [0027], malware tries to attack persistent firmware, making memory 825 storing the firmware a security device).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4, 9, 14 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Minnich.
As per claims 4 and 14:
Taking claim 4 as exemplary: Minnich does not specifically disclose that the CPU is to record the modified states of the hardware peripherals in a first data structure, and wherein the BMC is to record the modified states of the hardware peripherals in a second data structure, separate from the first data structure. However, it would have been obvious to one of ordinary skill in the art at the time of filing that having both the CPU and the BMC keep copies of the states of the hardware peripherals in separate data structures would provide a level of redundancy in the event that one of the data structures fail at some point in time.
As per claims 9 and 19:
Taking claim 9 as exemplary: Minnich does not specifically disclose that the BMC is to modify a state of a hardware peripheral indirectly, by instructing the CPU to modify the state. However, it would have been obvious to one of ordinary skill in the art at the time of filing that if there should be a situation in which the BMC is unable to modify the state of the peripheral directly, it would be useful for the BMC to indirectly modify the state of the peripheral by way of the CPU if the CPU does have access to the peripheral.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Markow et al (US 2025/0286833) teaches a management fabric to peripheral devices for control by processors and a BMC. Remis et al (US 2018/0314318) teaches use of a baseboard management controller couple for communication with the CPU and power supply, controlling voltage regulators and operating state updates from the CPU. Liu (US 2025/0173158) teaches identifying peripherals states for both the central processing unit and a baseboard management controller.
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/ZACHARY K HUSON/Primary Examiner, Art Unit 2181