DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 08/03/2026 have been fully considered but they are not persuasive.
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Fig. 3 of Kim discloses a plurality of thermal interface material layers 436 (tin-silver solders - Tin–silver (Sn–Ag) solders, such as Sn96/Ag4 and common SAC (tin–silver–copper) alloys, have moderate to good thermal conductivity for solder materials) between the semiconductor chip and the plurality of capacitors, each thermal interface material layer (indirectly) contacting the semiconductor chip and at least one of the plurality of capacitors.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-11, 13-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim 20220336336
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Regarding claim 1, figs. 1 and 3 of Kim discloses a semiconductor package comprising:
a lower redistribution structure (as labeled by examine above);
a semiconductor chip 300 on a top surface of the lower redistribution structure;
a plurality of conductive posts 226 (see those between first opening OP1 and second opening OP2) on a top surface of the lower redistribution structure and spaced apart from the semiconductor chip in a direction parallel to the top surface of the lower redistribution structure;
a plurality of capacitors 430 (par [0048]) on the top surface of the lower redistribution structure, the plurality of capacitors being between the semiconductor chip and the plurality of conductive posts; and
a plurality of thermal interface material layers 436 (tin-silver solders - Tin–silver (Sn–Ag) solders, such as Sn96/Ag4 and common SAC (tin–silver–copper) alloys, have moderate to good thermal conductivity for solder materials) between the semiconductor chip and the plurality of capacitors, each thermal interface material layer (indirectly) contacting the semiconductor chip and at least one of the plurality of capacitors.
Regarding claim 2, fig. 1 of Kim discloses further comprising: an upper redistribution structure 600 on the conductive posts; and a plurality of thermal vias 630 (fig. 1 which are inherently thermal via as metal are thermally conductive) in the upper redistribution structure, the plurality of thermal vias being connected to the plurality of capacitors.
Regarding claim 11, Kim disclose a semiconductor package comprising: a lower redistribution structure; a semiconductor chip on a top surface of the lower redistribution structure; a plurality of conductive posts on the top surface of the lower redistribution structure and spaced apart from the semiconductor chip in a direction parallel to the top surface of the lower redistribution structure; a plurality of capacitors on the top surface of the lower redistribution structure, the plurality of capacitors being between the semiconductor chip and the plurality of conductive posts; a plurality of thermal interface material layers between the semiconductor chip and the plurality of capacitors, each thermal interface material layer (indirectly) contacting the semiconductor chip and at least one of the plurality of capacitors (see rejection of claim 1 above); an upper redistribution structure on the conductive posts; and a plurality of thermal vias in the upper redistribution structure and connected to the plurality of capacitors (see rejection of claim 2 above), (fig. 1 of Kim necessary discloses) wherein an area of the semiconductor chip in a plan view is smaller than an area of the lower redistribution structure in the plan view.
Regarding claims 4 and 15, fig. 1 of Kim discloses further comprising a molding layer 500 covering the top surface of the lower redistribution structure, the molding layer surrounding the semiconductor chip, the plurality of conductive posts, the plurality of capacitors, and the molding layer is covering the plurality of thermal interface material layers.
Regarding claims 5 and 16, fig. 1 of Kim discloses further comprising a plurality of chip connection terminals between the lower redistribution structure and the semiconductor chip and between the lower redistribution structure and the plurality of capacitors.
Regarding claim 6, fig. 1 of Kim discloses wherein the plurality of chip connection terminals each include: a lower pillar 130 disposed on the top surface of the lower redistribution structure so as to be electrically connected to the lower redistribution structure; and a conductive cap (interconnect above 130) between the lower pillar and the semiconductor chip or one of the plurality of capacitors to electrically connect the semiconductor chip or the one of the plurality of capacitors to the lower pillar.
Regarding claim 17, fig. 1 of Kim discloses wherein the plurality of chip connection terminals each include: a lower pillar electrically connected to the lower redistribution structure; and a conductive cap between the lower pillar and the semiconductor chip or one of the plurality of capacitors to electrically connect the semiconductor chip or the one of the plurality of capacitors to the lower pillar.
Regarding claim 7, fig. 1 of Kim discloses wherein the plurality of capacitors comprise at least two capacitors spaced apart from each other at equal intervals along a first edge of the semiconductor chip in a plan view in order to symmetry in design.
Regarding claim 9, figs. 1 and 3 of Kim discloses wherein at least one of the plurality of thermal interface material layers is in contact with the semiconductor chip and with at least two capacitors from among the plurality of capacitor structures (indirect contact and all elements are in contact indirectly).
Regarding claim 10, fig. 1 of Kim discloses further comprising a plurality of external connection terminals 140 on a bottom surface of the lower redistribution structure.
Regarding claim 13, figs. 1 and 3 of Kim discloses wherein an uppermost end of each of the plurality of thermal interface material layers is on a same plane as a top surface of the semiconductor chip in a vertical direction (the plane of top surface of 500), and a lowermost end of each of the plurality of thermal interface material layers is on a same plane of the semiconductor chip in the vertical direction (bottom surface plane of layer 200).
Regarding claim 14, figs. 1 and 3 of Kim discloses wherein at least one of the plurality of thermal interface material layers is in contact with at least two of the plurality of capacitors and the semiconductor chip
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim.
Regarding claim 8, it would have been obvious to form wherein a first capacitor of the at least two capacitors is at an end of the first edge of the semiconductor chip in a first horizontal direction and a second capacitor is at an opposite end of the first edge of the semiconductor chip in the first horizontal direction, a length of the first edge of the semiconductor chip in the first horizontal direction is the same as a distance between opposite side surfaces of the first capacitor and the second capacitor in order to have symmetry in design.
Furthermore, it would have been obvious to a package further comprising a third capacitor of the plurality of capacitors is at an end of a second edge of the semiconductor chip in a second horizontal direction and a fourth capacitor is at an opposite end of the second edge of the semiconductor chip in the second horizontal direction, and a length of the second edge of the semiconductor chip in the second horizontal direction is the same as a distance between opposite side surfaces of the third capacitor and the fourth capacitor in order form a many capacitors as needed to per applicant design as duplication of parts is obvious to one of ordinary skill in the art.
Regarding claim 18, it would have been obvious to form a package wherein the plurality of capacitors are spaced apart from each other at equal intervals along a first edge of the semiconductor chip in a plan view, a first capacitor of the plurality of capacitors is at an end of the first edge of the semiconductor chip in a first horizontal direction and a second capacitor is at an opposite end of the first edge of the semiconductor chip in the first horizontal direction, a length of the first edge of the semiconductor chip in a first horizontal direction is the same as a distance between opposite side surfaces of the first capacitor and the second capacitor as needed to per applicant design as duplication of parts is obvious to one of ordinary skill in the art.
Furthermore, it would have been obvious to a package further comprising a third capacitor of the plurality of capacitors is at an end of a second edge of the semiconductor chip in a second horizontal direction and a fourth capacitor is at an opposite end of the second edge of the semiconductor chip in the second horizontal direction, and a length of the second edge of the semiconductor chip in the second horizontal direction is the same as a distance between opposite side surfaces of the third capacitor and the fourth capacitor in order form a many capacitors as needed to per applicant design as duplication of parts is obvious to one of ordinary skill in the art.
Claims 3, 12 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Kim et al. 20200388549 (hereinafter Kim9).
Regarding claims 3 and 12, Kim does not disclose further comprising: a heat dissipation contact on a top surface of the upper redistribution structure; and a heat sink (heat dissipation part) on a top surface of the heat dissipation contact.
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However, fig. 15 of Kim9 disclose a package comprising: a heat dissipation contact 263/253 on a top surface a structure; and a heat sink (heat dissipation part) 285 on a top surface of the heat dissipation contact.
As such it would have been obvious to form a package of Kim further comprising: a heat dissipation contact on a top surface of the upper redistribution structure; and a heat sink (heat dissipation part) on a top surface of the heat dissipation contact such as taught by Kim9 in order to dissipate heat from the package.
Regarding claim 19, Kim and Kim9 disclose a semiconductor package comprising:
a lower redistribution structure;
a semiconductor chip on a top surface of the lower redistribution structure;
a plurality of conductive posts on the top surface of the lower redistribution structure and spaced apart from the semiconductor chip in a first horizontal direction parallel to the top surface of the lower redistribution structure or in a second horizontal direction perpendicular to the first horizontal direction;
a plurality of capacitors on the top surface of the lower redistribution structure, the plurality of capacitors being between the semiconductor chip and the plurality of conductive posts;
a plurality of thermal interface material layers between the semiconductor chip and the plurality of capacitors, each thermal interface material layer contacting the semiconductor chip and at least one of the plurality of capacitors (see rejection claim 1 above);
a plurality of chip connection terminals between the lower redistribution structure and the semiconductor chip and between the lower redistribution structure and the plurality of capacitors (see rejection of claim 5 above);
a molding layer covering the top surface of the lower redistribution structure, the molding layer surrounding the semiconductor chip, the plurality of conductive posts, the plurality of capacitors, the plurality of thermal interface material layers, and the plurality of chip connection terminals (see rejection of claim 1 and fig. 1 of Kim);
an upper redistribution structure on the conductive posts;
a plurality of thermal vias in the upper redistribution structure, the plurality of thermal vias being connected to the plurality of capacitors (see rejection of claim 2 above);
a heat dissipation contact on a top surface of the upper redistribution structure (see rejection of claim 2 above); and a heat dissipation part on a top surface of the heat dissipation contact (see rejection of claim 3 above),
the resulting structure of Kim and Kim9 would have been one wherein heat generated from the semiconductor chip is transferred sequentially (this is necessary the case as heat will transfer in some form of sequence) along the plurality of thermal interface material layers, the plurality of capacitors, the plurality of thermal vias, the heat dissipation contact, and the heat dissipation part.
an area of the semiconductor chip in a plan view is smaller than an area of the lower redistribution structure in the plan view (see fig. 9 and rejection of claim 11),
The resulting structure would have been one wherein the plurality of thermal interface material layers surround at least part of horizontal edges of the semiconductor chip,
an uppermost end of each of the plurality of thermal interface material layers is on a same plane as or above a top surface of the semiconductor chip in a vertical direction, and a lowermost end of each of the plurality of thermal interface material layers is on a same plane as or below a bottom surface of the semiconductor chip in the vertical direction (see rejection of claim 13 above).
Regarding claim 20, par [0060] and fig. 8 of Kim discloses wherein the thermal vias include copper or an alloy of copper (Cu).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/VONGSAVANH SENGDARA/Primary Examiner, Art Unit 2893
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