DETAILED ACTION
1. This Office action is in response to the amendment filed on 03/16/2026.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 112
4. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
5. Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites the limitation "… ,wherein one of the inverting output of the SR latch….”. However, claim 6 recites “an inverting output of the SR latch …”. The language used for claim 8 seems to imply that the SR latch has more than one inverting output, while claim 6 implies that the SR latch has only one inverting output. Therefore, it’s not clear if there is one or more than one inverting output.
For examination purpose, the examiner will interpret “.. wherein one of the inverting output of the SR latch …” as “.. wherein the inverting output of the SR latch is …”.
Claim Rejections - 35 USC § 102
6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
7. Claim(s) 1 - 4, 11 and 16 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Vaquette (US Pub. No. 2020/0244172 A1); (hereinafter Vaquette).
Regarding claim 1, Vaquette [e.g., Figs. 1 - 5] discloses a circuit [e.g., -- refer to Fig. 1 --, switched power converter 100], comprising: a switching system including a switch coupled to a flyback inductor terminal [e.g., primary FET 116 coupled to winding 108] and configurable to: set a state of the switch responsive to a comparison between a current through the switch and a threshold [e.g., controls primary FET 116 based on comparison between primary current and a predetermined threshold value 212, p. 0056 recites “…, as the load increases above a certain point, the primary current peak value Ip_pk rises above a predetermined threshold. In the example system of FIG. 3, the mode controller 306 indirectly senses that the primary current peak value Ip_pk has met or exceeded the predetermined threshold by observance of the gate signal applied to the second gate input 322; however, in other cases the mode controller 306 may be provided the predetermined value and/or the primary current peak value Ip_pk value directly from the constant voltage controller 302.”]; and circuitry configurable to set the threshold responsive to a converter output voltage [e.g., setpoint established by the primary-side controller 122 based on the monitored output voltage, p.0027 recites “During the discharge cycle, the primary-side controller 112 monitors a value indicative of output voltage. If the output voltage is low, the primary side controller increases the primary-side current setpoint for the next energy storage cycle. If the output voltage is high, the primary-side controller 112 decreases the primary-side current setpoint for the next energy storage cycle.”].
Regarding claim 2, Vaquette [e.g., Figs. 1 - 5] discloses wherein the threshold is a first threshold [e.g., predetermined value 212], and the switching system is configurable to enable the switch responsive to an instantaneous amplitude of a converter output current falling below a second threshold [e.g., --refer to Fig. 2 - enables FET 116 when secondary current reaches zero after discharge cycle 210 at t6] and deactivate the switch responsive to the current exceeding the first threshold [e.g., turns off FET 116 when primary current exceeds predetermined value 212, p. 0044 recites “The predetermined value 212 represents a target amount of current after which the storing of energy ceases. The predetermined value 212 can be defined as the primary-side peak current setpoint. At time t3, the primary current reaches a primary current peak value Ip_pk.”]; and wherein the circuitry is configurable to set the first threshold responsive to an average of the converter output voltage [e.g., p. 0048 recites “Throughout the duration of the energy storage cycle 208 and the discharge cycle 210, the output current IOUT (plot 200) is the average of the secondary current produced during the same time period. Furthermore, the value of the primary current peak value Ip_pk in a given energy storage cycle influences the output current IOUT. For example, the value of the primary current peak value Ip_pk occurring in the energy storage cycle 208 controls the secondary current (ISEC) produced in the subsequent discharge cycle 210, which in turn contributes to the output current. If during successive energy storage cycles, the value of the primary current peak value Ip_pk increases, the secondary current in respective discharge cycles will also increase. In turn the overall average of the output current will also increase. Similarly, if during successive energy storage cycles, the value of the primary current peak value Ip_pk decreases, the secondary current in respective discharge cycles will also decrease. In turn, the overall average of the output current will also decrease.”].
Regarding claim 3, Vaquette [e.g., Figs. 1 - 5] discloses wherein the circuitry is configurable to set the first threshold responsive to a converter input voltage [e.g., Primary-Side Controller 112 sets predetermined value 212 responsive to primary current IPRI responsive to input voltage VIN].
Regarding claim 4, Vaquette [e.g., Figs. 1 - 5] discloses wherein the switching system is configurable to receive a signal representing the instantaneous amplitude of the converter output current from an output current detector [e.g., -- refer to Fig. 3 for a block diagram of a primary-side controller --, receives current from sense node 124 via current sense terminal 138 and inputted to Constant Current Controller 304 and Constant Voltage controller 302].
Regarding claim 11, Vaquette [e.g., Figs. 1 - 5] discloses an apparatus [e.g., -- refer to Fig. 1 --, switched power converter 100], comprising: a flyback converter including: a switching system including a switch coupled to a flyback inductor terminal [e.g., primary FET 116 coupled to primary winding 108] and configurable to set a state of the switch responsive to a comparison between a current through the switch and a threshold [e.g., controls primary FET 116 based on comparison between primary current and a predetermined threshold value 212, p. 0056 recites “…, as the load increases above a certain point, the primary current peak value Ip_pk rises above a predetermined threshold. In the example system of FIG. 3, the mode controller 306 indirectly senses that the primary current peak value Ip_pk has met or exceeded the predetermined threshold by observance of the gate signal applied to the second gate input 322; however, in other cases the mode controller 306 may be provided the predetermined value and/or the primary current peak value Ip_pk value directly from the constant voltage controller 302.”]; and circuitry configurable to set the threshold responsive to an output voltage of the flyback converter [e.g., setpoint established by the primary-side controller 122 based on the monitored output voltage, p.0027 recites “During the discharge cycle, the primary-side controller 112 monitors a value indicative of output voltage. If the output voltage is low, the primary side controller increases the primary-side current setpoint for the next energy storage cycle. If the output voltage is high, the primary-side controller 112 decreases the primary-side current setpoint for the next energy storage cycle.”].
Regarding claim 16, Vaquette [e.g., Figs. 1 - 5] discloses wherein the threshold is a first threshold [e.g., predetermined value 212], and the switching system is configurable to enable the switch responsive to an instantaneous amplitude of a converter output current falling below a second threshold [e.g., --refer to Fig. 2 - enables FET 116 when secondary current reaches zero after discharge cycle 210 at t6] and deactivate the switch responsive to the current exceeding the first threshold [e.g., turns off FET 116 when primary current exceeds predestined value 212, p. 0044 recites “The predetermined value 212 represents a target amount of current after which the storing of energy ceases. The predetermined value 212 can be defined as the primary-side peak current setpoint. At time t3, the primary current reaches a primary current peak value Ip_pk.”]; and wherein the circuitry is configurable to set the first threshold responsive to an average of the output voltage [e.g., p. 0048 recites “Throughout the duration of the energy storage cycle 208 and the discharge cycle 210, the output current IOUT (plot 200) is the average of the secondary current produced during the same time period. Furthermore, the value of the primary current peak value Ip_pk in a given energy storage cycle influences the output current IOUT. For example, the value of the primary current peak value Ip_pk occurring in the energy storage cycle 208 controls the secondary current (ISEC) produced in the subsequent discharge cycle 210, which in turn contributes to the output current. If during successive energy storage cycles, the value of the primary current peak value Ip_pk increases, the secondary current in respective discharge cycles will also increase. In turn the overall average of the output current will also increase. Similarly, if during successive energy storage cycles, the value of the primary current peak value Ip_pk decreases, the secondary current in respective discharge cycles will also decrease. In turn, the overall average of the output current will also decrease.”].
8. Claim(s) 17 is rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Wang (US Pub. No. 2019/0006935 A1); (hereinafter).
Regarding claim 17, Wang [e.g., Fig. 2] discloses a circuit [e.g., switching converter 20], comprising: a switching system having a first input [e.g., top terminal of switch M1], a second input [e.g., current sense Ics received by non-inverting terminal of comparator 204], a third input [e.g., a peak current reference signal Ipk_ref], and an output [e.g., switching control signal PG], the first input of the switching system being coupled to a flyback inductor [e.g., top terminal of switch M1 coupled to primary winding of T1. For examination purposes, the examiner will interpret the term "coupled" in its broadest sense to refer as electrical components that are connected directly or indirectly in a way that allows for the transfer of electrical energy or signals between them], the second input of the switching system being coupled to an output of an output current detector [e.g., second input Ics coupled to current sense, p. 0031 recites "The current sense signal Ics indicates the current flowing through the transformer T1. Any circuit performing current sense may be used with the present technology. In one embodiment, the current sense signal Ics may be obtained by sensing a current flowing through the primary winding or the secondary winding of the transformer T1"]; and a reference controller, comprising: an output voltage sampler [e.g., Valley detecting circuit 201 and Mode detecting circuit 202] having a first input [e.g., input via Valley detecting circuit 201 (VDS)], a second input [e.g., input via Mode detecting circuit 202, p. 0026 recites "The mode detecting circuit 202 detects whether the switching converter 20 is working under CCM, and provides a mode detecting signal VM based thereon"], and an output [e.g., output of Valley detecting circuit 201], the first and second inputs of the output voltage sampler being coupled across the flyback inductor [e.g., first two inputs coupled across primary winding of transformer T1], and a variable reference generator [e.g., Peak Current regulating circuit 203] having an input and an output [e.g., input receiving VL via Valley detecting circuit 201 and output Δlpk supplied to peak current comparing circuit 204], the input of the variable reference generator being coupled to the output of the output voltage sampler [e.g., input of Peak current regulating circuit 203 coupled to output of valley detecting circuit 201], and the output of the variable reference generator being coupled to the third input of the switching system [e.g., Peak current regulating circuit 203 coupled to subtractor receiving peak current reference signal Ipk_ref].
Claim Rejections - 35 USC § 103
9. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
11. Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vaquette (US Pub. No. 2020/0244172 A1) in view of Zheng et al (US Pub. No. 2014/0268913 A1); (hereinafter Vaquette and Zheng et al).
Regarding claim 5, Vaquette [e.g., Figs. 1 - 5] discloses wherein the second threshold is zero in a transition mode [e.g., threshold is zero during discharging cycle p. 0046 - 0047 recites "At time t4, the transformer 106 enters the discharge cycle 210 in which energy is transferred from the field of the transformer 106. The example discharge cycle 210 is defined as starting at time t4 and ending at time t6. At time t4, the primary current IPRI begins to drop to zero, however, due to leakage inductance effects, the drop to zero does not happen instantaneously. At time t5, the primary current IPRI is zero and remains there for the remainder of the discharge cycle 210. The time period t2 is defined as between t5 and t6.[0047] Upon the primary current IPRI dropping to zero, the voltage induced on the secondary winding 126 reverses polarity and the diode 158 begins to conduct. Accordingly, during the discharge cycle 210, the collapsing field of the transformer 106 produces secondary current ISEC through the secondary winding 126 (plot 202). At time t6, the energy of the field of the transformer 106 is discharged, and the primary-side controller 112 re-asserts the gate terminal 136 again and another energy storage cycle begins anew."]
Vaquette does not disclose wherein the second threshold is greater than zero in a continuous conduction mode (CCM).
Zheng et al teaches wherein the second threshold is greater than zero in a continuous conduction mode (CCM) [e.g., p. 0039 recites "Accordingly, in CCM operation, for each switching cycle, the initial primary-side switching current may be high. Given the same Vin*tON (i.e., voltage-time product) applied to the transformer T1-A, the delta current increase is fixed. However, because the initial primary-side switching current may be relatively high compared to the current levels in PFM, DCM, and CDCM operation, the "ending" primary-side switching current during CCM operation may also be relatively high. For example, in CCM operation the controller IC 102 does not wait for the transformer reset to initiate the next cycle. Thus, in CCM operation the initial current is not zero. Instead, the increased switching current based on Vin*tON is in addition to the initial non-zero current, resulting in a higher ending current. By employing this CCM method, the controller IC 102 causes the transformer T1-A to output energy that is significantly higher than normal DCM or CDCM operation”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Vaquette with wherein the second threshold is greater than zero in a continuous conduction mode (CCM) as suggested by Zheng et al since its expected for predetermined current threshold to be greater than zero since the controller does not wait for the transformer reset to initiate the next cycle and as a result, during CCM operation the initial current is not zero.
12. Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US Pub. No. 2019/0006935 A1) in view of Brinlee et al (US Pub. No. 2014/0254215 A1); (hereinafter Wang and Brinlee et al).
Regarding claim 19, Wang discloses the claimed invention except for wherein the output voltage sampler comprises: a voltage sensor having a sampling voltage approximately equal to an output voltage of the flyback inductor; a sampling switch coupled to the voltage sensor, the sampling switch being activated in response to a sampling signal; a sampling capacitor coupled to the sampling switch, the sampling capacitor being configured to sample the sampling voltage in response to activation of the sampling switch; and a monostable flip-flop configured to generate the sampling signal in response to deactivation of a primary switch of the switching system.
Brinlee et al [e.g., Figs. 6 and 7] teaches wherein the output voltage sampler [e.g., secondary side controller] comprises: a voltage sensor [e.g., -- refer to Fig. 6 --, voltage sensed by reference voltage and wake-up comparator 610 contained within One Shot Generator and Switching Lockout circuit 720] having a sampling voltage approximately equal to an output voltage of the flyback inductor [e.g., samples Vout]; a sampling switch coupled to the voltage sensor [e.g., switch 710 coupled to One Shot Generator and Switching Lockout circuit 720], the sampling switch being activated in response to a sampling signal [e.g., opens or closes depending on signal generated by One Shot Generator and Switching Lockout circuit 720]; a sampling capacitor coupled to the sampling switch [e.g., capacitor coupled to switch 710 and Vout], the sampling capacitor being configured to sample the sampling voltage in response to activation of the sampling switch [e.g., charges and discharges depending on switch 710]; and a monostable flip-flop [e.g., one-shot pulse generator and switching lockout circuit 720] configured to generate the sampling signal in response to deactivation of a primary switch of the switching system [e.g., generates signal when 750 turns off, p. 0056 recites “The secondary side of the power converter includes the one-shot pulse generator and switching lockout circuit 720 coupled to a switch 710, which closes the switch 710 (i.e., causes the switch 710 to conduct) during a brief interval of time to produce a voltage pulse across the secondary winding S1 when the output voltage Vout declines below a threshold voltage level.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Wang with wherein the output voltage sampler comprises: a voltage sensor having a sampling voltage approximately equal to an output voltage of the flyback inductor; a sampling switch coupled to the voltage sensor, the sampling switch being activated in response to a sampling signal; a sampling capacitor coupled to the sampling switch, the sampling capacitor being configured to sample the sampling voltage in response to activation of the sampling switch; and a monostable flip-flop configured to generate the sampling signal in response to deactivation of a primary switch of the switching system as suggested by Brinlee et al to sample the output voltage and generate a signal corresponding to the sampled output voltage value to regulate an output characteristic of the power converter.
Response to Arguments
13. Applicant's arguments filed 03/16/2026 have been fully considered but they are not persuasive.
Applicant(s) argue(s) with respect to claims 1 and 11:
“Amended claim 1 recites, inter alia, "circuitry configurable to set the threshold responsive to a converter output voltage." Vaquette fails to disclose at least such claim elements…. the Office alleges that predetermined value 212 in FIG. 2 of
Vaquette corresponds to the claimed threshold set based responsive to a converter output voltage.
Applicant respectfully disagrees, at least because Vaquette does not disclose setting 212 based on the converter output voltage. Vaquette describes compensating a subsequent predetermined value 212 based on the value indicative of input voltage VIN. Vaquette, [0049]. But Vaquette does not disclose adjusting 212 based on the converter output voltage Vout. In contrast, claim 1 recites "circuitry configurable to set the threshold responsive to a converter output voltage."
In response, the setpoint established by the primary-side controller is based on the monitored output voltage, as shown in p.0027 recites “During the discharge cycle, the primary-side controller 112 monitors a value indicative of output voltage. If the output voltage is low, the primary side controller increases the primary-side current setpoint for the next energy storage cycle. If the output voltage is high, the primary-side controller 112 decreases the primary-side current setpoint for the next energy storage cycle”. As disclosed by Vaquette the primary side controller adjust the primary side current setpoint in response to a value indicative of the output voltage. As a result, the rejection is maintained.
Applicant(s) argue(s) with respect to claim 17
“Moreover, amended claim 17 recites, inter alia, "an output voltage sampler having a first input, a second input, and an output, the first and second inputs of the output voltage sampler being coupled across the flyback inductor." Wang fails to disclose at least these claim elements, at least because in Wang, the valley detection circuit 201 (the alleged output voltage sampler) is not coupled across the primary winding of T1 (the alleged flyback inductor). In contrast, claim 17 recites "the output voltage sampler being coupled across the flyback inductor." For at least these reasons, claim 17 is not anticipated by Wang.”
In response, it is possible to see in Wang the control circuit 200 which has two inputs coupled across the primary winding of switching converter 20. Specifically, the Mode Detecting circuit 202 coupled to the output of the primary winding and Valley Detecting circuit 201 coupled across transformer T1 to generate signals VL and VM received by the Peak current regulating circuit 203 to generate peak current regulating signal ΔIPK, which corresponds to the output voltage of the primary winding. As a result, the rejection is maintained.
Examiner’s Note
14. Examiner has cited particular columns, paragraphs and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figure may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art disclosed by the Examiner.
15. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Allowable Subject Matter
16. Claims 6 - 7, 9 - 10, 12 - 15, 18 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
17. Claim 8 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the indication of the allowability of claim 6 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of "…; and wherein the switching system includes: a comparator configurable to provide a signal responsive to the comparison between the current and the threshold; and an SR latch having a non-inverting output coupled to the primary switch, an inverting output coupled to the output voltage sampler, a set input coupled to the output current detector, and a reset input coupled to an output of the comparator.".
The primary reason for the indication of the allowability of claim 10 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “… a summation component configurable to generate a summation voltage of a converter input voltage and the converter output voltage; a division component configurable to divide the summation voltage by the converter input voltage to generate a division term voltage; and a multiplication component configurable to multiply the division term voltage by a value indicative of a constant average amplitude of the converter output current to generate the threshold.”
The primary reason for the indication of the allowability of claim 12 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “…a comparator configurable to provide a signal responsive to the comparison between the current and the threshold; and comprises an SR latch having a non-inverting output coupled to the switch, an inverting output coupled to the output voltage sampler, a set input coupled to an output current detector, and a reset input coupled to an output of the comparator”.
The primary reason for the indication of the allowability of claim 15 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “…a summation component configurable to generate a summation voltage of a converter input voltage and the output voltage; a division component configurable to divide the summation voltage by the converter input voltage to generate a division term voltage; and a multiplication component configurable to multiply the division term voltage by a value indicative of a constant average amplitude of the output current of the flyback converter to generate the threshold.”
The primary reason for the indication of the allowability of claim 18 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “…; a comparator having a first input, a second input, and an output, the first input of the comparator being coupled to the output of the current sensor, the second input of the comparator being coupled to the output of the variable reference generator; and an SR latch having a first input, a second input, a first output, and a second output, the first input of the SR latch corresponding to the second input of the switching system, the second input of the SR latch being coupled to the output of the comparator, the first output of the SR latch being coupled to the control terminal of the primary switch, and the second output corresponding to the output of the switching system.”
The primary reason for the indication of the allowability of claim 20 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “… a summation component configured to add the sampled output voltage and an input voltage associated with an input current of a flyback inductor to generate a summation voltage; a division component configured to divide the summation voltage by the input voltage to generate a division term voltage; and a multiplication component configured to multiply the division term voltage by a programmable multiplier associated with a constant average amplitude of output current of the flyback inductor to generate a variable voltage reference voltage associated with a variable peak current amplitude”.
Conclusion
18. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MONICA LEWIS/ Supervisory Patent Examiner, Art Unit 2838
/ULARISLAO CORDOVA/Examiner, Art Unit 2838
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