Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
As per the instant application having Application No. 18/636,879; the amendment filed on 12/1/2025 with subsequent request for continued examination (RCE) filed on 12/11/2025 is herein acknowledge. Claims 1, 6, 15, 17, 19 and 27-28 have been amended and claims 3-5, 8-14 and 16 have been canceled. Claims 1-2, 6-7, 15 and 17-28 are pending.
In the response to this Office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/11/2025 has been entered.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 7, 15 and 17-28 are rejected under 35 U.S.C. 103 as being unpatentable over Erickson (US 2022/0179799) in view of Roberts (US 20240070072), Koufaty et al. (US 11,526,290), Duluk, Jr. et al. (US 2014/0281110) and Jin et al. (US 2025/0208996), Continuation of PCT/CN2023/010381, filed on Jun. 29, 2023, with Foreign Priority To claims foreign priority to CN 202211431336.4, filed 11/14/2022 and CN 202211180232.0, filed 09/26/2022.
1. A system for managing pages in memory, the system comprising: one or more computing processors having near memory; [Erickson teaches each server having one or more CPUs 111 comprising CPU cores 121 having local memory 115 (fig. 1 and related text; par. 0017)]
far memory coupled to the one or more computing processors; and [remote memory, MV-attached memory 116 (fig. 1 and related text; par. 0018)]
one or more telemetry processors, wherein the one or more telemetry processors are configured to: [Erickson teaches “memory virtualizer 117 additionally includes an access/allocation engine 133 (AAE)” where AAE comprises “MV controller 173” where “MV controller implemented, for example, by a programmed processor, sequencer, finite state machine, etc.) “ (par. 0021) (fig. 2 and related text), where MV controller comprises “page-access engines (180, 182) implemented by MV controller 173 together with a page migration engine 184” (par. 0026; fig. 2 and related text)] where the AAE is interpreted to correspond to the claimed telemetry processor but Erickson does not expressly refer to the AAE processor as a telemetry processor
receive a page access request from one or more computing processors; [Erickson teaches “[0027] FIG. 3 illustrates exemplary memory-access and statistic collection operations implemented concurrently (i.e., at least partly overlapping in time) by page access engine 182 of FIG. 2. As shown, page access engine 182 responds to an incoming load/store instruction and MV-associated LPA by concurrently executing memory access and access-statistic collection operations (201 and 203 respectively).”]
parse the page access request by: identifying a memory address associated with the requested page;… [Erickson teaches the LPA of the access request is identified (par. 0027) “In both cross-fabric and virtualizer-attached memory accesses, the LPA is used to index an access counter and increment or otherwise update the indexed counter as shown at 215.” (par. 0027; fig. 3 and related text)
query a directory using the subset of bits to determine that the directory contains a record associated with the requested page; and [Erickson teaches “(AAE)… serving as a centralized memory allocation coordinator for all operating memory pages allocated to processes executed by local CPU cores 121 (and pages allocated to CPU cores of other MP servers), and also as the gateway and access-statistics collector for local-CPU access requests that map to remote memory – that is, to MV-attached memory 116 and/or memory installation on other MP servers” (par. 0018) “page allocation engine 180 allocates and initializes access-statistics data structures 185, for example, by allocating one or more fields within page tables and TLBs for counter storage, allocating a counting elements within a hardware counter, etc. … incrementing an access count for each access to a corresponding memory page (or group of memory pages) within a given interval, with optional inclusion of historical data from prior intervals” (par. 0026) “the LPA is used to index an access counter and increment or otherwise update the indexed counter as shown at 215.” (par. 0027) “[0028] FIG. 4 illustrates a more detailed embodiment of an LPA-indexed page table 231 and corresponding LPA-indexed translation lookaside buffer 233 having address, cross-fabric and access-count fields (FA/MVPA, X, AC, respectively) organized in a per-entry address/counter tuple 235”. Note that since access-statistics data structures may be initialized or counters incremented if already present, it is effectively determined whether the data structures contain a record for the requested page. (see figs. 8 and 9 and related text); thus, the LPA which corresponds to the accessed page is used to access the access-statistics data structure or directory] but Erickson does not expressly refer to the index of the data structure being the subset of bits identifying the memory page
in response to determining that the directory contains the record associated with the requested page, increment an access count associated with the requested page [Erickson teaches “page allocation engine 180 allocates and initializes access-statistics data structures 185, for example, by allocating one or more fields within page tables and TLBs for counter storage, allocating a counting element within a hardware counter, etc. Similarly, as page access engine 182 carries out remote-memory load/store operations (e.g., generally as discussed above, translating LPA to FA or MVPA and directing the translation result to the fabric interface or virtualizer-attached memory as the case may be), the page access engine updates the access statistics, for example, incrementing an access count for each access to a corresponding memory page (or group of memory pages) within a given interval, with optional inclusion of historical data from prior intervals.” (par. 0026; fig. 2 and related text) “the LPA is used to index an access counter and increment or otherwise update the indexed counter as shown at 215.” (par. 0027) (see figs. 8 and 9 and related text)].
Erickson does not expressly disclose identifying a page size of the requested page; determining a number of upper bits and lower bits of the memory address based on the page size; reducing the memory address into the upper bits and lower bits, where the lower bits are offset bits; and removing the offset bits from the memory address to generate a subset of bits that identify the requested page… the directory comprising a bitmap having a maximum number of bits corresponding to a capacity of the directory, wherein each bit of the bitmap corresponds to a different page stored in the far memory and the capacity of the directory corresponds to a capacity of pages maintained by the directory.
Regarding the limitations of a telemetry processor performing the access monitoring, Roberts teaches [“[0013] Memory telemetry can be used by the host system and/or by the memory sub-system controller to optimize memory usage. Memory telemetry can include memory access statistics, such as a frequency of access metric (i.e., a memory access count), or a reuse distance metric (i.e., a number of distinct memory accesses made by multiple memory references to the same location).” Where “[0020] The memory sub-system controller can then transmit the access counter values to the host system. In some embodiments, the memory sub-system controller can combine access counter values from other sources with its own access counter values. For example, a computing system can have multiple telemetry-capable memory sub-systems, in which case the memory sub-system controller can combine the access counter values generated by the multiple telemetry-capable memory sub-systems. The memory sub-system controller and/or the host system can compare the system-wide memory activity to make system-level data management decisions.” And where “[0033] A memory sub-system controller 115 (or controller 115 for simplicity) can communicate with the memory devices 130 to perform operations such as reading data, writing data, or erasing data at the memory devices 130 and other such operations. The memory sub-system controller 115 can include hardware such as one or more integrated circuits and/or discrete components, a buffer memory, or a combination thereof. The hardware can include a digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory sub-system controller 115 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.”].
Erickson and Roberts are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify Erickson to implement the processor which monitors access counts of Erickson as a telemetry processor performing the access monitoring as taught by Roberts since doing so would provide the benefits of [“[0021] In some embodiments, the memory sub-system controller can implement a variety of memory management schemes to optimize memory usage based on the access counter values. The memory management schemes can include, for example, data placement techniques, page scheduling techniques, application optimization techniques, application security monitoring techniques, VM provisioning techniques, and/or cache sizing techniques. The memory management schemes can optimize memory usage, thus increasing performance of the computing system as a whole, and increasing performing of application usability.”].
The combination of Erickson and Roberts does not expressly disclose identifying a page size of the requested page; determining a number of upper bits and lower bits of the memory address based on the page size; reducing the memory address into the upper bits and lower bits, where the lower bits are offset bits; and removing the offset bits from the memory address to generate a subset of bits that identify the requested page… the directory comprising a bitmap having a maximum number of bits corresponding to a capacity of the directory, wherein each bit of the bitmap corresponds to a different page stored in the far memory and the capacity of the directory corresponds to a capacity of pages maintained by the directory.
Regarding the limitations identifying a page size of the requested page; determining a number of upper bits and lower bits of the memory address based on the page size; reducing the memory address into the upper bits and lower bits, where the lower bits are offset bits; and removing the offset bits from the memory address to generate a subset of bits that identify the requested page… query a directory using the subset of bits, Koufaty teaches [“To address the aforementioned issues, an aspect of this disclosure is directed to a new mechanism for implementing and maintaining attributes (i.e. metadata) for physical addresses in a physical address space. According to an embodiment, the physical memory is divided into variable-size physical pages, each physical page associated with its own set of attributes. The attributes may be maintained by software, hardware, or a combination thereof. According to an embodiment, the attributes are used to drive data movement and/or migration policies as well as access permission. The attributes may also be used to guide software optimizations.” (col. 4, lines 7-18) where “FIG. 3A is a block diagram illustrating a PAT organized as a flat table according to an embodiment. The PAT root 312 is an address or a pointer that identifies the location 320 of where the PAT is stored. For example, the PAT may be stored in memory and the PAT root 312 identifies the memory location 320 that stores the head of the PAT. The PAT root 312 itself may be stored in a regis
ter of the CPU, IOMMU, or device. It may also be stored in the memory. To locate a PAT entry for a particular physical address 310, M-bits of the physical address 310 are used as an offset into the memory location 320, which is identified by the PAT root 312. The number of M-bits to use depends on the desired size of the PAT. In one embodiment, where each memory page is of 2.sup.N KB in size (thus, identifying the page size of the requested page), the least significant N-bits (corresponding to the claimed lower bits) are not used because the physical addresses in that range all belong to the same memory page (thus, the rest of the bits, excluding the N lower bits are used to identify the memory page, where for a page of 2.sup.N KB, the N bits are not used to identify the page and are thus identified based on the page size of 2.sup.N KB) and thus share the same attributes. As such, only one PAT entry is needed for each memory page.” (col. 7, lines 18-34; fig. 3A and related text) where Koufaty explains attributes are maintained for each memory page 510 (see fig. 5 and related text), including access counts which are incremented when the corresponding memory page is accessed (see col. 8, lines 44-62)] but Koufaty does not expressly refer to query a directory using the subset of bits.
Erickson, Roberts and Koufaty are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Erickson and Roberts to identify a page size of the requested page; reduce the memory address into upper bits and lower bits based on the page size, wherein the lower bits are offset bits; and remove the offset bits from the memory address to generate a subset of bits that identify the requested page as taught by Koufaty since doing so would provide the benefits of [facilitating storage of page physical attributes in a physical attribute table since “As such, only one PAT entry is needed for each memory page” (col. 7, lines 33-34) and help optimize performance for example, by facilitating “migrating data between local and remote memory locations, etc” (col. 4, lines 19-29)].
The combination of Erickson, Roberts and Koufaty does not expressly disclose “query a directory using the subset of bits” … the directory comprising a bitmap having a maximum number of bits corresponding to a capacity of the directory, wherein each bit of the bitmap corresponds to a different page stored in the far memory and the capacity of the directory corresponds to a capacity of pages maintained by the directory.
Regarding the limitations query a directory using the subset of bits, Duluk teaches [“[0093] The access tracking unit 220 tracks access operations to various shared memory pages by the PPU 202 over communications path 113. Shared memory pages residing in system memory 104 that are accessed often by the PPU 202 may be candidates for migration from system memory 104 to PPU memory 204. The access tracking unit 220 monitors communications path 113 for memory access operations issued by the PPU 202 that are directed to shared memory pages residing in system memory 104. When the access tracking unit 220 detects such a memory access operation, the access tracking unit 220 extracts the page number of the memory access operation, where the page number typically includes the leftmost bits of the memory address associated with the memory access operation. The access tracking unit 220 records the page numbers associated with such memory access operations with a reference count that indicates the number of times each shared memory page was accessed by the PPU 202. The access tracking unit 220 stores these page numbers, along with related information, in the access cache memory 230, as further described herein.” “[0098] If the access tracking unit 220 detects a memory access operation from the PPU 202 directed to a shared memory page in system memory 104, then the access tracking unit 220 determines whether the access cache memory 230 includes a valid access cache entry corresponding to the accessed memory page. If a valid entry exists for the accessed memory page, then the access tracking unit 220 increments the reference count in the access cache entry. If a valid entry does not exist for the accessed memory page, then the access tracking unit 220 selects an unused cache access entry, and stores the page number in the unused entry. The access tracking unit the initializes the reference count for the unused cache access entry and sets the corresponding valid bit.” “[0104] The field identifiers 310 indicate that each access cache memory entry 320 includes a page number field 330, a valid bit field 340, and a reference count field 350.” “[0105] The page number field 330 is associated with the memory address of the first location of the corresponding shared memory page. Typically, the page number is the leftmost portion of the memory address specified by the memory access operation. For example, if memory addresses directed to shared memory are 48-bits wide and each shared memory page is 2.sup.16 or 64 k bytes long, then the page number would be the leftmost 32 bits of the memory address. In another example, if a shared memory address includes 40 bits, and the page size is 4 kB (12 bits of address space), then the page frame would include 40-12=28 bits. In yet another example, if a physical address includes 42 bits, and the page size is 4 kB (12 bits of address space), then the page number would include 42-12=30 bits.”]; thus, according to Duluk, the page number field (which corresponds to the upper or leftmost portion of the memory address) is used to query/access the cache memory or directory shown in fig. 3 and related text which is used to record the number of accesses or reference count for each page. Note that according to Duluk, the page number is based on the page size (see par. 0105).
Erickson, Roberts, Koufaty and Duluk are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Erickson, Roberts and Koufaty to specifically query the directory using the subset of bits as taught by Duluk since doing so would provide the benefits of facilitating access tracking to memory pages as well as accessing to the data structure/directory storing the access tracking information.
The combination of Erickson, Roberts, Koufaty and Duluk does not expressly disclose the directory comprising a bitmap having a maximum number of bits corresponding to a capacity of the directory, wherein each bit of the bitmap corresponds to a different page stored in the far memory and the capacity of the directory corresponds to a capacity of pages maintained by the directory; however, regarding these limitations, Jin teaches [“The access record table includes a plurality of access fields, and each access field corresponds to a page number of one physical page, so that each access field is associated with a corresponding physical page. For example, the access record table is a bitmap. Assuming that the first storage space is a physical memory of 64 gigabytes (GB), and a size of the physical page is 64 kilobytes (KB), the operating system allocates a bitmap of 128 KB to the first storage space as the access record table (thus, the bitmap or record table having a number of bits corresponding to the capacity of the directory). Each bit in the bitmap is associated with one access field, and each bit is associated with one physical page in the first storage space (thus, the capacity of the directory or record table corresponds to a capacity of pages mainttained).” (par. 0056) “[0074] For example, the access record table is a bitmap. When cold/hot identification is performed on the physical page, the processor uses a first duration as a read periodicity. Each time the first duration elapses, the processor reads an access identifier stored in the access field that is associated with the physical page and that is in the access record table, in other words, obtains an access identifier of the physical page in a time period including the first duration, and stores the access identifier of the physical page. If the access identifier of the physical page is the first access identifier, it indicates that the application program has accessed the physical page in the time period including the first duration. If the access identifier of the physical page is the second access identifier, it indicates that the application program has not accessed the physical page in the time period including the first duration. In some embodiments, the processor uses a second duration as a cold/hot physical page identification periodicity.” (see figs. 1-2 )].
Erickson, Roberts, Koufaty, Duluk and Jin are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Erickson, Roberts, Koufaty and Duluk to have the far memory directory of the combination implemented as a bitmap as taught by Jin such that the directory comprising a bitmap having a maximum number of bits corresponding to a capacity of the directory, wherein each bit of the bitmap corresponds to a different page stored in the far memory and the capacity of the directory corresponds to a capacity of pages maintained by the directory since doing so would provide the benefits of [“[0006] This application provides a cold/hot physical page identification method and apparatus, a chip, and a storage medium, to improve efficiency of accessing a storage medium by an application program.”].
Therefore, it would have been obvious to combine Erickson, Roberts, Koufaty, Duluk and Jin for the benefit of creating a storage system/method to obtain the invention as specified in claim 1.
2. The system of claim 1, wherein the one or more telemetry processors are further configured to transmit a signal to the one or more computing processors indicating the access count associated with the requested page has been incremented [Roberts teaches “[0018]… That is, if the host system accesses the line (e.g., by issuing a read or a write request referencing the line), it sends an access notification to the current owner of the line. Following the receipt of an access notification, the memory sub-system controller increases the counter associated with the segment, and releases ownership of the line. The memory sub-system controller can then request ownership of another line of the segment in order to monitor a consistent number of lines of each segment at once. While the memory sub-system controller can monitor any number of lines of each segment, the number of lines monitored should remain consistent.” “[0020] The memory sub-system controller can then transmit the access counter values to the host system.” (see fig. 5 and related text) where “ At operation 530, the processing logic increases a value of an access counter associated with the segment.” (par. 0092) and at operation 560, the value of the access counter is transmitted to the host].
7. The system of claim 1, wherein the access count indicates a number of times a request to access the page is parsed [Erickson teaches “the page access engine updates the access statistics, for example, incrementing an access count for each access to a corresponding memory page (or group of memory pages) within a given interval, with optional inclusion of historical data from prior intervals.” (par. 0026) “the access bits and access counters for local and remote memory pages, respectively, are analyzed/evaluated, leading to selection of a relatively cold local memory page for down-migration (local page 0x01 for which access bit shows no-access during t0) and selection of a relatively warm remote memory page (remote page 0x0D having maximum access count within the exemplary four-page group) for up-migration” (par. 0033; figs. 6-7 and related text). Roberts teaches “[0047] The memory access monitoring component 113 can maintain an access counter for each segment of memory that it monitors, and can increase the corresponding access counter each time a segment is accessed. The memory access monitoring component 113 can monitor entire segments, or can monitor a subset of each segment.” Koufaty teaches recording page access counts (fig. 5 and related text). Duluk teaches “[0093] The access tracking unit 220 records the page numbers associated with such memory access operations with a reference count that indicates the number of times each shared memory page was accessed by the PPU 202. The access tracking unit 220 stores these page numbers, along with related information, in the access cache memory 230, as further described herein.”].
15. The system of claim 12, wherein a state of a bit indicates whether the access count for the requested page exceeds the access threshold for the requested page [Erickson teaches “As discussed below, the page-access statistics may include both high-resolution access counts generated by the page access engine within the memory virtualizer (i.e., for access to remote memory, both cross-fabric and virtualizer attached) and low-resolution access/no-access information from the VA-to-LPA page table entries for local memory pages (i.e., bit indicating page accessed or not accessed).” (par. 0029; figs. 5, 7 and 9-10 and related text), where a page having been accessed represents an access count exceeding a threshold of 0. John teaches “At operation 520, a hotness indicator and an access density is determined for the page… monitor a page access count for each memory page during a time period. When the access count crosses a specified threshold, a special bit may be set in the Page Table Entry (PTE) for the page. The bit may indicate that the page is hot.” (col. 9, line 50-col. 10, line 3; fig. 5 and related text)]. It would have been obvious to one of ordinary skill in the art to modify the page access counters of Erickson which correspond to far or remote memory to have a bit set for each page access counter that exceeds a threshold in a bitmap form as taught by John since doing so would facilitate migration operation of hot pages. Jin further teaches [“[0045] In a possible implementation, the access record table 105 is a bitmap, the access field 51 is a bit, and each bit corresponds to a page number of one physical page in the storage medium 102. For example, a 1.sup.st bit in the access record table corresponds to a page number 1, a 2.sup.nd bit corresponds to a page number 2, and so on. If the TLB miss occurs when the application program accesses a physical page in the storage medium 102, the processor 101 sets a corresponding bit in the access record table to the first access identifier (for example, 1) based on a page number of the physical page, so that the processor 101 subsequently reads an access identifier of each physical page from the access record table 105, and performs, based on the read access identifier, the cold/hot physical page identification method provided in this application.”].
17. The system of claim 1, wherein the directory further comprises a list [Erickson teaches “ In some implementations, for example, the memory virtualizer maintains an LPA-indexed list of pages undergoing migration (e.g., as a bit field within an address translation table, access statistics table, and/or dedicated “active-migration” lookup table) and affirmatively delays access requests directed LPAs for which migration is indicated (by table lookup) to be under way” (par. 0030) where the warmest pages are selected for migration and the list of pages being migrated thus comprises most requested pages stored in far or remote memory, as Erickson teaches “relatively warm (access count=250) remote memory page 0x0A for up-migration—operations reflected by the relative page locations shown at the start of interval t3. Access-statistic evaluation at the start of t3 leads, in the depicted example, to determination not to migrate any pages during that interval—a determination made based on various factors including, for example and without limitation the relative page warmth, access-count thresholding (comparing remote-page access counts against a programmed and/or heuristically adjusted access-count threshold), page migration history (e.g., factoring recent migration of page 0x0D against its non-access during time interval t2) and so forth” (par. 0034). Roberts teaches “[0043]…Processing the counter values can include generating a sorted list of page addresses by access count, which the host system 120 can then use in page scheduling to move frequently accessed pages to fast memory.” “[0055]… The higher-level telemetry post-processing function can include, for example, receiving a sorted and unsorted segment access frequency histogram, receiving a segment schedule using a scheduling policy (e.g., a page schedule that lists blocks to migrate to each memory type),” “[0087]… [0087] A page scheduling technique can involve relocating heavily accessed segments (i.e., segments for which the access counter value exceeds a threshold value) to faster memory devices to improve the overall performance of the memory sub-system. In some embodiments, page scheduling can include generating lists of the moveable segments, and ordering the list in order of access frequency or access counter value”].
18. The system of claim 17, wherein the list comprises one or more most requested pages stored in the far memory [The rationale in the rejection of claim 17 is herein incorporated].
19. The system of claim 17, wherein a number of pages in the list is based on the capacity of the directory [Erickson teaches “ In some implementations, for example, the memory virtualizer maintains an LPA-indexed list of pages undergoing migration (e.g., as a bit field within an address translation table, access statistics table, and/or dedicated “active-migration” lookup table) and affirmatively delays access requests directed LPAs for which migration is indicated (by table lookup) to be under way” (par. 0030) where the number of pages in the list corresponds to the size of the corresponding structure, i.e., the bit field within an address translation table, access statistics table, and/or dedicated “active-migration” lookup table. Roberts teaches “[0043]…Processing the counter values can include generating a sorted list of page addresses by access count, which the host system 120 can then use in page scheduling to move frequently accessed pages to fast memory.” “[0055]… The higher-level telemetry post-processing function can include, for example, receiving a sorted and unsorted segment access frequency histogram, receiving a segment schedule using a scheduling policy (e.g., a page schedule that lists blocks to migrate to each memory type),” “[0087]… [0087] A page scheduling technique can involve relocating heavily accessed segments (i.e., segments for which the access counter value exceeds a threshold value) to faster memory devices to improve the overall performance of the memory sub-system. In some embodiments, page scheduling can include generating lists of the moveable segments, and ordering the list in order of access frequency or access counter value” where the number of pages in the list corresponds to the capacity of the list or number of counters monitored].
20. The system of claim 1, wherein the one or more computing processors are configured to: identify pages in the directory for which the access count exceeds an access threshold; and move the identified pages from the far memory to the near memory [Erickson teaches “After the collection interval transpires, the collected statistics are evaluated to identify the most accessed pages and up-migrate those relatively warm pages from remote to local memory (307) and, optionally, to identify the least accessed pages and further down-migrate those relatively cold pages to more-latent remote memory (309).” (par. 0032; fig. 6 and elated text) “the access bits and access counters for local and remote memory pages, respectively, are analyzed/evaluated, leading to selection of a relatively cold local memory page for down-migration (local page 0x01 for which access bit shows no-access during t0) and selection of a relatively warm remote memory page (remote page 0x0D having maximum access count within the exemplary four-page group) for up-migration” (par. 0033; fig. 7 and related text) “[0038] Concurrently with history-data-adjustment of the remote page access counts (i.e., operations at 415 and 417), the accessed/not-accessed bit within all local-page PTEs are read out (421) and used to increment or decrement the backing-store counters 402 according to bit state (423, 425, 427). At 431, the access counts within the backing-store and cache counters (low-resolution and high-resolution access counts) are analyzed to identify up-migration and/or down-migration targets, followed by cache-counter reset 433 and autonomous or OS-assisted migration of those target pages (435) before proceeding with another reset/collection/migration loop.” (see par. 0034; fig. 7 and related text). Roberts teaches “[0022] Advantages of the present disclosure include, but are not limited to, generating and providing an accurate, system-wide view of memory behavior, thus enabling more accurate memory management capability. For example, an accurate system-wide view of memory behavior improves data placement throughout the entire computing system. Furthermore, improved data placement leads to improved overall performance of the memory sub-system. For example, overall performance of the memory sub-system can be improved by moving frequently accessed data to fast memory devices, and moving infrequently accessed data to slow memory devices.” “[0043]… Processing the counter values can include generating a sorted list of page addresses by access count, which the host system 120 can then use in page scheduling to move frequently accessed pages to fast memory.” “[0044]… As another example, the memory access monitoring component 113 can optimize data placement for an application running on host system 120, by analyzing the access frequency for the application data and moving frequently accessed data to faster memory devices. The memory management schemes, which can be implemented by the host system 120 and/or the memory access monitoring component 113, can include page scheduling techniques, application optimization techniques, security monitoring techniques, virtual machine provisioning techniques, and/or cache sizing techniques, for example.” Duluk teaches “[0021] In addition, the cache tracker may include a threshold value, where the access tracker indicates when a counter has reached the threshold value, such as by setting a flag or causing a trap or interrupt to occur. When a counter reaches a threshold value, the associated memory page is being frequently accessed by the GPU. The CPU or the GPU may respond by migrating the associated memory page from the CPU memory system to the GPU memory system. Cache entries may be preset, allowing the access tracker to monitor specific predefined memory pages. In some embodiments, the access tracker may maintain a list of barred memory pages that may not be allocated to a cache entry.”].
21. The system of claim 1, wherein the one or more telemetry processors are further configured to: receive a second page access request from the one or more computing processors; parse the second page access request; and query the directory to determine that the directory does not contain a record associated with the second requested page [Erickson teaches “page allocation engine 180 allocates and initializes access-statistics data structures 185, for example, by allocating one or more fields within page tables and TLBs for counter storage, allocating a counting elements within a hardware counter, etc. … incrementing an access count for each access to a corresponding memory page (or group of memory pages) within a given interval, with optional inclusion of historical data from prior intervals” (par. 0026) “the LPA is used to index an access counter and increment or otherwise update the indexed counter as shown at 215.” (par. 0027) “[0028] FIG. 4 illustrates a more detailed embodiment of an LPA-indexed page table 231 and corresponding LPA-indexed translation lookaside buffer 233 having address, cross-fabric and access-count fields (FA/MVPA, X, AC, respectively) organized in a per-entry address/counter tuple 235”. Note that since access-statistics data structures may be initialized or counters incremented if already present, it is effectively determined whether the data structures contain a record for the requested page. (see figs. 8 and 9 and related text). Duluk teaches “[0093]… When the access tracking unit 220 detects such a memory access operation, the access tracking unit 220 extracts the page number of the memory access operation, where the page number typically includes the leftmost bits of the memory address associated with the memory access operation. The access tracking unit 220 records the page numbers associated with such memory access operations with a reference count that indicates the number of times each shared memory page was accessed by the PPU 202. The access tracking unit 220 stores these page numbers, along with related information, in the access cache memory 230, as further described herein.” “[0098] If the access tracking unit 220 detects a memory access operation from the PPU 202 directed to a shared memory page in system memory 104, then the access tracking unit 220 determines whether the access cache memory 230 includes a valid access cache entry corresponding to the accessed memory page. If a valid entry exists for the accessed memory page, then the access tracking unit 220 increments the reference count in the access cache entry. If a valid entry does not exist for the accessed memory page (thus, the directory not containing a record for the associated page), then the access tracking unit 220 selects an unused cache access entry, and stores the page number in the unused entry. The access tracking unit the initializes the reference count for the unused cache access entry and sets the corresponding valid bit.”].
22. The system of claim 21, wherein the one or more telemetry processors are further configured to, in response to determining that the directory does not contain the record associated with the second requested page, add the record associated with the second requested page to the directory [Erickson teaches “page allocation engine 180 allocates and initializes access-statistics data structures 185, for example, by allocating one or more fields within page tables and TLBs for counter storage, allocating a counting elements within a hardware counter, etc. … incrementing an access count for each access to a corresponding memory page (or group of memory pages) within a given interval, with optional inclusion of historical data from prior intervals” (par. 0026) “the LPA is used to index an access counter and increment or otherwise update the indexed counter as shown at 215.” (par. 0027) “[0028] FIG. 4 illustrates a more detailed embodiment of an LPA-indexed page table 231 and corresponding LPA-indexed translation lookaside buffer 233 having address, cross-fabric and access-count fields (FA/MVPA, X, AC, respectively) organized in a per-entry address/counter tuple 235”. Note that since access-statistics data structures may be initialized or counters incremented if already present, it is effectively determined whether the data structures contain a record for the requested page. (see figs. 8 and 9 and related text) and adds/allocates a record. Duluk teaches “[0093]… When the access tracking unit 220 detects such a memory access operation, the access tracking unit 220 extracts the page number of the memory access operation, where the page number typically includes the leftmost bits of the memory address associated with the memory access operation. The access tracking unit 220 records the page numbers associated with such memory access operations with a reference count that indicates the number of times each shared memory page was accessed by the PPU 202. The access tracking unit 220 stores these page numbers, along with related information, in the access cache memory 230, as further described herein.” “[0098] If the access tracking unit 220 detects a memory access operation from the PPU 202 directed to a shared memory page in system memory 104, then the access tracking unit 220 determines whether the access cache memory 230 includes a valid access cache entry corresponding to the accessed memory page. If a valid entry exists for the accessed memory page, then the access tracking unit 220 increments the reference count in the access cache entry. If a valid entry does not exist for the accessed memory page (thus, the directory not containing a record for the associated page), then the access tracking unit 220 selects an unused cache access entry, and stores the page number in the unused entry (thus, adding a record for the associated page). The access tracking unit the initializes the reference count for the unused cache access entry and sets the corresponding valid bit.”].
23. The system of claim 22, wherein the one or more telemetry processors are further configured to transmit a signal to the one or more computing processors indicating the record associated with the second requested page has been added to the directory [Roberts teaches “[0018]… That is, if the host system accesses the line (e.g., by issuing a read or a write request referencing the line), it sends an access notification to the current owner of the line. Following the receipt of an access notification, the memory sub-system controller increases the counter associated with the segment, and releases ownership of the line. The memory sub-system controller can then request ownership of another line of the segment in order to monitor a consistent number of lines of each segment at once. While the memory sub-system controller can monitor any number of lines of each segment, the number of lines monitored should remain consistent.” “[0020] The memory sub-system controller can then transmit the access counter values to the host system.” (see fig. 5 and related text) where “ At operation 530, the processing logic increases a value of an access counter associated with the segment.” (par. 0092) and at operation 560, the value of the access counter is transmitted to the host. Duluk teaches “[0097] The second OS operation is a read count values command that causes the access tracking unit 220 to transmit the contents of the valid access cache entries in the access cache memory 230 to the requester. Alternatively, the access tracking unit 220 transmits the contents of all access cache entries in the access cache memory 230 to the requester. For example, if the access cache memory 230 includes sixteen entries, where each entry includes eight bytes per entry, then the returned data would be 128 bytes of data. The transmitted access cache entries include accumulated tracking data from the access cache memory 230 since the most recent initialize command…” where once unused entries are associated with memory page, they are initialized in step 420; see figs. 4A and 4B and related text. Thus, also transmitting entries that have been added to the directory to the requester].
24. The system of claim 22, wherein the one or more telemetry processors are further configured to add the record associated with the second requested page to the directory based on determining the directory is not at capacity [Duluk teaches “[0098]… If a valid entry exists for the accessed memory page, then the access tracking unit 220 increments the reference count in the access cache entry. If a valid entry does not exist for the accessed memory page, then the access tracking unit 220 selects an unused cache access entry, and stores the page number in the unused entry. The access tracking unit the initializes the reference count for the unused cache access entry and sets the corresponding valid bit.” “[0116] Returning to step 408, if the access cache memory 230 does not include a valid access cache entry for the accessed memory page, then the method 400 proceeds to step 412, where the access tracking unit 220 determines whether the access cache memory 230 includes an unused access cache entry. An unused access cache entry may be indicated by an access cache entry with a cleared valid bit. If the access cache memory 230 does not include an unused access cache entry, then the method 400 proceeds to step 414, where the access tracking unit 220 selects a valid cache entry in the access cache memory 230 to evict. The valid access cache entry may be selected using any technically feasible method, including, without limitation, an access cache entry with the lowest reference count, a randomly selected access cache entry, or an access cache entry selected on a round robin basis. Alternatively, the access tracking unit 220 may evict no access cache entries. In this latter case, accesses to the memory page corresponding to the current memory access operation are not tracked.” Where available unused entries correspond to the directory not being at capacity].
25. The system of claim 21, wherein the one or more telemetry processors are further configured to, in response to determining that the directory does not contain the record associated with the second requested page, discard the second page access request [Duluk teaches “[0116] Returning to step 408, if the access cache memory 230 does not include a valid access cache entry for the accessed memory page, then the method 400 proceeds to step 412, where the access tracking unit 220 determines whether the access cache memory 230 includes an unused access cache entry. An unused access cache entry may be indicated by an access cache entry with a cleared valid bit. If the access cache memory 230 does not include an unused access cache entry, then the method 400 proceeds to step 414, where the access tracking unit 220 selects a valid cache entry in the access cache memory 230 to evict. The valid access cache entry may be selected using any technically feasible method, including, without limitation, an access cache entry with the lowest reference count, a randomly selected access cache entry, or an access cache entry selected on a round robin basis. Alternatively, the access tracking unit 220 may evict no access cache entries. In this latter case, accesses to the memory page corresponding to the current memory access operation are not tracked.”], where accesses that are not tracked in the cache/directory are effectively3 discarded.
26. The system of claim 25, wherein the one or more telemetry processors are further configured to discard the second page access request based on determining the directory is at capacity [The rationale in the rejection of claim 25 is herein incorporated].
27. A method for managing pages in memory comprising: receiving, by one or more telemetry processors, a page access request from the one or more computing processors, the one or more computing processors having near memory and being coupled to far memory; parsing, by the one or more telemetry processors, the page access request by: identifying a memory address associated with the requested page; identifying a page size of the requested page; determining a number of upper bits and lower bits of the memory address based on the page size; reducing the memory address into the upper bits and lower bits, wherein the lower bits are offset bits; and removing the offset bits from the memory address to generate a subset of bits that identify the requested page; querying, by the one or more telemetry processors, a directory using the subset of bits to determine that the directory contains a record associated with the requested page; the directory comprising a bitmap having a maximum number of bits corresponding to a capacity of the directory, wherein each bit of the bitmap corresponds to a different page stored in the far memory and the capacity of the directory corresponds to a capacity of pages maintained by the directory; and in response to determining that the directory contains the record associated with the requested page, incrementing, by the one or more telemetry processors, an access count associated with the requested page [The rationale in the rejection of claim 1 is herein incorporated].
28. A non-transitory computer readable medium storing instructions that, when executed by one or more telemetry processors, cause the one or more telemetry processors to perform a method for managing pages in memory, the method comprising: receiving a page access request from one or more computing processors, the one or more computing processors having near memory and being coupled to far memory; parsing the page access request by: identifying a memory address associated with the requested page; identifying a page size of the requested page; determining a number of upper bits and lower bits of the memory address based on the page size; reducing the memory address into the upper bits and lower bits, wherein the lower bits are offset bits; and removing the offset bits from the memory address to generate a subset of bits that identify the requested page; querying a directory using the subset of bits to determine that the directory contains a record associated with the requested page; the directory comprising a bitmap having a maximum number of bits corresponding to a capacity of the directory, wherein each bit of the bitmap corresponds to a different page stored in the far memory and the capacity of the directory corresponds to a capacity of pages maintained by the directory; and in response to determining that the directory contains the record associated with the requested page, incrementing an access count associated with the requested page [The rationale in the rejection of claim 1 is herein incorporated].
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Erickson (US 2022/0179799) in view of Roberts (US 20240070072), Koufaty et al. (US 11,526,290), Duluk, Jr. et al. (US 2014/0281110) and Jin et al. (US 2025/0208996), Continuation of PCT/CN2023/010381, filed on Jun. 29, 2023, with Foreign Priority To claims foreign priority to CN 202211431336.4, filed 11/14/2022 and CN 202211180232.0, filed 09/26/2022; as applied in the rejection of claim 1 above, and further in view of Abhishek Raja (US 2019/0294551).
6. The system of claim 1, wherein the directory is a table comprising the first subset of bits, the page size and the access count [Erickson teaches access statistics include page addresses and access counts (see figs. 6-10 and related text). Roberts teaches “[0043]… Processing the counter values can include generating a sorted list of page addresses by access count, which the host system 120 can then use in page scheduling to move frequently accessed pages to fast memory.” Koufaty teaches access counts recorded for each page entry 510 in attribute table (fig. 5 and related text). Duluk teaches cache 300 recording the page number 330 which corresponds to the claimed subset of bits as well as reference count (fig. 3 and related text) where Duluk explains “[0105] The page number field 330 is associated with the memory address of the first location of the corresponding shared memory page. Typically, the page number is the leftmost portion of the memory address specified by the memory access operation. For example, if memory addresses directed to shared memory are 48-bits wide and each shared memory page is 2.sup.16 or 64 k bytes long, then the page number would be the leftmost 32 bits of the memory address. In another example, if a shared memory address includes 40 bits, and the page size is 4 kB (12 bits of address space), then the page frame would include 40-12=28 bits. In yet another example, if a physical address includes 42 bits, and the page size is 4 kB (12 bits of address space), then the page number would include 42-12=30 bits.”] but the combination of Erickson, Roberts, Koufaty and Duluk does not expressly disclose the table also recording the page size; however, regarding these limitations, Abhishek Raja teaches a table including memory page information such as page size info 315 (fig. 5 and related text).
Erickson, Roberts, Koufaty, Duluk, Jin and Abhishek Raja are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Erickson, Roberts, Koufaty, Duluk and Jin to include page size information in the directory/tracking data structure of the combination as taught by Abhishek since doing so would facilitate page address translations.
Therefore, it would have been obvious to combine Erickson, Roberts, Koufaty, Duluk, Jin and Abhishek Raja for the benefit of creating a storage system/method to obtain the invention as specified in claim 6.
ACKNOWLEDGEMENT OF ISSUES RAISED BY APPLICANT
Response to Amendment
Applicant's arguments filed on 12/1/2025 have been fully considered but are moot in view of new grounds of rejection.
CLOSING COMMENTS
a. STATUS OF CLAIMS IN THE APPLICATION
a(1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-2, 6-7, 15, 17-28 have received a first action on the merits and are subject to a final rejection.
a(2) CLAIMS NO LONGER UNDER CONSIDERATION
Claims 3-5, 8-14 and 16 have been canceled.
b. DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YAIMA RIGOL whose telephone number is (571)272-1232. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared I. Rutz can be reached on (571) 272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
January 16, 2026
/YAIMA RIGOL/
Primary Examiner, Art Unit 2135