DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 and 12-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsujimoto (US 5,524,023).
In regard to Claim 1:
Tsujimoto discloses, in Figure 4, a logarithmic amplifier system, comprising:
first (403) and second (404) amplifiers, the first amplifier having a first gain (Column 9: lines 3-8), and the second amplifier having a second gain (Column 9: lines 19-24);
a first multiplier (405) having an input connected to an output of the first amplifier (403), and being configured to output a first multiplied signal (405 output) based on an output signal of the first amplifier (403 output) and based on a received first multiplication factor equal to a value K (Column 9: lines 46-52);
a second multiplier (407) having an input connected to an output of the second amplifier (404), and being configured to output a second multiplied signal (407 output) based on an output signal of the second amplifier (404 output) and based on a received second multiplication factor equal to 1 minus the value K (Column 9: lines 46-52);
a transition shaping circuit (406, 408) configured to generate the value K, wherein the transition shaping circuit is configured to change the value K from 0 to 1 with a filtered transfer function (Column 9: lines 46-52); and
a summing circuit (409) having inputs coupled to outputs of the first multiplier (405) and the second multiplier (407).
In regard to Claim 2:
Tsujimoto discloses, in Figure 4, the logarithmic amplifier system of claim 1, wherein the transition shaping circuit is configured to change the value K in response to a trigger signal (416 output) generated based on one or more characteristics of an analog signal at an input of the first amplifier (403) or generated based on one or more characteristics of a digitized version of the analog signal at the input of the first amplifier (Column 9: lines 41-55).
In regard to Claim 3:
Tsujimoto discloses, in Figure 4, the logarithmic amplifier system of claim 2, wherein the transition shaping circuit (406, 408) is configured to change the value K in response to a filtered version of the trigger signal (416 output filtered through 421 and fed back to 416).
In regard to Claim 4:
Tsujimoto discloses, in Figure 4, the logarithmic amplifier system of claim 3, wherein the transition shaping circuit (406, 408) is configured to change the value K using a digital processor (410) configured to process the filtered version of the trigger signal (416 output filtered through 421 and fed back to 416 and 410).
In regard to Claim 12:
Tsujimoto discloses, in Figure 4, a method of using a logarithmic amplifier system, the method comprising:
generating (403) a first amplified signal (403 output) based on an analog input (input to 403) and based on a first gain (Column 9: lines 3-8);
generating (404) a second amplified signal (404 output) based on the analog input (input to 404) and based on a second gain (Column 9: lines 19-24);
generating (405) a first multiplied signal (405 output) based on the first amplified signal (403 output) and based on a first multiplication factor equal to a value K (Column 9: lines 46-52);
generating (407) a second multiplied signal (407 output) based on the second amplified signal (404 output) and based on a second multiplication factor equal to 1 minus the value K (Column 9: lines 46-52);
changing (406, 408) the value K from 0 to 1 with a filtered transfer function (Column 9: lines 46-52); and
generating (409) an analog output signal by summing the first (405 output) and second (407 output) multiplied signals.
In regard to Claim 13:
Tsujimoto discloses, in Figure 4, the method of claim 12, further comprising changing the value K in response to a trigger signal (416 output) generated based on one or more characteristics of the analog input (403, 404 input) or generated based on one or more characteristics of a digitized version of the analog input (Column 9: lines 41-55).
In regard to Claim 14:
Tsujimoto discloses, in Figure 4, the method of claim 13, further comprising changing the value K in response to a filtered version of the trigger signal (416 output filtered through 421 and fed back to 416).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsujimoto (US 5,524,023), in view of Kornfeld et al. (US 5,758,266).
In regard to Claim 7:
All of the claim limitations have been discussed with respect to Claim 1 above, except for wherein the first and second amplifiers have inputs connected to a same analog signal input.
Kornfeld discloses, in Figure 1, wherein the first (120) and second amplifiers (125) have inputs connected to a same analog signal input (101).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the same analog input taught by Kornfeld with the first and second amplifiers taught by Tsujimoto, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsujimoto (US 5,524,023), in view of Hanks et al. (US 2019/0288737).
In regard to Claim 9:
All of the claim limitations have been discussed with respect to Claim 1 above, except for further comprising an analog-to-digital converter (ADC) configured to generate a digital representation of an analog output signal from the summing circuit.
Hanks discloses, in Figure 16, further comprising an analog-to-digital converter (ADC) (1622) configured to generate a digital representation of an analog output signal (¶ 0118) from the summing circuit (409 taught by Tsujimoto discussed above).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the ADC taught by Hanks with the summing circuit taught by Tsujimoto, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385).
Claim(s) 15-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsujimoto (US 5,524,023), in view of Chang (US 2012/0319885).
In regard to Claim 15:
Tsujimoto discloses, in Figure 4, a digital microphone, comprising:
a logarithmic amplifier system, comprising:
first (403) and second (404) amplifiers, the first amplifier having a first gain (Column 9: lines 3-8), and the second amplifier having a second gain (Column 9: lines 19-24);
a first multiplier (405) having an input connected to an output of the first amplifier (403), and being configured to output a first multiplied signal (405 output) based on an output signal of the first amplifier (403 output) and based on a received first multiplication factor equal to a value K (Column 9: lines 46-52);
a second multiplier (407) having an input connected to an output of the second amplifier (404), and being configured to output a second multiplied signal (407 output) based on an output signal of the second amplifier (404 output) and based on a received second multiplication factor equal to 1 minus the value K (Column 9: lines 46-52);
a transition shaping circuit (406, 408) configured to generate the value K, wherein the transition shaping circuit is configured to change the value K from 0 to 1 with a filtered transfer function (Column 9: lines 46-52); and
a summing circuit (409) having inputs coupled to outputs of the first multiplier (405) and the second multiplier (407).
Tsujimoto does not disclose a MEMS device configured to generate an analog signal.
Chang discloses a MEMS device configured to generate an analog signal (¶ 0168: lines 9-17).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the MEMS device to generate the analog signal taught by Chang with the logarithmic amplifier system taught by Tsujimoto, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385).
In reard to Claim 16:
All of the claim limitations have been discussed with respect to Claim 15 above, except for wherein the transition shaping circuit is configured to change the value K in response to a trigger signal generated based on one or more characteristics of an analog signal at an input of the first amplifier or generated based on one or more characteristics of a digitized version of the analog signal at the input of the first amplifier.
Tsujimoto further discloses, in Figure 4, wherein the transition shaping circuit is configured to change the value K in response to a trigger signal (416 output) generated based on one or more characteristics of an analog signal at an input of the first amplifier (403) or generated based on one or more characteristics of a digitized version of the analog signal at the input of the first amplifier (Column 9: lines 41-55).
In regard to Claim 17:
All of the claim limitations have been discussed with respect to Claims 15-16 above, except for wherein the transition shaping circuit is configured to change the value K in response to a filtered version of the trigger signal.
Tsujimoto further discloses, in Figure 4, wherein the transition shaping circuit (406, 408) is configured to change the value K in response to a filtered version of the trigger signal (416 output filtered through 421 and fed back to 416).
In regard to Claim 18:
All of the claim limitations have been discussed with respect to Claims 15-17 above, except for wherein the transition shaping circuit is configured to change the value K using a digital processor configured to process the filtered version of the trigger signal.
Tsujimoto further discloses, in Figure 4, wherein the transition shaping circuit (406, 408) is configured to change the value K using a digital processor (410) configured to process the filtered version of the trigger signal (416 output filtered through 421 and fed back to 416 and 410).
Allowable Subject Matter
Claims 5-6, 8, 10-11, and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
In regard to Claim 5:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
wherein the transition shaping circuit is configured to change the value K from a first of a minimum and a maximum to the other of the minimum or maximum strictly monotonically, and wherein the transition shaping circuit is configured to change the value K from the other of the minimum or maximum to the first of the minimum and the maximum by changing the value K from the other of the minimum or maximum to a midpoint value between the minimum and the maximum, and to subsequently change the value K from the midpoint value to the first of the minimum and the maximum.
In regard to Claim 6:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
wherein the transition shaping circuit is configured to change the value K from one of a minimum and a maximum to a midpoint value between the minimum and the maximum, and to subsequently change the value K from the midpoint value to the one of the minimum and the maximum.
In regard to Claim 8:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
wherein the second amplifier has an input connected to an output connection of the first amplifier.
In regard to Claim 10:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
further comprising: an offset summing circuit; and an offset register, wherein the offset summing circuit is configured to generate an offset calibrated analog output signal based on the digital representation of the analog output signal and based on one or more offset values received from the offset register, and wherein the offset values are determined based on an offset calibration routine.
In regard to Claim 19:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
wherein the transition shaping circuit is configured to change the value K from a first of a minimum and a maximum to the other of the minimum or maximum strictly monotonically, and wherein the transition shaping circuit is configured to change the value K from the other of the minimum or maximum to the first of the minimum and the maximum by changing the value K from the other of the minimum or maximum to a midpoint value between the minimum and the maximum, and to subsequently change the value K from the midpoint value to the first of the minimum and the maximum.
In regard to Claim 20:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
wherein the transition shaping circuit is configured to change the value K from one of a minimum and a maximum to a midpoint value between the minimum and the maximum, and to subsequently change the value K from the midpoint value to the one of the minimum and the maximum.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nash (US 2004/0223349) discloses a system that includes a variable gain amplifier having transfer function ripple that receives an input signal and provides an amplifier output signal, a detector that receives the amplifier output signal and provides a detector output signal, an error amplifier that receives the detector output signal and provides an error amplifier output signal having an AC component, and a feedback circuit coupled to the error amplifier output signal and to the variable gain amplifier for providing a feedback signal to the variable gain amplifier that includes an AC component for reducing transfer function ripple of the RMS-to-DC converter system.
Tsujimoto (US 5,349,609) discloses an interference canceler comprises an adaptive equalizer, first and second diversity branches, and an auxiliary branch. A first correlator detects a correlation between the output of the equalizer and the output of the first diversity branch, and a second correlator detects a correlation between the equalizer output and the output of the second diversity branch. The first and second diversity branch signals are multiplied with the detected first and second correlations, respectively, and diversity combined.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to John W Poos whose telephone number is (571)270-5077. The examiner can normally be reached M-Th 8-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOHN W POOS/Primary Examiner, Art Unit 2843
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