DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-4 and 10-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
For claim 3, the recitation “a second cycle has the first period and the second period” (emphasis added), on lines 1-2, is indefinite. It is unclear whether the “second cycle” of claim 3 and “a first cycle” recited in line 11 of claim 1 are the same or difference because both the “second cycle” and the “first cycle” recitations have the same “the first period and the second period”. Appropriate correction and/or clarification is required.
Claim 4 is rejected due to its dependencies on the base claim 3.
For claim 10, the recitation “a second cycle has the first period and the second period” (emphasis added), on lines 1-2, is indefinite. It is unclear whether the “second cycle” of claim 10 and “a first cycle” recited in line 25 of claim 7 are the same or difference because both the “second cycle” and the “first cycle” recitations have the same “the first period and the second period”. Appropriate correction and/or clarification is required.
Claim 11-12 are rejected due to their dependencies on the base claim 10.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7-12 and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Mizukami et al. (hereinafter Mizukami, US 2023/0073943 A1) in view of Giordano (US 5,642,247 A).
For claim 1, Mizukami discloses a driver circuit for a switching circuit, wherein the switching circuit is configured to drive a motor (Figs. 1-2 of Mizukami disclose a driver circuit (13,23) for a switching circuit (11,12,21,22), wherein the switching circuit (11,12,21,22) is configured to drive a motor 2 – see Mizukami, Figs. 1-2, paragraphs [0019]-[0022], [0054]-[0057] and [0059]-[0061]), and the driver circuit comprises:
a pulse width modulation terminal configured to receive a PWM signal (Figs. 1-2 of Mizukami disclose a pulse width modulation terminal (10e, 20e) configured to receive a PWM signal (PWM1, PWM1) from controller 60 – see Mizukami, Figs. 1-2, paragraphs [0040]-[0042]);
a first gate control terminal configured to provide a first control signal (Fig. 2 of Mizukami discloses a first gate control terminal at output of first gate control circuit 13 connected to gate of switch 11, wherein the first gate control terminal configured to provide a first control signal – see Mizukami, Fig. 2, paragraphs [0054]-[0055]);
a second gate control terminal configured to provide a second control signal (Fig. 2 of Mizukami discloses a second gate control terminal at output of first gate control circuit 13 connected to gate of switch 12, wherein the first gate control terminal configured to provide a first control signal – see Mizukami, Fig. 2, paragraphs [0054] and [0056]);
a third gate control terminal configured to provide a third control signal (Fig. 2 of Mizukami discloses a third gate control terminal at output of second gate control circuit 23 connected to gate of switch 21, wherein the third gate control terminal configured to provide a third control signal – see Mizukami, Fig. 2, paragraphs [0059]-[0060]);
a fourth gate control terminal configured to provide a fourth control signal (Fig. 2 of Mizukami discloses a fourth gate control terminal at output of second gate control circuit 23 connected to gate of switch 22, wherein the fourth gate control terminal configured to provide a fourth control signal – see Mizukami, Fig. 2, paragraphs [0059] and [0061]);
a first output terminal coupled to a first terminal of the motor (Figs. 1-2 of Mizukami disclose a first output terminal 10a coupled to a first terminal of the motor 2 – see Mizukami, Figs. 1-2, paragraphs [0021], lines 1-3 and [0055]); and
a second output terminal coupled to a second terminal of the motor (Figs. 1-2 of Mizukami disclose a second output terminal 20a coupled to a second terminal of the motor 2 – see Mizukami, Figs. 1-2, paragraphs [0021], lines 3-5 and [0060]).
Mizukami discloses the PWM signal (PWM1, PWM2) which is a high logic level and/or a low logic level (see Mizukami, Fig. 2, paragraphs [0058], [0062] and [0066]). Mizukami is silent for disclosing a first cycle has a first period and a second period, the PWM signal is at a high logic level during the first period, and the PWM signal is at a low logic level during the second period.
However, Giordano discloses a motor control system (see Giordano, Fig. 1, col. 1, lines 11-24) which is similar as Mizukami’s motor control system. Giordano discloses a first cycle has a first period and a second period, the PWM signal is at a high logic level during the first period, and the PWM signal is at a low logic level during the second period (Figs. 1-3 of Giordano disclose a first cycle (For example, a cycle includes states S2 and S4 as shown in Fig. 3) has a first period (during state S2) and a second period (during state S4), the PWM signal is at a high logic level (for example, Fig. 3, Q1 is ON) during the first period (Fig. 3, during a state S4), and the PWM signal is at a low logic level (for example, Fig. 3, Q1 is OFF) during the second period (during a state S2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify teaching of Mizukami to incorporate teaching of Giordano for purpose of providing erroneous fault detection to be minimized in different operating conditions of the load during certain windows of time.
Mizukami in view of Giordano disclose the driver circuit,
wherein in a normal operation mode, during the first period of the first cycle, the first control signal and the fourth control signal are of a first voltage level and the second control signal and the third control signal are of a second voltage level, and during the second period of the first cycle, the second control signal and the fourth control signal are of the first voltage level and the first control signal and the third control signal are of the second voltage level (Fig. 2 of Mizukami in view of equivalent illustrated Fig. 3A below of Giordano disclose, in a normal operation mode (see Mizukami, Fig. 2, paragraphs [0064] and [0066]; and see Giordano, equivalent illustrated Fig. 3A below, during states S4, S2), during the first period (during period in state S4) of the first cycle (S4, S2), the first control signal and the fourth control signal are of a first voltage level (see equivalent Fig. 3A of Giordano) and the second control signal and the third control signal are of a second voltage level (see equivalent illustrated Fig. 3A of Giordano), and during the second period (during period in state S2) of the first cycle, the second control signal and the fourth control signal are of the first voltage level (see equivalent illustrated Fig. 3A of Giordano) and the first control signal and the third control signal are of the second voltage level (see equivalent illustrated Fig. 3A of Giordano) – see Mizukami, Fig. 2, paragraphs [0064] and [0066]; and see Giordano, equivalent illustrated Fig. 3A below, during states S4, S2);
wherein in a power loss mode (see Mizukami, Fig. 2, paragraph [0070]; and see Giordano, equivalent illustrated Fig. 3 below, during states S3, S1), during the first period (during period in state S3) of the first cycle, the second control signal and the third control signal are of the first voltage level and the first control signal and the fourth control signal are of the second voltage level (see equivalent illustrated Fig. 3 of Giordano), and during the second period (during period in state S1) of the first cycle, the second control signal and the fourth control signal are of the first voltage level and the first control signal and the third control signal are of the second voltage level (see equivalent illustrated Fig. 3A of Giordano) – see Mizukami, Fig. 2, paragraph [0070]; and see Giordano, equivalent illustrated Fig. 3 below, during states S3, S1).
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For claim 2, Mizukami in view of Giordano disclose the driver circuit of claim 1, wherein in the normal operation mode, during the first period of the first cycle, a voltage at the first output terminal is of a third voltage level and a voltage at the second output terminal is of a fourth voltage level, and during the second period of the first cycle, the voltage at the first output terminal and the voltage at the second output terminal are of the fourth voltage level (Fig. 2 and equivalent illustrated Fig. 3A of Giordano disclose in the normal operation mode (equivalent illustrated Fig. 3A above of Giordano indicates the normal operation mode during states S4, S2), during the first period (during period in state S4) of the first cycle, a voltage (OUT1) at the first output terminal 22 is of a third voltage level and a voltage (OUT2) at the second output terminal 24 is of a fourth voltage level, and during the second period (during period in state S2) of the first cycle, the voltage at the first output terminal and the voltage at the second output terminal are of the fourth voltage level -- see Giordano, Fig. 2 and equivalent illustrated Fig. 3 above, during states S4, S2);
wherein in the power loss mode, during the first period of the first cycle, the voltage at the first output terminal is of the fourth voltage level and the voltage at the second output terminal is of the third voltage level, and during the second period of the first cycle, the voltage at the first output terminal and the voltage at the second output terminal are of the fourth voltage level (Fig. 2 and equivalent illustrated Fig. 3A of Giordano disclose in the power loss mode (equivalent illustrated Fig. 3A above of Giordano indicates the power loss mode during states S3, S1), during the first period (during period in state S3) of the first cycle, the voltage (OUT1) at the first output terminal 22 is of the fourth voltage level (Low) and the voltage (OUT2) at the second output terminal 24 is of the third voltage level (High), and during the second period (during period in state S1) of the first cycle, the voltage (OUT1) at the first output terminal 22 and the voltage(OUT2) at the second output terminal 24 are of the fourth voltage level (Low) -- see Giordano, Fig. 2 and equivalent illustrated Fig. 3A above, during states S3, S1).
For claim 3, Mizukami in view of Giordano disclose the driver circuit of claim 1, wherein a second cycle has the first period and the second period (equivalent illustrated Fig. 3B below of Giordano disclose a second cycle has the first period (during period in state S3) and the second period (during period in state S1));
wherein in the normal operation mode, during the first period of the second cycle, the second control signal and the third control signal are of the first voltage level, and during the second period of the second cycle, the second control signal and the fourth control signal are of the first voltage level (Figs. 1-2 of Mizukami in view of equivalent illustrated Fig. 3B below of Giordano disclose, in the normal operation mode (see Mizukami, Figs. 12, paragraphs [0047]-[0048], [0058] and [0062]; and see Giordano, equivalent illustrated Fig. 3B below, during states S3, S1), during the first period (during period in state S3) of the second cycle (S3, S1), the second control signal Q2 and the third control signal Q3 are of the first voltage level (ON), and during the second period (during period in state S1) of the second cycle, the second control signal and the fourth control signal are of the first voltage level (ON) -- see Mizukami, Figs. 1-2, paragraphs ([0047], lines 1-5; [0048]; [0058], lines 1-12; and [0062], lines 1-13); and see Giordano, equivalent illustrated Fig. 3B below, during states S3, S1);
wherein in the power loss mode, during the first period of the second cycle, the first control signal and the fourth control signal are of the first voltage level, during the second period of the second cycle, the second control signal and the fourth control signal are of the first voltage level (Figs. 1-2 of Mizukami in view of equivalent illustrated Fig. 3B below of Giordano disclose in the power loss mode, during the first period (during period in state S4) of the second cycle (S4, S2), the first control signal and the fourth control signal are of the first voltage level (ON), during the second period (during period in state S2) of the second cycle (S4,S2), the second control signal and the fourth control signal are of the first voltage level (ON) -- see Mizukami, Figs. 1-2, ([0047], lines 5-11; [0049]; [0058], lines 12-18; and [0062], lines 13-19); and see Giordano, equivalent illustrated Fig. 3B below, during states S4, S2).
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For claim 4, Mizukami in view of Giordano disclose the driver circuit of claim 3, wherein in the normal operation mode, during the first period of the second cycle, a voltage at the first output terminal is of a fourth voltage level and a voltage at the second output terminal is of a third voltage level, and during the second period of the second cycle, the voltage at the first output terminal and the voltage at the second output terminal are of the fourth voltage level (Fig. 2 and equivalent illustrated Fig. 3B above of Giordano disclose, in the normal operation mode (equivalent illustrated Fig. 3B above of Giordano indicates the normal operation mode during states S3,S1), during the first period (during period in state S3) of the second cycle, a voltage (OUT1) at the first output terminal 22 is of a fourth voltage level (Low) and a voltage(OUT2) at the second output terminal 24 is of a third voltage level (High), and during the second period (during period in state S1) of the second cycle, the voltage (OUT1) at the first output terminal 22 and the voltage (OUT2) at the second output terminal 24 are of the fourth voltage level (Low) -- see Giordano, Fig. 2 and equivalent illustrated Fig. 3B above, during states S3, S1);
wherein in the power loss mode, during the first period of the second cycle, the voltage at the first output terminal is of the third voltage level and the voltage at the second output terminal is of the fourth voltage level, and during the second period of the second cycle, the voltage at the first output terminal and the voltage at the second output terminal are of the fourth voltage level (Fig. 2 and equivalent illustrated Fig. 3B above of Giordano disclose, in the power loss mode (equivalent illustrated Fig. 3B above of Giordano indicates the power loss mode during states S4, S2), during the first period (during period in state S4) of the second cycle, the voltage (OUT1) at the first output terminal 22 is of the third voltage level (High) and the voltage (OUT2) at the second output terminal 24 is of the fourth voltage level (Low), and during the second period (during period in state S2) of the second cycle, the voltage (OUT1) at the first output terminal 22 and the voltage (OUT2) at the second output terminal 24 are of the fourth voltage level (Low) -- see Giordano, Fig. 2 and equivalent illustrated Fig. 3B above, during states S4, S2).
For claim 7, Mizukami discloses a driving circuit for a motor (Figs. 1-2 of Mizukami disclose a driver circuit (10,20) for a motor 2 – see Mizukami, Figs. 1-2, paragraphs [0019]-[0022], [0054.-[0057] and [0059]-[0061])), the driving circuit (10, 20) comprising:
a first switch having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first switch is configured to receive an input voltage (Fig. 2 of Mizukami discloses a first switch 11 having a first terminal 10b, a second terminal 10a, and a control terminal at gate G of the first switch 11, wherein the first terminal 10b of the first switch 11 is configured to receive an input voltage P1 – see Mizukami, Fig. 2, paragraph [0055]);
a second switch having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second switch is coupled to the second terminal of the first switch, and the second terminal of the second switch is configured to be coupled to a ground (Fig. 2 of Mizukami discloses a second switch 12 having a first terminal 10a, a second terminal 10c, and a control terminal at gate G of switch 12, wherein the first terminal 10a of the second switch 12 is coupled to the second terminal 10a of the first switch 11, and the second terminal 10c of the second switch 12 is configured to be coupled to a ground GND via resistor 31 – see Mizukami, Fig. 2, paragraph [0056]);
a third switch having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the third switch is configured to receive the input voltage (Fig. 2 of Mizukami discloses a third switch 21 having a first terminal 20b, a second terminal 20a, and a control terminal at gat G of third switch 21, wherein the first terminal 20b of the third switch 21 is configured to receive the input voltage P1 -- see Mizukami, Fig. 2, paragraph [0060]);
a fourth switch having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the fourth switch is coupled to the second terminal of the third switch, and the second terminal of the fourth switch is configured to be coupled to the ground (Fig. 2 of Mizukami discloses a fourth switch 22 having a first terminal 20a, a second terminal 20c, and a control terminal at gate G of fourth switch 22, wherein the first terminal 20a of the fourth switch 22 is coupled to the second terminal 20a of the third switch 21, and the second terminal 20c of the fourth switch 22 is configured to be coupled to the ground GND via resistor 31 -- see Mizukami, Fig. 2, paragraph [0061]);
a driving control circuit configured to provide, in response to a PWM signal, a first control signal to the control terminal of the first switch, a second control signal to the control terminal of the second switch, a third control signal to the control terminal of the third switch, and a fourth control signal to the control terminal of the fourth switch (Figs. 1-2 of Mizukami disclose a driver control circuit (13,23) configured to provide, in response to a PWM signal (PWM1, PWM2), a first control signal to the control terminal of the first switch 11, a second control signal to the control terminal of the second switch 12, a third control signal to the control terminal of the third switch 21, and a fourth control signal to the control terminal of the fourth switch 22 – see Mizukami, Figs. 1-2, paragraphs [0022], [0054]-[0057] and [0059]-[0061]);
a first output terminal coupled to the second terminal of the first switch, the first terminal of the second switch, and a first terminal of the motor (Fig. 2 of Mizukami discloses a first output terminal 10a coupled to the second terminal 10a of the first switch 11, the first terminal 10a of the second switch 12, and a first terminal 10a of the motor 2 – see Mizukami, Fig. 2, paragraphs [0021] and [0055]-[0056]); and
a second output terminal coupled to the second terminal of the third switch, the first terminal of the fourth switch, and a second terminal of the motor (Fig. 2 of Mizukami discloses a second output terminal 20a coupled to the second terminal 20a of the third switch 21, the first terminal 20a of the fourth switch 22, and a second terminal of the motor 2 – see Mizukami, Fig. 2, paragraphs [0021] and [0060]-[0061]).
Mizukami discloses the PWM signal (PWM1, PWM2) which is a high logic level and/or a low logic level (see Mizukami, Fig. 2, paragraphs [0058], [0062] and [0066]). Mizukami is silent for disclosing a first cycle has a first period and a second period, the PWM signal is at a high logic level during the first period, and the PWM signal is at a low logic level during the second period.
However, Giordano discloses a motor control system (see Giordano, Fig. 1, col. 1, lines 11-24) which is similar as Mizukami’s motor control system. Giordano discloses a first cycle has a first period and a second period, the PWM signal is at a high logic level during the first period, and the PWM signal is at a low logic level during the second period (Figs. 1-3 of Giordano disclose a first cycle (For example, a cycle includes states S2 and S4 as shown in Fig. 3) has a first period (during state S2) and a second period (during state S4), the PWM signal is at a high logic level (for example, Fig. 3, Q1 is ON) during the first period (Fig. 3, during a state S4), and the PWM signal is at a low logic level (for example, Fig. 3, Q1 is OFF) during the second period (during a state S2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify teaching of Mizukami to incorporate teaching of Giordano for purpose of providing erroneous fault detection to be minimized in different operating conditions of the load during certain windows of time.
Mizukami in view of Giordano disclose the driver circuit,
wherein in a normal operation mode, during the first period of the first cycle, the first switch and the fourth switch are turned on, and during the second period of the first cycle, the second switch and the fourth switch are turned on (Fig. 2 of Mizukami in view of equivalent illustrated Fig. 3A of Giordano disclose, in a normal operation mode (see Mizukami, Fig. 2, paragraphs [0064] and [0066]; and see Giordano, equivalent illustrated Fig. 3A above, during states S4, S2), during the first period (during period in state S4) of the first cycle (S4, S2), the first switch Q1 and the fourth switch Q4 are turned on, and during the second period (during period in state S2) of the first cycle, the second switch Q2 and the fourth switch Q4 are turned on – see Mizukami, Fig. 2, paragraphs [0064] and [0066]; and see Giordano, equivalent illustrated Fig. 3A above, during states S4, S2);
wherein in a power loss mode, during the first period of the first cycle, the second switch and the third switch are turned on, and during the second period of the first cycle, the second switch and the fourth switch are turned on (Fig. 2 of Mizukami in view of equivalent illustrated Fig. 3A of Giordano disclose, in a power loss mode (see Mizukami, Fig. 2, paragraph [0070]; and see Giordano, equivalent illustrated Fig. 3A above, during states S3, S1), during the first period (during period in state S3) of the first cycle, the second switch Q2 and the third switch Q3 are turned on, and during the second period (during period in state S1) of the first cycle, the second switch Q2 and the fourth switch Q4 are turned on (see equivalent illustrated Fig. 3A of Giordano) – see Mizukami, Fig. 2, paragraph [0070]; and see Giordano, equivalent illustrated Fig. 3 below, during states S3, S1).
For claim 8, Mizukami in view of Giordano disclose the driving circuit of claim 7, wherein in the power loss mode, during the first period of the first cycle, a current flowing through the second switch, flows from the first output terminal to the second output terminal through the motor, and through the third switch (Fig. 4 of Mizukami in view of equivalent illustrated Fig. 3A of Giordano disclose, in the power loss mode (see Mizukami, Fig. 2, paragraph [0070]; and see Giordano, equivalent illustrated Fig. 3A above, during states S3, S1), during the first period (during period in state S3) of the first cycle, a current flowing through the second switch 12, flows from the first output terminal 10a to the second output terminal 20a through the motor 2, and through the third switch 21 – see Mizukami, Fig. 4, paragraph [0073], lines 1-5; and see Giordano, equivalent illustrated Fig. 3 below, during states S3, S1).
For claim 9, Mizukami in view of Giordano disclose the driving circuit of claim 7, wherein in the power loss mode, during the second period of the first cycle, a current flowing through the fourth switch and through the second switch, flows from the first output terminal to the second output terminal through the motor (Fig. 2 and equivalent illustrated Fig. 3A of Giordano disclose in the power loss mode (equivalent illustrated Fig. 3A above of Giordano indicates the power loss mode during states S3, S1), during the second period (during period in state S1) of the first cycle, a current flowing through the fourth switch Q4 and through the second switch Q2, flows from the first output terminal OUT1 to the second output terminal OUT2 through the motor 2 -- see Giordano, Fig. 2 and equivalent illustrated Fig. 3A above, during states S3, S1).
For claim 10, Mizukami in view of Giordano disclose the driving circuit of claim 7, wherein a second cycle has the first period and the second period (equivalent illustrated Fig. 3B above of Giordano disclose a second cycle has the first period (during period in state S3) and the second period (during period in state S1));
wherein in the normal operation mode, during the first period of the second cycle, the second switch and the third switch are turned on, and during the second period of the second cycle, the second switch and the fourth switch are turned on (Figs. 1-2 of Mizukami in view of equivalent illustrated Fig. 3B above of Giordano disclose, in the normal operation mode (see Mizukami, Figs. 12, paragraphs [0047]-[0048], [0058] and [0062]; and see Giordano, equivalent illustrated Fig. 3B above, during states S3, S1), during the first period (during period in state S3) of the second cycle (S3, S1), the second switch Q2 and the third switch Q3 are turn ON, and during the second period (during period in state S1) of the second cycle, the second switch and the fourth switch are turn ON -- see Mizukami, Figs. 1-2, paragraphs ([0047], lines 1-5; [0048]; [0058], lines 1-12; and [0062], lines 1-13); and see Giordano, equivalent illustrated Fig. 3B above, during states S3, S1);
wherein in the power loss mode, during the first period of the second cycle, the first switch and the fourth switch are turned on, during the second period of the second cycle, the second switch and the fourth switch are turned on (Figs. 1-2 of Mizukami in view of equivalent illustrated Fig. 3B above of Giordano disclose in the power loss mode, during the first period (during period in state S4) of the second cycle (S4, S2), the first switch Q1 and the fourth switch are turn ON, during the second period (during period in state S2) of the second cycle (S4,S2), the second switch and the fourth switch are turn ON -- see Mizukami, Figs. 1-2, ([0047], lines 5-11; [0049]; [0058], lines 12-18; and [0062], lines 13-19); and see Giordano, equivalent illustrated Fig. 3B above, during states S4, S2).
For claim 11, Mizukami in view of Giordano disclose the driving circuit of claim 10, wherein in the power loss mode, during the first period of the second cycle, a current flowing through the fourth switch, flows from the second output terminal to the first output terminal through the motor, and through the first switch (Fig. 2 and equivalent illustrated Fig. 3B above of Giordano disclose, in the power loss mode, during the first period (during period in state S4) of the second cycle (S4, S2), a current flowing through the fourth switch Q4, flows from the second output terminal OUT2 to the first output terminal OUT1 through the motor 2, and through the first switch Q1).
For claim 12, Mizukami in view of Giordano disclose the driving circuit of claim 10, wherein in the power loss mode, during the second period of the second cycle, a current flowing through the second switch and through the fourth switch, flows from the second output terminal to the first output terminal through the motor (Figs. 1-2 of Mizukami in view of equivalent illustrated Fig. 3B above of Giordano disclose, in the power loss mode, during the second period (during period in state S2) of the second cycle (S4,S2), a current flowing through the second switch Q2 and through the fourth switch Q4, flows from the second output terminal OUT2 to the first output terminal OUT1 through the motor 2 -- see Giordano, equivalent illustrated Fig. 3B above, during states S4, S2).
For claim 15, Mizukami discloses a driving circuit for a motor (Figs. 1-2 of Mizukami disclose a driver circuit (10,20) for a motor 2 – see Mizukami, Figs. 1-2, paragraphs [0019]-[0022], [0054.-[0057] and [0059]-[0061])), the driving circuit (10,20) comprising:
a first switch and a second switch coupled in series (Fig. 2 of Mizukami discloses a first switch 11 and a second switch 12 coupled in series);
a third switch and a fourth switch coupled in series (Fig. 2 of Mizukami discloses a third switch 21 and a fourth switch 22 coupled in series);
a driving control circuit configured to control the first switch, the second switch, the third switch, and the fourth switch in response to a PWM signal (Fig. 2 of Mizukami discloses a driver control circuit (13,23) configured to control the first switch 11, the second switch 12, the third switch 21, and the fourth switch 22 in response to a PWM signal (PWM1, PWM2 – see Mizukami, Figs. 1-2, paragraphs [0022], [0054]-[0057] and [0059]-[0061]);
a first output terminal configured to couple a common node of the first switch and the second switch to a first terminal of the motor (Fig. 2 of Mizukami discloses a first output terminal 10a configured to couple a common node of the first switch 11 and the second switch 12 to a first terminal of the motor 2 -- see Mizukami, Fig. 2, paragraphs [0021] and [0055]-[0056]); and
a second output terminal configured to couple a common node of the third switch and the fourth switch to a second terminal of the motor (Fig. 2 of Mizukami discloses a second output terminal 20a configured to couple a common node of the third switch 21 and the fourth switch 22 to a second terminal of the motor 2 -- see Mizukami, Fig. 2, paragraphs [0021] and [0060]-[0061]).
Mizukami discloses the PWM signal (PWM1, PWM2) which is a high logic level and/or a low logic level (see Mizukami, Fig. 2, paragraphs [0058], [0062] and [0066]). Mizukami is silent for disclosing a first cycle has a first period and a second period, the PWM signal is at a high logic level during the first period, and the PWM signal is at a low logic level during the second period.
However, Giordano discloses a motor control system (see Giordano, Fig. 1, col. 1, lines 11-24) which is similar as Mizukami’s motor control system. Giordano discloses a first cycle has a first period and a second period, the PWM signal is at a high logic level during the first period, and the PWM signal is at a low logic level during the second period (Figs. 1-3 of Giordano disclose a first cycle (For example, a cycle includes states S2 and S4 as shown in Fig. 3) has a first period (during state S2) and a second period (during state S4), the PWM signal is at a high logic level (for example, Fig. 3, Q1 is ON) during the first period (Fig. 3, during a state S4), and the PWM signal is at a low logic level (for example, Fig. 3, Q1 is OFF) during the second period (during a state S2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify teaching of Mizukami to incorporate teaching of Giordano for purpose of providing erroneous fault detection to be minimized in different operating conditions of the load during certain windows of time.
Mizukami in view of Giordano disclose the driver circuit,
wherein in a normal operation mode, during the first period of the first cycle, a voltage at the first output terminal is of a first voltage level and a voltage at the second output terminal is of a second voltage level, and during the second period of the first cycle, the voltage at the first output terminal and the voltage at the second output terminal are of the second voltage level (Fig. 2 and equivalent illustrated Fig. 3A of Giordano disclose, in the normal operation mode (equivalent illustrated Fig. 3A above of Giordano indicates the normal operation mode during states S4, S2), during the first period (during period in state S4) of the first cycle, a voltage (OUT1) at the first output terminal 22 is of a first voltage level (High) and a voltage (OUT2) at the second output terminal 24 is of a second voltage level (Low), and during the second period (during period in state S2) of the first cycle, the voltage (OUT1) at the first output terminal 22 and the voltage (OUT2) at the second output terminal 24 are of the second voltage level (Low) -- see Giordano, Fig. 2 and equivalent illustrated Fig. 3A above, during states S4, S2);
wherein in a power loss mode, during the first period of the first cycle, the voltage at the first output terminal is of the second voltage level and the voltage at the second output terminal is of the first voltage level, and during the second period of the first cycle, the voltage at the first output terminal and the voltage at the second output terminal are of the second voltage level (Fig. 2 and equivalent illustrated Fig. 3A of Giordano disclose, in the power loss mode (equivalent illustrated Fig. 3A above of Giordano indicates the power loss mode during states S3, S1), during the first period (during period in state S3) of the first cycle, the voltage (OUT1) at the first output terminal 22 is of the second voltage level (Low) and the voltage (OUT2) at the second output terminal 24 is of the first voltage level (High), and during the second period (during period in state S1) of the first cycle, the voltage (OUT1) at the first output terminal 22 and the voltage(OUT2) at the second output terminal 24 are of the second voltage level (Low) -- see Giordano, Fig. 2 and equivalent illustrated Fig. 3A above, during states S3, S1).
For claim 16, Mizukami in view of Giordano disclose the driving circuit of claim 15, wherein in the normal operation mode, during the first period of the first cycle, the first switch and the fourth switch are turned on, and during the second period of the first cycle, the second switch and the fourth switch are turned on (Fig. 2 of Mizukami in view of equivalent illustrated Fig. 3A of Giordano disclose, in a normal operation mode (see Mizukami, Fig. 2, paragraphs [0064] and [0066]; and see Giordano, equivalent illustrated Fig. 3A above, during states S4, S2), during the first period (during period in state S4) of the first cycle (S4, S2), the first switch Q1 and the fourth switch Q4 are turned on, and during the second period (during period in state S2) of the first cycle, the second switch Q2 and the fourth switch Q4 are turned on – see Mizukami, Fig. 2, paragraphs [0064] and [0066]; and see Giordano, equivalent illustrated Fig. 3A above, during states S4, S2);
wherein in the power loss mode, during the first period of the first cycle, the second switch and the third switch are turned on, and during the second period of the first cycle, the second switch and the fourth switch are turned on (Fig. 2 of Mizukami in view of equivalent illustrated Fig. 3A of Giordano disclose, in a power loss mode (see Mizukami, Fig. 2, paragraph [0070]; and see Giordano, equivalent illustrated Fig. 3A above, during states S3, S1), during the first period (during period in state S3) of the first cycle, the second switch Q2 and the third switch Q3 are turned on, and during the second period (during period in state S1) of the first cycle, the second switch Q2 and the fourth switch Q4 are turned on (see equivalent illustrated Fig. 3A of Giordano) – see Mizukami, Fig. 2, paragraph [0070]; and see Giordano, equivalent illustrated Fig. 3 below, during states S3, S1).
For claim 17, Mizukami in view of Giordano disclose the driving circuit of claim 15, wherein a second cycle has a first period and a second period (equivalent illustrated Fig. 3B above of Giordano disclose a second cycle has the first period (during period in state S3) and the second period (during period in state S1));
wherein in the normal operation mode, during the first period of the second cycle, the voltage at the first output terminal is of the second voltage level and the voltage at the second output terminal is of the first voltage level, and during the second period of the second cycle, the voltage at the first output terminal and the voltage at the second output terminal are of the second voltage level (Fig. 2 and equivalent illustrated Fig. 3B above of Giordano disclose, in the normal operation mode (equivalent illustrated Fig. 3B above of Giordano indicates the normal operation mode during states S3,S1), during the first period (during period in state S3) of the second cycle, a voltage (OUT1) at the first output terminal 22 is of a second voltage level (Low) and a voltage (OUT2) at the second output terminal 24 is of a first voltage level (High), and during the second period (during period in state S1) of the second cycle, the voltage (OUT1) at the first output terminal 22 and the voltage (OUT2) at the second output terminal 24 are of the second voltage level (Low) -- see Giordano, Fig. 2 and equivalent illustrated Fig. 3B above, during states S3, S1);
wherein in the power loss mode, during the first period of the second cycle, the voltage at the first output terminal is of the first voltage level and the voltage at the second output terminal is of the second voltage level, and during the second period of the second cycle, the voltage at the first output terminal and the voltage at the second output terminal are of the second voltage level (Fig. 2 and equivalent illustrated Fig. 3B above of Giordano disclose, in the power loss mode (equivalent illustrated Fig. 3B above of Giordano indicates the power loss mode during states S4, S2), during the first period (during period in state S4) of the second cycle, the voltage (OUT1) at the first output terminal 22 is of the first voltage level (High) and the voltage (OUT2) at the second output terminal 24 is of the second voltage level (Low), and during the second period (during period in state S2) of the second cycle, the voltage (OUT1) at the first output terminal 22 and the voltage (OUT2) at the second output terminal 24 are of the second voltage level (Low) -- see Giordano, Fig. 2 and equivalent illustrated Fig. 3B above, during states S4, S2).
For claim 18, Mizukami in view of Giordano disclose the driving circuit of claim 17, wherein in the normal operation mode, during the first period of the second cycle, the second switch and the third switch are turned on, and during the second period of the second cycle, the second switch and the fourth switch are turned on (Figs. 1-2 of Mizukami in view of equivalent illustrated Fig. 3B above of Giordano disclose, in the normal operation mode (see Mizukami, Figs. 12, paragraphs [0047]-[0048], [0058] and [0062]; and see Giordano, equivalent illustrated Fig. 3B above, during states S3, S1), during the first period (during period in state S3) of the second cycle (S3, S1), the second switch Q2 and the third switch Q3 are turn ON, and during the second period (during period in state S1) of the second cycle, the second switch and the fourth switch are turn ON -- see Mizukami, Figs. 1-2, paragraphs ([0047], lines 1-5; [0048]; [0058], lines 1-12; and [0062], lines 1-13); and see Giordano, equivalent illustrated Fig. 3B above, during states S3, S1);
wherein in the power loss mode, during the first period of the second cycle, the first switch and the fourth switch are turned on, during the second period of the second cycle, the second switch and the fourth switch are turned on (Figs. 1-2 of Mizukami in view of equivalent illustrated Fig. 3B above of Giordano disclose in the power loss mode, during the first period (during period in state S4) of the second cycle (S4, S2), the first switch Q1 and the fourth switch are turn ON, during the second period (during period in state S2) of the second cycle (S4,S2), the second switch and the fourth switch are turn ON -- see Mizukami, Figs. 1-2, ([0047], lines 5-11; [0049]; [0058], lines 12-18; and [0062], lines 13-19); and see Giordano, equivalent illustrated Fig. 3B above, during states S4, S2).
Allowable Subject Matter
Claims 5-6, 13-14 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/THAI T DINH/Primary Examiner, Art Unit 2846
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