DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 01/20/2026 have been fully considered but they are not persuasive.
The Applicant contends that the prior art fails to disclose "a decoder circuit configured to detect and correct an error included in an output codeword based on a first syndrome, a second syndrome, and a third syndrome for identifying an error boundary between adjacent symbols of the output codeword," as recited in claim 1.
The Examiner disagrees and asserts Ha teaches a decoder that generates multiple syndromes (s1, s2, s3) to solve for error locators. Because these syndromes are derived from a parity check matrix H that covers the entirety of the codeword, the decoding logic inherently identifies the precise bit-position of an error. When an error occurs at the transition point between adjacent symbols, the error locator polynomial Λ(x) identifies that specific index. Therefore, the 'identification of an error boundary' is the functional result of the decoder's ability to resolve the exact bit-address of an error within the sequence.
Marrow (Fig. 1, Item 6) explicitly teaches a 'boundary error detection means.' This confirms that in the field of digital data recovery, it is known to specifically monitor the interface between data blocks (adjacent symbols) to detect transition-related errors. Combining Ha’s multi-syndrome correction with Marrow’s boundary-specific detection renders the claimed subject matter a predictable application of known error-correction techniques.
The Applicant contends that 'identifying an error boundary' is a distinct functional action. However, in the context of the claimed decoder, this 'identification' is merely the inherent output of a standard syndrome-based decoding process. As taught in Ha, calculating syndromes (s1, s2, s3) allows the decoder to locate errors with bit-level precision. When an error occurs at the transition between symbols, the location identified is the boundary. Because the prior art (Ha and Marrow) performs the same structural operations on the same data structures (codewords/symbols), the 'boundary' language is merely an intended use of a known apparatus.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over HA; Jeong-Seok et al. (US 20170004036 A1, hereafter referred to as HA) and Marrow; Marcus (US 5938790 A, hereafter referred to as Marrow).
Paragraphs [0021]-[0022] in HA teaches an error correction and detection decoder circuit configured to detect and correct errors included in an output codeword for memory based on a first syndrome a second syndrome and a third syndrome used for identifying error locations. The examiner would like to point out that a syndrome s are inherently defined by the equation s=Hc wherein H is a parity check matrix and c is a codeword. In addition, the error locations include errors at the boundary of codeword blocks.
Figure 1; and, claims 1, 4-5 and 7 on page 7 in Marrow, in an analogous art, teaches an error correction and detection decoder means comprising a boundary error detection means for detecting errors in a boundary between a first data block and a second data block., In addition, Figure 1 in Marrow teaches an encoder 3 for encoding data prior to storing it.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine HA with the teachings of Marrow by including use of a boundary error detection means for detecting errors in a boundary. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, because one of ordinary skill in the art would have recognized that use of a boundary error detection means for detecting errors in a boundary would have provided a means for correcting errors that span two codewords (column 6, lines 31-51 in Marrow).
Allowable Subject Matter
Claims 2-10 and 12-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the rejection of claims 1 and 11, above, identify the differences between the prior art and that which is found novel and/or nonobvious in dependent claims 2-10 and 12-20 since dependent claims inherit all the limitations of the claims from which they depend and any intervening claims
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20080104487 A1 is directed to an error detection method for compensating a syndrome based on error correction information of the received data rewritten by the error correction, the error detection method comprising: creating a first syndrome by using a cyclic code before error correction for received data in which a plurality of data units are arrayed each of which is constituted of a bit row constituted of a predetermined number of bits, storing beforehand, for each of the data units, a second syndrome which is computed in a case where an error exists at a specified bit position in the bit row; reading the second syndrome in the data unit pinpointed by the error correction information as containing the error; outputting a result of computations equivalent to a shift operation being performed by a linear feedback shift register for as many times as a bit difference as counted from an error bit position to the specified bit position in the data unit, by using the read second syndrome as an initial code; EXOR-ing the computation result output for each of the error bit positions and outputting it as a third syndrome; and EXOR-ing the first syndrome with the third syndrome; and, is a good 103 reference.
US 4604655 A is directed to A method of recording and reproducing a video format signal containing picture information, sound information and control information comprising: forming said control information as data indicative of identification numbers of sections of a two-dimensional picture format into which said sound information is to be inserted, recording said sound information and said control information on said recording medium in the form of binary signals each comprising a predetermined number of bits of data, modulating each of said binary signals before recordation on said recording medium such that the signal level is inverted between every adjacent two bits, reproducing the video format signal on said recording medium in a two-dimensional picture format which is divided into a plurality of sections having predetermined identification numbers respectively allocated thereto, said sections comprising at least one section for inserting said sound information in accordance with said control information, at least one section for inserting said control information and remaining sections for inserting said picture information, monitoring the inversions of signal level during reproduction of said picture and sound information; and signaling an occurrence of a burst error in response to a break in the regularity of inversions of signal level during reproduction of said picture and sound information; and, is a good teaching reference.
US 4468769 A is directed to An error correction system for correcting two simultaneous errors comprising: (a) an input terminal for receiving a code signal, (b) a data buffer for storing said code signal, (c) a first syndrome generation circuit for providing the first syndrome A.sub.1 from the code signal at the input terminal, (d) a second syndrome generation circuit for providing the second syndrome A.sub.2 from the code signal at the input terminal. (e) a correction inhibit circuit for detecting the condition that all the bit positions in said first syndrome A.sub.1 are zero, (f) means for providing a first bit train which shows an element .alpha..sup.n-t of a Galois field for each bit position in a code signal where n is a code length and t is an integer not larger than n for indicating a test bit; and, is a good 103 reference.
US 8972833 B1 is directed to An apparatus, comprising: a memory for storing encoded data; a decoder coupled to the memory to receive the encoded data; wherein the decoder comprises a block code matrix function configured to: generate syndrome information from the encoded data; and decode the encoded data to provide decoded data; wherein the block code matrix function of the decoder is further configured to: detect and correct a double adjacent bit error; and detect a triple adjacent bit error; wherein the block code matrix function of the decoder has a first syndrome, a second syndrome, and a third syndrome; wherein the first syndrome, the second syndrome, and the third syndrome are respectively associated with a single bit error space, a two adjacent bit error space, and a three adjacent bit error space; wherein the first syndrome and the second syndrome are configured to share a first common space; wherein the first syndrome and the third syndrome have mutually exclusive signatures; and wherein the third syndrome and the second syndrome are configured to share a second common space; wherein: the block code matrix function is configured to arrange data bits and parity bits of the encoded data in a matrix format to generate the syndrome information; the data bits and parity bits are for writing to and reading from memory cells of a memory array; to provide the syndrome information from the encoded data, the block code matrix function includes exclusive OR resources configured to exclusively OR: (n-1) different combinations of subsets of the data bits and an associated parity bit of the parity bits from the matrix format to generate each bit(n-1) syndrome bit for n a positive integer greater than one; and a combination of all of the data bits and all of the parity bits from the encoded data to generate a bit(n) syndrome bit; and the matrix format includes a significantly greater number of rows with a same number of columns with respect to a Hamming Code configuration of the data bits and the parity bits; and wherein the matrix format has approximately a 9-to-7 ratio of occupied cells to unoccupied cells of the memory cells; and, is a good 103 reference.
US 4604747 A is directed to An error correcting and controlling system used with a PCM decoder and comprising: (a) first syndrome generator means for generating a syndrome S.sub.1 given by the subsequently mentioned expression (1) on the basis of an error correcting word P and sampled words A.sub.n to A.sub.n+2, and B.sub.n to B.sub.n+2 which comprise data to be reproduced; (b) a second syndrome generator means for generating the product of a T.sup.i-7 and a syndrome S.sub.2 given by the subsequently mentioned expression (2) on the basis of an error correcting word Q and said sampled words A.sub.n to A.sub.n+2, and B.sub.n to B.sub.n+2 ; (c) a third syndrome generator means operatively connected to said first and second syndrome generator means and consisting of an adder used to generate a syndrome S.sub.i given by the subsequently mentioned expression (3) on the basis of outputs from said first and second syndrome generator means; and, is a good 103 reference.
US 20140195881 A1 is directed to A decoder, comprising: a syndrome generator for receiving a set of encoded bits and generating a corresponding set of syndromes based on a clock signal; a key equation solver, connected to the syndrome generator, for determining an error location polynomial using the set of syndromes, wherein the key equation solver determines first through fourth coefficients of the error location polynomial, and wherein each of the first through fourth coefficients include first through fifth bits, wherein the key equation solver comprises: a first polynomial basis multiplier circuit for determining a first product that is a product of first and second syndromes; a first finite field inversion circuit for determining a first inverse that is a multiplicative inverse of the first syndrome; a first finite field adder circuit, connected to the first polynomial basis multiplier circuit, for determining a first finite field sum that is a sum of the first product and a third syndrome; a second finite field inversion circuit connected to the first adder circuit, for determining a second inverse that is a multiplicative inverse of the first sum; a second polynomial basis multiplier circuit, connected to the first adder circuit and the first inversion circuit, for determining a second product that is a product of the first sum and the first inverse; a third polynomial basis multiplier circuit, connected to the second polynomial basis multiplier circuit, for determining a third product that is a product of the second product and the third syndrome; a fourth polynomial basis multiplier circuit for determining a fourth product that is a product of the first syndrome and a fourth syndrome; a second finite field adder circuit, connected to the fourth polynomial basis multiplier circuit, for determining a second finite field sum that is a sum of the fourth product and a fifth syndrome; a third finite field adder circuit, connected to the second finite field adder circuit and the third polynomial basis multiplier circuit, for determining a third finite field sum that is a sum of the third product and the second finite field sum; a fifth polynomial basis multiplier circuit, connected to the third finite field adder circuit and the second finite field inversion circuit, for determining a fifth product that is a product of the third finite field sum and the second finite field inverse; a fourth finite field adder circuit, connected to the second and fifth polynomial basis multiplier circuits, for determining a fourth finite field sum that is a sum of the second and fifth products; and a sixth polynomial basis multiplier circuit, connected to the fifth polynomial basis multiplier circuit, for determining a sixth product that is a product of the fifth product and the first syndrome, wherein the first coefficient is the first syndrome, the second coefficient is the fourth finite field sum, the third coefficient is the sixth product, and the fourth coefficient is binary one; a serial bit register for receiving the set of encoded bits and outputting an encoded bit at each active edge of the clock signal; an error bit locator, connected to the key equation solver, for identifying an erroneous encoded bit by generating an error match bit based on the first through fourth coefficients of the error location polynomial; and a first XOR gate, connected to the serial bit register and the error bit locator, for generating a decoded bit based on the encoded bit and the error match bit; and, is a good teaching reference.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH D TORRES whose telephone number is (571)272-3829. The examiner can normally be reached Monday-Friday 10-7 PT.
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/JOSEPH D TORRES/Primary Examiner, Art Unit 2112