DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 3/16/2026 have been fully considered but they are not persuasive.
With respect to claim 2 Applicant cites paragraph 9 of Lu and argues one of ordinary skill would recognize the threshold voltages of the resistive memory device of Lu is predetermined and “in order to write data into the resistive memory device of Lu, a write voltage greater than the threshold voltage is applied” and therefore “there is no indication that the “threshold voltage” of the resistive memory device of Lu is being programmed”.
The Examine respectfully disagrees with Applicants argument. Applicant is reminded that although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
The claim states “wherein the threshold voltages of the array of memory cells are programmable to represent the weight matrix.” The claim does not discuss specific individual threshold voltages but the threshold voltages of the array being programmable. Paragraph 9 and 15 of Lu discusses each resistive memory has an associated threshold voltage and is configured to store a data value as a resistance value through selective application of write voltages. The Examiners cited paragraph 59 then states that combinations of those memories then store values to make the weights. Thus, the threshold voltages are at least “programmable” as required by their selective application to different memories to create the weights.
In view of Applicant’s amendments there are no further objections to claims 4 or 14.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 2-3 and 12-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Application Publication 2018/0095930 A1 to Lu et al.
With respect to claim 2 Lu discloses, in Fig. 1-17, a device, comprising: an array of memory cells configured to store a weight matrix (paragraph 40 and 59; were a resistive array of memory cells is provided to store data which includes weighting matrix is the processing includes neural network operation); voltage drivers connected to the array of memory cells (paragraph 48; where a voltage is applied to memories that are to be made active); current digitizers coupled to the array of memory cells (paragraph 48 and 57; where currents are digitized of the current summations to perform processes); and a logic circuit configured to cause the voltage drivers to apply voltages to the array of memory cells and process outputs of the current digitizers to generate image data (paragraph 48, 62 and 68; where the outputs are used to image processing to generate corrected/compressed images); wherein threshold voltages of the array of memory cells are programmable to represent the weight matrix (paragraph 9, 15 and 59; where the memories hold data to mimic a neural network for processing data).
With respect to claim 3 Lu discloses, in Fig. 1-17, the device of claim 2, wherein the logic circuit is configured to program a threshold voltage of each respective memory cell in the array to: a first level to store a significant bit of a weight in response to the significant bit having a first value of one; or a second level above a predetermined read voltage to store the significant bit in response to the significant bit having a second value of zero; wherein the respective memory cell is configured to output a predetermined amount of current when read using the predetermined read voltage and when the threshold voltage of the respective memory cell is programmed to the first level; and wherein the respective memory cell is configured to output a negligible amount of current when not read (paragraph 47 and 74-75; where ones and zero are stored as resistive states and for operations only the ones are added).
Claims 12-13 are rejected for similar reasons as claims 2-3 above as they are corresponding method claims to those of apparatus claims 2-3.
Allowable Subject Matter
Claims 17-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
With respect to the independent claims the closest available prior art (US 2018/0095930 A1 to Lu et al) using memory cells and current digitizers to used stored weight matrix and digitized currents to generate image data (paragraph 15, 57, 64-68). However, Lu states (paragraph 69) that a lot of the attractive features start to vanish a at the system level.
Therefore, the prior art does not teach or fairly suggest:
With respect to claim 17 an apparatus, comprising: a first integrated circuit die having formed thereon an array of memory cells configured to store a weight matrix; a second integrated circuit die having formed thereon an image sensing pixel array configured to generate first image data; a third integrated circuit die having formed thereon at least one logic circuit connected between the image sensing pixel array and the array of memory cells; wherein the at least one logic circuit is configured to cause voltage drivers to apply voltages to the array of memory cells and process outputs of the current digitizers to generate image data.
Claims 18-20 are allowable for at least the reason that they depend from claim 17 which is allowable as discussed above.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claims 4-10 and 14-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL M PASIEWICZ whose telephone number is (571)272-5516. The examiner can normally be reached M-F 9 AM - 5:30 PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, George Eng can be reached at (571)272-7495. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL M PASIEWICZ/Primary Examiner, Art Unit 2699
May 1, 2026
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