Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This office action is in response to communication filed on 05/28/2026. Claims 1 and 11 have been amended. Claims 1-20 are pending on this application.
Response to Arguments
3. Applicant's arguments filed on 08/26/2026 have been fully considered but they are not persuasive.
Under remark, with respect to claims 1 and 11, applicant argued: “Paragraph 0043 of Zare Hoseini explains that the heterogeneous hardware configuration proposed therein can achieve various technical advantages, including high speed, low power consumption, reduced chip area, and relaxed component- matching requirements:
The modification proposed by the Office Action is to combine the capacitor switches in the balance circuits 1 a/1 b, 2a/2b, 3a/3b of Zare Hoseini with the capacitor switch circuits in each SAR ADC of Xu, thereby alleviating sampling mismatch between channels.
However, if the hardware configuration of Zare Hoseini were modified to use the same configuration for the respective voltage generators (i.e., the configuration relied upon from Xu), the resulting architecture would necessarily lose or undermine the advantages provided by the heterogeneous hardware configuration of Zare Hoseini.
Accordingly, modifying Zare Hoseini with the capacitor switch circuits in each SAR ADC of Xu, as proposed by the Office Action, would render Zare Hoseini unsatisfactory for its intended purpose. Consequently, there is no motivation to modify Zare Hoseini in view of Xu, and for at least this reason, the Office Action has failed to establish a prima facie case of obviousness for claim 1 over Zare Hoseini in view of Xu under 35 U.S.C 103. Therefore, claim 1 and all claims that depend from claim 1 are not rendered obvious over Zare Hoseini in view of Xu under 35 U.S.C 103, and independent claim 11 is a claim similar to claim 1. For reasons similar to those set forth above, claim 11 and all claims that depend from claim 1 are not unpatentable over Zare Hoseini in view of Xu under 35 U.S.C. 103”.
Examiner respectfully disagrees with the following:
The subject matter in Claims 1 and 11, “wherein a number of the plurality of comparison stages is equal to a number of the plurality of first capacitor switch circuits of each of the three DACs and the number of first capacitor switch circuits included in each of the three DACs is the same” is not new as taught by SAR ADC Fig. 1 of Xu.
Paragraph 0025 of Xu et al. discloses the motivation of Fig. 1 SAR ADC “improving the sampling precision and significantly reducing the complexity of a corresponding correction circuit. In the present disclosure, by using lower plates of capacitors for sampling, the sampling error caused by the charge injection effect is eliminated when the sampling switch is turned off, thereby further improving the sampling precision, allowing the use of a larger sampling switch, and further increasing the sampling speed of the ADC and providing better high-frequency performance compared with traditional techniques” (stated in office action mailed on 06/05/2026).
Since Zare Hseini and Xu et al. are common subject matter of number of comparator and DAC stages for SAR ADC; modifying Zare Hoseini with the same capacitor switch circuits in each SAR ADC of Xu, would render Zare Hoseini satisfactory for the purpose of “improving the sampling precision, allowing the use of a larger sampling switch, and further increasing the sampling speed of the ADC and providing better high-frequency performance compared with traditional” as suggested by paragraph 0025 of Xu et al..
From the explanation above, claims 1 and 11 are 35 U.S.C. 103 as being unpatentable over Zare Hoseini et al. in view of Xu et al. are proper. Accordingly, the rejections of Claims 1-6, 9-16 and 19-20 are sustained from the same references as applied from previous office action.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1-6, 10-16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Zare Hoseini et al. Pub. No. 2019/0253062 in view of Xu et al. Pub. No. 2022/0247423.
Regarding claim 1. Fig. 1 of Zare Hoseini et al. discloses A successive approximation register (SAR) analog-to-digital converter (paragraph 0027), configured to receive an input signal (Vin) and comprising: a digital-to-analog converter (DAC) array (1a/1b, 2a/2b,3a/3b), configured to receive the input signal (Vin) and comprising: three DACs (1a/1b, 2a/2b,3a/3b) configured to sample an input voltage level of the input signal (level of Vin), wherein each of the three DACs (1a/1b, 2a/2b,3a/3b) comprises a plurality of first capacitor switch circuits (capacitor switch circuits of each 1a/1b, 2a/2b, and 3a/3b) and three comparators (5, 6, 7) , respectively connected in series with the three DACs (1a/1b, 2a/2b,3a/3b), and configured to respectively generate a comparison result (result outputs of 5, 6, and 7); and a SAR logic circuit (4), coupled (13, 14, 15) to the DAC array (1a/1b, 2a/2b,3a/3b) and configured to generate the nth bit of a conversion result (bits output of SAR 4) according to the comparison result (result outputs of 5, 6, and 7) in an nth comparison stage (5, 6, 7), wherein in the nth comparison stage (5 or 6 or 7), the SAR logic circuit (4) is configured to: choose a first comparator (5) of the three comparators (5, 6, 7) to compare a sampling result of a first DAC (result of 1a, 1b) of the three DACs (1a/1b, 2a/2b,3a/3b)) with the voltage level (voltage level Vin) corresponding to a first (n-1) bits (paragraph 0038 discloses “voltage generator 1 and its comparator 5 can be used to distinguish between bit outcomes 00 and 01, voltage generator 2 and its comparator 6 can be used to distinguish between bit outcomes 01 and 10, and voltage generator 3 and its comparator 7 can be used to distinguish between bit outcomes 10 and 11”) of the conversion result (bits output of SAR 4), according to the comparison result of an (n-1) th comparison stage (5), to generate the comparison result (output of 5), and adjust sampling results (adjusting of 14 and 15) of a second DAC (2a/2b) and a third DAC (3a/3c) of the three DACs (1a/1b, 2a/2b,3a/3b)) corresponding to a second comparator (6) and a third comparator (7) of the three comparators (5, 6, 7) to the voltage levels (voltage level of Vin) respectively corresponding to the cases where the nth bit (bits output of SAR 4) of the conversion result is 0 and 1 (paragraph 0042), wherein n is a positive integer greater than 1 (paragraph 0041 discloses 12 bits).
However, Zare Hoseini et al. do not disclose wherein a number of the plurality of comparison stages is equal to a number of the plurality of first capacitor switch circuits of each of the three DACs and the number of first capacitor switch circuits included in each of the three DACs is the same.
Fig. 1 of Xu et al. discloses a successive approximation register (SAR) ADC (paragraph 00126) comprising: a number of the plurality of comparison stages (three comparison stages) is equal to a number of the plurality of first capacitor switch circuits (three capacitor switch circuits) of each of the three DACs (three capacitor switch circuits) and the number of first capacitor switch circuits (three capacitor switch circuits included in each of the three DACs (three capacitor switch circuits) is the same.
Zare Hoseini et al. and Xu et al. are common subject matter of the plurality of capacitor switch circuits for SAR ADC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertained to incorporate number of switch capacitor circuits of Xu et al. into Zare Hoseini et al. for the purpose of solves the problem in the traditional technology that sampling moments are mismatched due to different sampling signals in each of the time-interleaved channels, thereby improving the sampling precision and significantly reducing the complexity of a corresponding correction circuit. In the present disclosure, by using lower plates of capacitors for sampling, the sampling error caused by the charge injection effect is eliminated when the sampling switch is turned off, thereby further improving the sampling precision, allowing the use of a larger sampling switch, and further increasing the sampling speed of the ADC and providing better high-frequency performance compared with traditional techniques (paragraph 0025 of Xu et al.)
Regarding claim 2. Zare Hoseini et al. and Xu et al. applied to claim 1 above, Fig. 1 of Zare Hoseini et al. further discloses wherein the DAC array ((1a/1b, 2a,2b,3a/3b ) further comprises: three sampling switch circuits (three samples switches of 1a/1b, 2a,2b,3a/3b) respectively coupled between the input signal and the three DACs (1a/1b, 2a,2b,3a/3b), wherein the three DACs (1a/1b, 2a,2b,3a/3b) are configured to be turned on in a sampling stage according to a sampling signal to make the DAC array (1a/1b, 2a,2b,3a/3b ) sample the input signal (sampling signal for Vin), and configured to be turned off according to the sampling signal (Switching off from Vin for connection to Vref or Ground in each 1a/1b, 2a,2b,3a/3b ) in the plurality of comparison stages (5, 6, 7).
Regarding claim 3. Zare Hoseini et al. and Xu et al. applied to claim 1 above, Fig. 1 of Zare Hoseini et al. further discloses: the plurality of first capacitor switch circuits (switching capacitors of each 1a, 2a,3a), wherein the plurality of first capacitor switch circuits (switching capacitor of 1a/1b) of each of the three DACs (1a/1b, 2a,2b,3a/3b) are coupled to each other in parallel and coupled to an input terminal of a corresponding one of the three comparators (+/- input terminals of each comparator 5, 6, 7), and are configured to be respectively coupled to a reference voltage or a ground voltage (Verf and ground of each switching capacitors) according to a plurality of control signals (13, 14, and 15).
Regarding claim 4. Zare Hoseini et al. and Xu et al. applied to claim 3 above, Fig. 1 of Zare Hoseini et al. further discloses wherein the capacitance values of the plurality of first capacitor switch circuits of each of the three DACs form a geometric sequence (6C, 8C, 4C, 2C, C).
Regarding claim 5. Zare Hoseini et al. and Xu et al. applied to claim 3 above, Fig. 3 of Zare Hoseini et al. further discloses wherein each of the three DACs further comprises a plurality of second capacitor switch circuits (switching capacitors of each 1b, 2b,3b), wherein the number of the plurality of second capacitor switch circuits (switching capacitors of each 1b, 2b,3b) is equal to the number of the plurality of first capacitor switch circuits (switching capacitors of each 1a, 2a,3a), wherein the plurality of second capacitor switch circuits (switching capacitors of each 1b, 2b,3b) of each of the three DACs (1a/1b, 2a/2b,3a/3b) are coupled to each other in parallel and coupled to an another input terminal (+/- terminals of 5, 6, 7) of the corresponding one of the three comparators (5, 6, 7) , and are configured to be respectively coupled to the reference voltage or the ground voltage (Vref and Ground) according to the plurality of control signals (13, 14, 15)
Regarding claim 6. Zare Hoseini et al. and Xu et al. applied to claim 3 above, Fig. 1 of Zare Hoseini et al. further discloses wherein the number of the plurality of comparison stages (5, 6, 7) is equal to the number of the plurality of comparison results (3 results outputs of 5, 6, 7).
Regarding claim 10. Zare Hoseini et al. and Xu et al. applied to claim 1 above, Fig. 1 of Zare Hoseini et al. further discloses wherein the conversion result (conversion result of SAR 4) is an array comprising a plurality of bits (paragraph 0022), and each of the plurality of comparison results respectively corresponds to each of the plurality of bits (paragraph 0038).
Regarding claim 11. Fig. 1 of Zare Hoseini et al. discloses An operation method for operating a SAR ADC (paragraph 0027) , wherein the SAR ADC (Fig. 1) is configured to receive an input signal (Vin) and comprises a DAC array (1a/1b, 2a,2b,3a/3b) and a SAR logic circuit (SAR 4) , and the operation method comprises: (a) in an nth comparison stage (5, 6, 7), choosing (13) a first comparator (5) of three comparators of the DAC array (1a/1b, 2a,2b,3a/3b) by the SAR logic circuit (4), to compare (5) a sampling result of a first DAC (1a/1b) of three DACs of the DAC array (1a/1b, 2a/2b,3a/3b) with a voltage level (Vin) corresponding to a first (n-1) bits of a conversion result (, according to the comparison result of an (n-1)th comparison stage (5, 6, 7), to generate a comparison result (result of 5, 6, 7), and adjusting (switching to Vref or Gnd) sampling results of a second DAC (2a/2b) and a third DAC (3a/3b) of the three DACs (1a/1b, 2a/2b,3a/3b) corresponding to a second comparator (6) and a third comparator (7) of the three comparators (5, 6, 7) to the voltage levels (levels of 1a/1b, 2a,2b,3a/3b) respectively corresponding to the cases where a nth bit of the conversion result is 0 and 1 (1 (paragraph 0035 discloses” The output of the comparator is passed to the logic unit 4 which establishes in dependence on the comparison whether the most significant bit of the desired digital representation is a 0 or a 1” ) by the SAR logic circuit (SAR 4); (b) comparing the input signal (Vin) with the voltage level corresponding to the first (n-1) bits of the conversion result (paragraph 0038 discloses “voltage generator 1 and its comparator 5 can be used to distinguish between bit outcomes 00 and 01) by the first comparator (5), to generate the comparison result (result of 5); (c) generating the nth bit of the conversion result (bits generate by SAR 4) according to the comparison result (result of 5, 6, 7) by the SAR logic circuit (SAR 4); and (d) repeating steps (a)-(c) (paragraphs 0021-0022) , wherein the DAC array (1a/1b, 2a,2b,3a/3b ) is coupled between the input signal (Vin) and the SAR logic circuit (4), and the three comparators (5, 6, 7) are respectively connected in series with the three DACs (1a/1b, 2a,2b,3a/3b), wherein n is a positive integer greater than 1 (paragraph 0041 discloses 12 bits).
However, Zare Hoseini et al. do not disclose wherein a number of the plurality of comparison stages is equal to a number of the plurality of first capacitor switch circuits of each of the three DACs and the number of first capacitor switch circuits included in each of the three DACs is the same.
Fig. 1 of Xu et al. discloses a successive approximation register (SAR) ADC (paragraph 00126) comprising: a number of the plurality of comparison stages (three comparison stages) is equal to a number of the plurality of first capacitor switch circuits (three capacitor switch circuits) of each of the three DACs (three capacitor switch circuits) and the number of first capacitor switch circuits (three capacitor switch circuits included in each of the three DACs (three capacitor switch circuits) is the same.
Zare Hoseini et al. and Xu et al. are common subject matter of the plurality of capacitor switch circuits for SAR ADC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertained to incorporate number of switch capacitor circuits of Xu et al. into Zare Hoseini et al. for the purpose of solves the problem in the traditional technology that sampling moments are mismatched due to different sampling signals in each of the time-interleaved channels, thereby improving the sampling precision and significantly reducing the complexity of a corresponding correction circuit. In the present disclosure, by using lower plates of capacitors for sampling, the sampling error caused by the charge injection effect is eliminated when the sampling switch is turned off, thereby further improving the sampling precision, allowing the use of a larger sampling switch, and further increasing the sampling speed of the ADC and providing better high-frequency performance compared with traditional techniques (paragraph 0025 of Xu et al.).
Regarding claim 12. Zare Hoseini et al. and Xu et al. applied to claim 11 above, Fig. 3 of Zare Hoseini et al. further comprising: (e) in a sampling stage (sampling for Vin) , turning on three sampling switch circuits (sampling switches for Vin of 1a/1b, 2a/2b,3a/3b) of the DAC array (1a/1b, 2a/2b,3a/3b ) by a sampling signal (sampling signal for switching on/off Vin), to make the DAC array (1a/1b, 2a/2b, and 3a/3b) sample the input signal (Vin), and in the plurality of comparison stages (5, 6, 7) , turning off the three sampling switch circuits (switching off from Vin) by the sampling signal (sampling signal for switch on/off Vin), wherein the three sampling switch circuits sampling switch 1a/1b, 2a/2b,3a/3b) are respectively coupled between the input signal (Vin) and the three DACs (1a/1b, 2a/2b,3a/3b).
Regarding claim 13. Zare Hoseini et al. and Xu et al. applied to claim 11 above, Fig. 1 of Zare Hoseini et al. discloses wherein step (a) further comprises: respectively coupling a plurality of first capacitor switch circuits (switching capacitors circuit 1a, 2a, 3a) of the three DACs (1a, 2a, 3a) to a reference voltage or a ground voltage (Vref or Ground) by a plurality of control signals (13, 14, 15), wherein the plurality of first capacitor switch circuits (switching capacitor circuits) of each of the three DACs (switching capacitor circuits ) are coupled to each other in parallel and coupled to an input terminal (+/- terminal or each 5, 6, 7) of a corresponding one of the three comparators (5, 6, 7).
Regarding claim 14. Zare Hoseini et al. and Xu et al. applied to claim 13 above, Fig. 1 of Zare Hoseini et al. further discloses wherein the capacitance values of the plurality of first capacitor switch circuits (switching capacitors of 1a, 2a, 3a) of the three DACs (1a/1b, 2a/2b,3a/3b) form a geometric sequence (6C, 8C, 4C, 2C, C).
Regarding claim 15. Zare Hoseini et al. and Xu et al. applied to claim 11 above, Fig. 1 of Zare Hoseini et al. further discloses wherein step (a) further comprises: respectively coupling a plurality of second capacitor switch circuits (switching capacitor circuits 1b, 2b, 3b) of the three DACs (1a/1b, 2a/2b,3a/3b) to the reference voltage or the ground voltage (Vref or Ground) by the plurality of control signals (13, 14, 15), wherein the number of the plurality of second capacitor switch circuits ( is equal to the number of the plurality of first capacitor switch circuits, wherein the plurality of second capacitor switch circuits (1b, 2b, 3b) of each of the three DACs (1a/1b, 2a/2b,3a/3b) are coupled to each other in parallel and coupled to an another input terminal (+/- input terminal of 5, 6, 7) of the corresponding one of the three comparators (5, 6, 7).
Regarding claim 16. Zare Hoseini et al. and Xu et al. applied to claim 13 above, Fig. 1 of Zare Hoseini et al. further discloses wherein the number of the plurality of comparison stages (5, 6, 7) is equal to the number of the plurality of comparison results (3 results outputs of 5, 6, 7).
Regarding claim 20. Zare Hoseini et al. and Xu et al. applied to claim 11 above, Fig. 1 of Zare Hoseini et al. further discloses wherein step (c) comprises: generating the conversion result (conversion result of SAR 4) comprising an array (array of comparators 5, 6, 7) with a plurality of bits ((paragraph 0038 discloses “voltage generator 1 and its comparator 5 can be used to distinguish between bit outcomes 00 and 01, voltage generator 2 and its comparator 6 can be used to distinguish between bit outcomes 01 and 10, and voltage generator 3 and its comparator 7 can be used to distinguish between bit outcomes 10 and 11”) according to the conversion result by the SAR logic circuit (conversion result of SAR 4) , wherein each of the plurality of comparison results (results of 5, 6, 7) respectively corresponds to each of the plurality of bits (paragraph 0038 discloses “voltage generator 1 and its comparator 5 can be used to distinguish between bit outcomes 00 and 01, voltage generator 2 and its comparator 6 can be used to distinguish between bit outcomes 01 and 10, and voltage generator 3 and its comparator 7 can be used to distinguish between bit outcomes 10 and 11”).
6. Claims 9 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Zare Hoseini et al. and Xu et al. applied to claims 1 and 11 above, in view of Pelgrom et al. Pub. No. 2008/0309541.
Zare Hoseini et al. and and Xu et al.applied to claims 1 and 11 above, respectively, Fig. 3 of Zare Hoseini et al. further discloses wherein in a first comparison stage (5), the SAR logic circuit (4) is configured to choose at least one of the three comparators (5, 6, 7) for performing a comparison (5, 6, 7).
However, Zare Hoseini et al does not disclose choose a random one of the three comparators for performing a comparison.
Fig. 1 of Pelgrom et al. discloses a logic circuit (CO) is configured to choose a random one (paragraph 004 discloses “each comparator is selected to discriminate many or all input levels in accordance with a (pseudo) random mismatch-mitigating algorithm”) of the three comparators (C1, C2, C3) for performing a comparison (comparison of C1, C2, C3).
Zare Hosein et al., Xu et al. and Pelgrom et al. are common subject matter of plurality comparators of ADC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate random selection of each comparator of Pelgrom et al. into comparators of Zare Hosein et al./ Xu et al. for the purpose of mismatch-mitigating (paragraph 0004 of Pelgrom et al.).
Allowable Subject Matter
7. Claims 7 and 8 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior arts do not teach: wherein when the input signal is greater than or equal to the voltage level corresponding to the first (n-1) bits of the conversion result, the SAR logic circuit chooses the third comparator corresponding to the third DAC to perform a comparison in a (n+1)th comparison stage, and synchronously adjusts the two sampling results of the first DAC and the second DAC to the voltage level corresponding to the case where the nth bit of the conversion result is 1.
8. Claims 17 and 18 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior arts do not teach: wherein when the input signal is greater than or equal to the voltage level corresponding to the first (n-1) bits of the conversion result, the SAR logic circuit chooses the third comparator corresponding to the third DAC to perform a comparison in a (n+1)th comparison stage, and synchronously adjusts the two sampling results of the first DAC and the second DAC to the voltage level corresponding to the case where the nth bit of the conversion result is 1 by the SAR logic.
Conclusion
9. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Linh Van Nguyen whose telephone number is (571) 272-1810. The examiner can normally be reached from 8:30 – 5:00 Monday-Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Dameon E. Levi can be reached at (571) 272-2105. The fax phone numbers for the organization where this application or proceeding is assigned are (571-273-8300) for regular communications and (571-273-8300) for After Final communications.
10/08/2026
/LINH V NGUYEN/Primary Examiner, Art Unit 2845
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