Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA ..
DETAILED ACTION
This office acknowledges receipt of the following items from the Applicant:
Information Disclosure Statement (IDS) filed on 6/21/24 was considered.
Claims 1-20 are presented for examination.
Specification
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-29 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Redwine (US 4989055), embodiment of Figure 7 (Figs. 7–10E).
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Claims 1-4, 6, 8, 13-17, 20, 24-26 and 29, are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chung U.S. Patent No. 2025/0273261.
Regarding to claim 1, 13, 24 and 29, Chung discloses gain cell (fig. 2, 200) for storing a data level, comprising: a write element (fig. 2, write TR) connected to a write word line (fig. 2, WWL) and a bit line (BL), configured to write a logic level from said BL to a storage node (fig. 2, storage node (SN)) of said gain cell when a write operation is triggered on said WWL, said write element comprising at least one transistor (fig. 2, write TR transistor); and a read element (fig. 2, read TR) connected to a read word line (fig. 1A, RWL) and said bit line (fig. 2, BL), configured to read a logic level from said storage node (fig. 2, Storage node (SN) to said BL (fig. 2, BL) when a read operation is triggered on said RWL (fig. 1A, RWL), said read element comprising at least one transistor (fig. 2, read TR transistor).
With regard to claim 2 and 14, Chung discloses wherein a driver (fig. 3, S/A) is connected to said BL (fig. 3, BL’s), said driver being configured for setting said BL to said logic level prior to a write operation and for presetting a level of said BL to a preset level prior to a read operation (page 4, [0063], L10-18).
With regard to claim 3 and 15, Chung discloses wherein said BL is connected to a diffusion of at least one transistor of said write element and to a diffusion of at least one transistor of said read element (fig. 2, BL is connected to diffusion of write TR transistor and fig. 2, read TR transistor).
With regard to claim 4, 16 and 25, Chung discloses wherein said WWL is connected to a gate of at least one transistor of said write element (fig. 3, WWL is connected to a gate of write TR transistor).
With regard to claim 6 and 17, Chung discloses wherein said RWL is connected to a diffusion of at least one transistor of said read element (fig. 1A, RWL is connected to read TR transistor).
With regard to claim 8, 20 and 26, Chung disclose wherein said at least one transistor of said write element and said at least one transistor of said read element are field-effect transistors (FETs) (fig. 2, discloses write TR and read TR transistors are a FETs transistor type).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicants’ disclosure. AOKI et al (2025/0292826) a memory includes a first data-line and a first control-line for writing and a second data-line and a second control-line for reading. A memory cell includes a first transistor connected to the first control-line at a gate and connected to the first data-line, a second transistor connected to the second control-line at a gate and connected to the second data-line, and a third transistor connected to the first transistor at a gate and connected to the second transistor. A detector is connected to the first and second data-lines. In writing or reading, the controller activates the second control-line, the detector detects first data based on a voltage of the second data-line, and thereafter the controller activates the first control-line. After reception of a write command, the detector transmits second data from outside to33 the gate of the third transistor when latching the second data.
Giterman et al ((2025/0285672) discloses the gain cell (100) has a write transistor (110) with a first diffusion that is connected to a write bit line (WBL), a gate connected to a write word line (WWL) and a second diffusion. A storage transistor (120) is associated with the write transistor, and comprises a gate connected to the second diffusion of write transistor, a first diffusion connected to a read bit line (RBL), and a second diffusion. A read transistor (130) is associated with the storage transistor, and is provided with a gate connected to a read word line (RWL), a first diffusion connected to the second diffusion of storage transistor, and a second diffusion that is connected to a reference voltage. The storage transistor comprises a p-type transistor and an n-type transistor. The write transistor, storage transistor and read transistor are field-effect transistors, fin field-effect transistors, metal-oxide-semiconductor field-effect transistors and bulk field-effect transistors.
When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the date of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Connie Yoha, whose telephone number is (571) 272-1799. The examiner can normally be reached on Mon. - Fri. from 8:00 A.M. to 5:30 PM. The examiner's supervisor, Alexander Sofocleous, can be reached at (571) 272-0635. The fax phone number for this Group is (571) 273-8300.
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/CONNIE C YOHA/Primary Examiner, Art Unit 2825