Prosecution Insights
Last updated: April 19, 2026
Application No. 18/637,661

CLOCK SYNC INPUT DROPOUT PROTECTION

Non-Final OA §102§103
Filed
Apr 17, 2024
Examiner
JAGER, RYAN C
Art Unit
2842
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
3 (Non-Final)
90%
Grant Probability
Favorable
3-4
OA Rounds
2y 0m
To Grant
92%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allow Rate
824 granted / 921 resolved
+21.5% vs TC avg
Minimal +3% lift
Without
With
+3.0%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
14 currently pending
Career history
935
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
35.9%
-4.1% vs TC avg
§102
37.0%
-3.0% vs TC avg
§112
18.5%
-21.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 921 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Non-final communication in response to communication filed 12/11/25. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1 and 21 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Holler Jr [5559458]. With respect to claim 1, figure 1 of Holler Jr. discloses a circuit comprising: a pulse generator [200,400] having an input [/PUR] and an output [EN]; and an oscillator [100] having an input [/PUR] and an output [CK], the input of the oscillator coupled to the input of the pulse generator; and an output circuit [300] having a first input [CLOCKIN], a second input [CK], a third input [SELECT CLOCK or /PUR] and an output [CLOCK], the first input of the output circuit coupled to an external clock input, the second input coupled to the outputs of the pulse generator and the oscillator, and the output of the output circuit coupled to a clock output [CLOCK]. With respect to claim 21, figure 1 of Holler Jr. discloses the circuit of claim 1, wherein the output circuit includes a multiplexer [300, MUX]. Claims 18-20, 23,25 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Laur et al. [8570014]. With respect to claim 18, figures 1-10 of Laur et al. disclose a system comprising: a sync pin [EXT. CLOCK]; a clock generator [240,244,280,210] having an output [outputs of any of the elements]; an output circuit [220] having a first input, a second input, and an output, the first input coupled to the sync pin, and the second input coupled to the output of the clock generator; and a power stage [66,61] having an input coupled to the output of the output circuit. With respect to claim 19, figures 1-10 of Laur et al. disclose the system of claim 18, wherein the output circuit includes a multiplexer [logic gates Fig. 9 form a multiplexer]. With respect to claim 20, figures 1-10 of Laur et al. disclose the system of claim 18, wherein the power stage comprises: a controller [66] having an input; and a power converter [61] having an input coupled to the output of the output circuit [coupled through 66] and having an output [Vo] coupled to the input of the controller [coupled through 68]. With respect to claim 23, figures 1-10 of Laur et al. disclose the system of claim 18, wherein the clock generator includes a pulse generator [270] and an oscillator [210]. With respect to claim 25, figures 1-10 of Laur et al. disclose the system of claim 18, wherein the power stage is a first power stage [POWER MODULE 1] and the system further comprises a second power stage [POWER MODULE 2-N] having an input coupled to the sync pin [EXT. CLOCK]. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Laur et al. With respect to claim 24, figures 1-10 of Laur et al. disclose the system of claim 18, but does not disclose wherein the sync pin is a sync-out pin or a sync-in pin of a universal serial bus (USB) power delivery controller. However, it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2 USPQ2d 1647. Allowable Subject Matter Claims 10-16 are allowed. Claim 2-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN C JAGER whose telephone number is (571)272-7016. The examiner can normally be reached on 8:30 - 5:30 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lincoln Donovan can be reached on 571-272-7016. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RYAN JAGER/ Primary Examiner, Art Unit 2842 1/27/26
Read full office action

Prosecution Timeline

Apr 17, 2024
Application Filed
Jan 18, 2025
Non-Final Rejection — §102, §103
Apr 22, 2025
Response Filed
May 05, 2025
Non-Final Rejection — §102, §103
Aug 11, 2025
Response Filed
Dec 11, 2025
Request for Continued Examination
Dec 29, 2025
Response after Non-Final Action
Feb 06, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
90%
Grant Probability
92%
With Interview (+3.0%)
2y 0m
Median Time to Grant
High
PTA Risk
Based on 921 resolved cases by this examiner. Grant probability derived from career allow rate.

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