DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 10 is objected to because of the following informalities:
In claim 10, lines 1-2, “logging the first timestamp and the first timestamp” should be --logging the first timestamp-- to correct a typo.
Appropriate correction is required.
Notes on 35 USC 101
Claims 1-20 are eligible under 35 USC 101, as discussed below.
Claim 1 (as the representative) recites an abstract idea of “calculating a system management mode (SMM) latency based on a difference between the second timestamp at the exit point and the first timestamp at the entry point.” The claim recites additional elements of “receiving, by a processor, a system management interrupt (SMI) at an information handling system; if SMI telemetry is enabled, then reading a first timestamp at an entry point of the SMI; subsequent to handling the SMI, reading a second timestamp at an exit point of the SMI.” The additional elements are ordered computer operations for reading System Management Interrupt (SMI), and first timestamp and the second timestamp before and after SMI handling operation. They are not insignificant data collection, but particular steps in response to an SMI, and reading particular values, i.e., timestamps, at particular timings. The claim, as a whole, purports to improve the functionality (i.e., measuring SMM latency) of the computer itself. See MPEP2106.05(a). Therefore, the claims are eligible, See MPEP 2106.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 9-14, and 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by LUO et al. (CN 107423206 A; machine translation provided; hereinafter “LUO”).
Regarding claim 1, LUO teaches a method comprising:
receiving, by a processor, a system management interrupt (SMI) at an information handling system (i.e., “an SMI can the SMI # pin is effective by the processor or APIC … and then CPU will jump to the system firmware SMI handler to execute processing entry program”; see translation p.2, ¶ 1);
if SMI telemetry is enabled, then reading a first timestamp at an entry point of the SMI (i.e., “triggering the SMI interruption, firstly entering the SMM the processor reading the first TSC clock for counting the preset position stored in the memory as a first timestamp, wherein the first TSC clock is firstly enters in the SMM processor TSC clock”; see translation p. 2, ¶ 6; note that SMI telemetry is enabled because at least the first timestamp is recorded);
subsequent to handling the SMI, reading a second timestamp at an exit point of the SMI (i.e., “after the main processor executing the SMI interrupt SMI processing program corresponding to read a second TSC clock count as a second timestamp, wherein the main processor is a processor selected from the entering the SMM processor of the second TSC clock is the main processor of the TSC clock”; see translation p. 2, ¶ 7); and
calculating a system management mode (SMM) latency based on a difference between the second timestamp at the exit point and the first timestamp at the entry point (i.e., “wherein the execution time is the second time minus the first time stamp”; see translation p. 3, ¶ 1).
Regarding claim 2, LUO further teaches:
wherein the reading of the first timestamp is performed prior to handling the SMI (i.e., “triggering the SMI interruption, firstly entering the SMM the processor reading the first TSC clock for counting the preset position stored in the memory as a first timestamp”; see translation p. 2, ¶ 6).
Regarding claim 3, LUO further teaches:
determining whether the SMM latency is longer than another SMM latency (i.e., “the main processor judges the SMI interrupt to execution time is greater than the maximum time of SMI”; see translation p. 3, ¶ 1).
Regarding claim 4, LUO further teaches:
storing a value of the SMM latency if the SMM latency is longer than the other SMM latency (i.e., “if yes, the SMI maximum time then the main processor updates the OEMACPI table, the SMI accumulation time and the SMI trigger times, and exits the SMM”; see translation p. 3, ¶ 3).
Regarding claim 5, LUO further teaches:
wherein the storing of the value of the SMM latency includes overwriting a previous SMM latency (i.e., “if yes, the SMI maximum time then the main processor updates the OEMACPI table, the SMI accumulation time and the SMI trigger times, and exits the SMM”; see translation p. 3, ¶ 3).
Regarding claim 9, LUO further teaches:
incrementing an SMI counter (i.e., “updates the accumulated time and the SMI trigger times of SMI in the OEMACPI table”; see translation p. 3, ¶¶ 2-3).
Regarding claim 10, LUO further teaches:
logging the first timestamp and the first timestamp as SMI telemetry data (i.e., “stored into the memory as a first timestamp”; see translation p. 3, ¶ 11).
Regarding claim 11, the claim recites the same substantive limitations as claim 1 and is rejected by applying the same teachings. See LUO translation p. 8, lower section, regarding the embodiment in a computer system.
Regarding claim 12, the claim recites the same substantive further limitations as claim 3 and is rejected by applying the same teachings.
Regarding claim 13, the claim recites the same substantive further limitations as claim 4 and is rejected by applying the same teachings.
Regarding claim 14, the claim recites the same substantive further limitations as claim 5 and is rejected by applying the same teachings.
Regarding claim 17, the claim recites the same substantive limitations as claim 1 and is rejected by applying the same teachings. See LUO translation p. 8, lower section regarding the embodiment in a computer-readable medium.
Regarding claim 18, the claim recites the same substantive further limitations as claim 3 and is rejected by applying the same teachings.
Regarding claim 19, the claim recites the same substantive further limitations as claim 4 and is rejected by applying the same teachings.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6, 15, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over LUO in view of ZHANG (CN 113110953 A; machine translation provided).
Regarding claim 6, the prior art applied to the preceding linking claim(s) teaches the features of the linking claim(s).
LOU does not explicitly disclose:
wherein the value of the SMM latency is stored in a complex programmable logic device register.
But ZHANG teaches:
storing abnormal information of a node in a register of CPLD (see abstract).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify LUO in view of ZHANG by incorporating a CPLD such that the value of the SMM latency is stored in a complex programmable logic device register, as claimed. The rationale would be to facilitate monitoring a node by a BMC (see ZHANG, abstract)
Regarding claim 15, the claim recites the same substantive further limitations as claim 6 and is rejected by applying the same teachings.
Regarding claim 20, the claim recites the same substantive further limitations as claim 6 and is rejected by applying the same teachings.
Claims 7, 8, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over LUO in view of TANG et al. (CN 116185799 A; machine translation provided; hereinafter “TANG”).
Regarding claim 7, LUO further teaches:
wherein the value of the SMM latency is stored in a buffer (i.e., “updates the OEMACPI table”; see translation p. 3, ¶¶ 3 and 7)
LUO does not explicitly disclose (see only the underlined):
wherein the value of the SMM latency is stored in a buffer accessible by a baseboard management controller.
But TANG teaches:
wherein the value of the SMM latency is stored in a buffer (i.e., “stores the SMI total time to the shared memory”) accessible by a baseboard management controller (i.e., “the BMC time analysis module obtains the IPMI sending information from the shared memory”; see translation p. 2, middle section).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify LUO in view of TANG by incorporating the OEMACPI table in a shared memory, such that the value of the SMM latency is stored in a buffer accessible by a baseboard management controller, as claimed. The rationale would be to help obtaining the latency information without additional obtaining OS login authority (see TANG, Abstract)
Regarding claim 8, LUO further teaches:
wherein the value of the SMM latency is provided as telemetry data (i.e., “the operating system can be OEMACPI table to obtain the desired parameters and the analysis result for measuring system performance”; see translation p. 4, lower section)
LUO does not explicitly disclose (see only the underlined):
wherein the value of the SMM latency is provided as telemetry data by a baseboard management controller.
But TANG teaches:
wherein the value of the SMM latency is provided as telemetry data by a baseboard management controller (i.e., “stores the SMI total time to the shared memory… the BMC time analysis module obtains the IPMI sending information from the shared memory”; see translation p. 2, middle section).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify LUO in view of TANG by sharing the latency information, such that the value of the SMM latency is provided as telemetry data by a baseboard management controller, as claimed. The rationale would be to facilitate obtaining the latency information without additional obtaining OS login authority (see TANG, Abstract)
Regarding claim 16, the claim recites the same substantive further limitations as claim 7 and is rejected by applying the same teachings.
Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
HSU et al. (US 20230205574 A1) teaches a method for storing data associated with a system management interrupt (SMI) in a computer system. The SMI data is converted to an accessible format. The converted SMI data is stored in a memory with timestamp and type attributes of SMI.
Kydles et al. (US 20120174122 A1) teaches a method that tests a real-time behavior of an operating system having a first time system (e.g., a SMI tracer real-time extension) responsible for the real-time behavior of the operating system, involving registering the time and duration of an SMI.
LU et al. (CN 102053907 A; also US 20110107072 A1) teaches a self-diagnostic method of an SMI processing program, involving calculating processing time of the SMI processing program by a difference between a first time value and a second time value; and recording relative information of the SMI if the processing time is not less than an overtime time.
Conclusion
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/JOHN C KUAN/Primary Examiner, Art Unit 2857
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