DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-7, 9-10, 13-14, 17-18, 23 and 25 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Consoer et al. (USPN 10,425,075).
With respect to claim 1, in Figs. 1, 2 and 6, (note Fig. 6 drives the gate of 20 of Fig. 2 and Fig. 2 is used within 20 of Fig. 1) circuit (Fig. 1 with Fig. 2 and Fig. 6) comprising:
a transistor (20 of Fig. 1) coupled between a first terminal (drain terminal of 20, se drain of 210 of Fig. 6) and a second terminal (source terminal of 20, see Fig. 2 and the circuit of Fig. 6), the transistor having a transistor control terminal (gate terminal of 20, note the gate of the power FET of Fig. 6 is mislabeled as “Power-FET gain”, see Col. 16 lines 31-34); and
a resistor (238 of Fig. 6) and a first switch (236) coupled between the transistor control terminal (gate of the power FET 20, se Col. 16 lines 31-34) and the second terminal (source, see “Power-FET source” of Fig. 6), the first switch having a switch control terminal (gate of 236) and a first switch terminal coupled to the second terminal (source connected to the power FET source via 238);and
a second switch coupled between the switch control terminal and the second terminal (242).
With respect to claim 2, the circuit of claim 1, wherein the transistor is a first transistor (20 is a transistor), and the transistor control terminal is a first transistor control terminal (gate of 20); and
wherein the first switch includes a second transistor (transistor of 236) having a second transistor control terminal as the switch control terminal (gate of 236).
With respect to claim 3, the circuit of claim 2, wherein the second switch includes a third transistor (transistor of 242) having a first terminal (drain) coupled to the second transistor control terminal (gate of 236), a second terminal coupled to the second terminal of the second transistor (source connected to the source of the power-FET 20), and a control terminal coupled to the second terminal of the third transistor (drain connected to gate of 236).
With respect to claim 4, the circuit of claim 3, wherein the resistor is a first resistor (238 is a first resistor), and the circuit further comprises a second resistor (262) coupled between the second transistor control terminal and the first terminal of the third transistor (the terminal of 262 connected to node 226 is connected between the gate of 236 and drain of 242 at node 226, thus the resistor is connected as claimed at said terminal of the resistor).
With respect to claim 6, the circuit of claim 1, further comprising , a third switch (232) coupled between the switch control terminal (gate of 236) and a third terminal (VSUPPLY terminal).
With respect to claim 7, the circuit of claim 6, wherein the circuit further comprises a first pull-up circuit (220 which is responsible, at least in part, for pulling up the gate of the power FET to the drain voltage and thus is a “first pull-up circuit”) and a second pull-up circuit coupled to the transistor control terminal (210 which is responsible, at least in part, for pulling up the gate of the power FET to the drain voltage and thus is a “second pull-up circuit” and is connected to the gate via 220).
With respect to claim 9, a circuit (Figs. 1, 2 and 6) comprising:
a transistor (20 of Fig. 2) coupled between a first terminal (drain, see Power-FET drain of Fig. 6) and a second terminal (source, see Figs. 2 and 6), the transistor having a transistor control terminal (gate terminal);
a resistor and a first switch coupled between the transistor control terminal and the second terminal (236 with 238), the first switch having a switch control terminal (gate of 236);
a second switch coupled between the switch control terminal and the second terminal (242);and
a control circuit having an output coupled to the switch transistor control terminal (210, 220, Enable Ramp-down generator and 270 and 290. 290 is connected to the gate of 236),
With respect to claim 10, the circuit of claim 9, wherein the transistor is a first transistor (20 is a first transistor), and the transistor control terminal is a first transistor control terminal (gate of 20);
wherein the first switch includes a second transistor (236 is a second transistor) having a second transistor control terminal as the switch control terminal (gate of 236); and
wherein the circuit includes a third switch (232) coupled between the second transistor control terminal (gate of 236) and a third terminal (VSUPPLY).
With respect to claim 13, (Currently Amended) The circuit of claim 9, wherein the second switch includes a third transistor (242 is a third transistor), the third transistor having a control terminal coupled to the second terminal (via 248).
With respect to claim 14, the circuit of claim 13, wherein the resistor is a first resistor (238 is a first resistor), and the circuit includes a second resistor (262) coupled between the second transistor switch control terminal and the third transistor (the terminal of 262 connected to 226 is connected between 242 and 236 at node 226. Thus, the resistor is connected as claimed).
With respect to claim 17, a system (system of Figs. 1, 2 and 6) comprising:
a power source (power source coupled to the Power-FET drain, see Fig. 6) having an output (output connected to the drain, PMOS transistors of 210 and 220 must be powered to operate. Thus, the power source is connected to the source of the PMOS transistors);
a circuit (Figs. 2 and 60, i.e., 20 of Fig. 2 within Fig. 1 and the circuit of Fig. 6 for driving the gate of 20) having a first terminal coupled to the output of the power source (drain), and a second terminal (source), the circuit including:
a transistor coupled between the first and second terminals (20 of Figs. 1 and 2), the transistor having a transistor control terminal (gate);
a resistor (238 of Fig. 6) and a first switch coupled between the transistor control terminal and the second terminal (236), the first switch including a switch control terminal (gate of 236); and
a second switch coupled between the switch control terminal and the second terminal (242); and
a load circuit having an input coupled to the second terminal (load of Fig. 1, i.e., at least one of L1 and 36 of Fig. 1) .
With respect to claim 18, the system of claim 17, wherein:
the transistor is a first transistor (20 is a first transistor), and the transistor control terminal is a first transistor control terminal (gate of 20);
the resistor is a first resistor (238 is a first resistor);
the first switch includes a second transistor (242 is a second transistor) having a second transistor control terminal as the switch control terminal (gate of 242);
the second switch includes a third transistor (242) having a first terminal (source), a second terminal coupled to the second transistor control terminal (drain), and a control terminal (gate) coupled to the first terminal of the third transistor (via 248); and
the circuit includes a second resistor coupled between the second transistor control terminal and the second terminal of the third transistor (262 having a terminal coupled between the drain of 242 and the gate of 236 at node 226 and thus connected as claimed).
With respect to claim 23, the circuit of claim 1, wherein the first switch is configurable to:
enable a current path from the transistor control terminal to the second terminal via the resistor responsive to the switch control terminal having a first state (when gate of 236 is high 236 is enabled such that 236 and 238 connected the power FET gate to the power FET source); and
disable the current path responsive to the switch control terminal having a second state (the current path is disabled when the gate voltage of 236 is low).
With respect to claim 25, the system of claim 17, wherein the first switch is configurable to:
enable a current path from the transistor control terminal to the second terminal via the resistor responsive to the switch control terminal having a first state (when the gate of 236 is high and 236 is active), and
disable the current path responsive to the switch control terminal having a second state (when the gate of 263 is low and 236 is off).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5, 15 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Consoer et al. (USPN 10,425,075) in view of Teggatz et al. (USPAPN 2012/002572).
With respect to claim 5, 15 and 19, Consoer et al. fails to explicitly disclose the type of transistors used to construct the circuitry of Figs. 1, 2 and 6. Thus, Consoer et al. fails to disclose, with respect to claim 5, “wherein at least one of the second or third transistor is a natural transistor”; with respect to claim 15, “wherein the third transistor is a natural transistor”; and, with respect to claim 19, “wherein at least one of the second transistor or the third transistor is a natural transistor”
However, a natural transistor is old and well-known transistor technology, wherein natural transistors have a low threshold voltage and allow for, among other things, the maximization of headroom in low-voltage conditions. This is further evidenced in paragraph 0024 of Teggatz et al.
It would have been obvious to one of ordinary skill in the art to construct all of the transistors of the circuitry of Figs. 1, 2 and 6 of Consoer et al. with natural transistors for the purpose of having low threshold transistors that allow for the maximization of headroom in low-voltage operating conditions when such low-voltage conditions are desired/required.
As modified above the transistors as recited in claims 5, 15 and 19 will be natural transistors.
Allowable Subject Matter
Claims 8, 11-12, 16, 20-22 and 24 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas J. Hiltunen whose telephone number is (571)272-5525. The examiner can normally be reached 9:00AM-5:30PM EST M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at (571)270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/THOMAS J. HILTUNEN/ Primary Examiner, Art Unit 2836
Prosecution Insights